JP2002140893A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Problem] Flash E that can significantly reduce rewriting time
An EPROM is provided. SOLUTION: A page programming latch circuit 108a, 108 is provided for each bit line BL1, BL2, BL3.
b, 108c, and selectively switches the source lines 110a, 110b of the memory cells on the same row controlled by the output of the row decoder 106.
9 connected to the source line selection transistors 111a and 111
1b, a source line switching circuit 10 for a source of a memory cell on a word line WL selected by an address signal.
9, a negative high voltage is applied to erase the information in the memory cell, VSS is applied to the source connected to the source line switching circuit 109, and according to the write information latched by the latch circuit 108. The page programming for 1WL is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable / erasable nonvolatile semiconductor memory device, and more particularly, to a flash EE capable of greatly shortening a rewriting time.
Regarding PROM.

[0002]

2. Description of the Related Art A conventional batch erase nonvolatile semiconductor memory device will be described. In FIG. 4, a plurality of rows of memory cell arrays 312 in which a plurality of memory cells each including a transistor having a floating gate are arranged are provided. Around the memory cell array 312, there are provided a row decoder 306 for selecting a word line WL, a column decoder 307 for selecting a bit line BL, and a sense amplifier 304 for reading data of a memory cell. When writing to a memory cell, the write control circuit 303 applies a program voltage to each of the bit line BL and the word line WL, and the erase control circuit 302 applies a voltage for erasing the written data to a source line of the memory cell. Is applied. The verify circuit 305 reads data written in the memory cell array 312 and performs verification. The control circuit 301 controls each operation of the erase control circuit 302, the write control circuit 303, and the verify circuit 305 based on an externally applied control signal.

Next, the writing and erasing operations in such a conventional device will be described. FIG. 6 shows a cross section of a memory cell in the memory cell array 312 of FIG.
Is a control gate, 504 is a source diffusion region (hereinafter simply referred to as a source) formed in the semiconductor substrate 506,
Reference numeral 503 denotes a drain diffusion region (hereinafter, simply referred to as a drain) formed in the semiconductor substrate 506. Here, a thin oxide film (not shown) is formed between the floating gate 502 and the semiconductor substrate 506, and the floating gate 50 is formed by utilizing a tunnel phenomenon.
The electron can be moved to 2.

Next, the operation of the memory cell will be described.
During programming, drain 503 and control gate 5
01 and a program voltage of about 6.3 V and VBB (−9.
0V: negative voltage), and the source 504 is grounded. A tunnel phenomenon occurs near the drain 503,
The electrons are supplied to the floating gate 502 and the drain 503.
Since acceleration is caused by the electric field formed therebetween, electrons are extracted from the floating gate 502, and the threshold value of the memory cell decreases. Here, this lowering of the threshold value is defined as storing information “0”.

On the other hand, at the time of erasing, the drain 503 is opened, a positive erasing voltage is applied to the control gate 501, and the VBB is applied to the source 504 and the semiconductor substrate 506.
When a (negative voltage) is applied, an electric field is formed between the source 504 and the floating gate 502, whereby a tunnel phenomenon occurs and the floating gate 502
Electron injection occurs, and the threshold value of the memory cell rises. Here, this rise in the threshold is defined as storage of information “1”.

Thereafter, a write / erase operation is performed according to a procedure as shown in FIG. The procedure for writing is shown in the flowchart of FIG. First, an address is set to the first address. A positive voltage of 6.3 V is applied to the bit line BL, and a program voltage (negative voltage) generated by the write control circuit 303 is applied to the word line for a certain time. When writing is performed in this manner, the threshold voltage Vth decreases (step 401).

Thereafter, a verify operation for checking whether the threshold voltage is a predetermined value is performed by a verify circuit 305.
(Step 402). If the result of the verification is a fail (step 403), the verify operation is interrupted, the address is returned to the start address, and writing is performed again. Then, verify (Step 4
02), the result of verification is the final address (step 40)
Steps 401 to 404 are repeated until OK is obtained until 4).

Next, after all the memory cell areas are in a write state (write before erase), an erase BLOCK is set, and an erase control circuit 302 generates an erase voltage. In the cross-sectional view of the memory cell shown in FIG. 6, the erase voltage is applied to the source 504 and the semiconductor substrate 506 for a certain time, the word line WL is held at a certain positive voltage, and the bit line BL is held in an open state. Then, electrons are injected from the semiconductor substrate 506 into the floating gate 502. In this way, the data written in all the memory cells is collectively erased (in BLOCK units) (step 4).
05). Thereafter, a verify command is input (step 406). After the erasing operation is performed, the verification circuit 305 checks whether or not the threshold voltage of the memory cell is a predetermined value. If the result of the verification is a pass and the result does not reach the final BLOCK (step 40)
7) Repeat the verification. If the result of the verification is “fail”, the verification is interrupted. And
Batch erase is performed again (step 405). Such an operation is repeated until the last BLOCK. Next, arbitrary data is written in the manner described above (step 408).
411).

[0009] When the writing characteristics vary within the same page, the following problem occurs. In other words, even if the fast-writing cell is OK in the verification, the writing to both cells is repeated simultaneously until the other slow-writing cell is OK. Therefore, a phenomenon called overwriting occurs. The cell is in a normal erased state and corresponds to logic "1" data. Also, the memory cell is
A cell in a write state, corresponding to logic "0" data. VCC to control gate of memory cell
When a voltage is applied, the erased cell remains off and no current flows. Cells in a normal write state are:
The current is turned on and current flows. Even if 0 V is applied to the control gate of the cell in the written state, the cell is turned off. However, when an overwritten cell is present, a leak current is present on the same bit line, so that when reading another logic "1" data cell connected to the connected bit line BL1, the bit line BL Will drop and the data will be read erroneously as logical "0" data. Such a problem of overwriting has occurred in the conventional apparatus.

[0010]

In the above-mentioned conventional flash EEPROM, when information of a memory cell is rewritten, erasing is performed on all the memory cells at once.
When the capacity of the memory is increased, the time required for writing becomes longer, and there is a problem that the rewriting time becomes longer.
Therefore, in order to reduce the time required for writing during rewriting, the data to be written to the memory cell on the same word line is latched by a plurality of bytes in a latch circuit, and a writing function and a page programming function for writing these all at once are provided. However, as described above, in the flash EEPROM, since erasing is performed on all memory cells at once, writing must be performed on all memory cells including memory cells storing information that does not need to be rewritten. However, there is a problem that the rewriting time cannot be sufficiently reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a nonvolatile semiconductor memory device capable of greatly reducing the rewriting time.

[0012]

In a flash EEPROM according to the present invention, a large amount of write data can be written to a memory cell at a time by a latch circuit for page programming for each bit line. A source line of a memory cell on a word line selected by a signal can be connected to a source line switching circuit based on an address signal. By using the source line switching circuit, only the word lines necessary for rewriting can be selected and rewritten.

This flash EEPROM has a latch circuit for latching write information for page programming for each bit line, and a negative high voltage is supplied from a row decoder to a word line selected by an address signal. It is made to be done.

By doing so, a control circuit capable of erasing a minimum area necessary for rewriting is provided.

According to the present invention, in a nonvolatile semiconductor memory device capable of electrically writing and erasing, a word line of a memory cell in which information is to be rewritten by an address signal is selected, and a memory on the selected word line is selected. Since only the source lines connecting the cells are connected to the source line switching circuit based on the address signal, the page programming can be performed after erasing only the memory cells on the word lines to be rewritten.

Further, a word line of a memory cell in which information is to be rewritten is selected by an address signal, and a negative high voltage is supplied from the row decoder to the selected word line. After erasing only the memory cells on the line, page programming can be performed.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a circuit configuration of a memory array of a flash EEPROM and its peripheral portion according to Embodiment 1 of the present invention.
Reference numeral 3 denotes a power supply, which is a power supply voltage for decoder VBB, VPP, VC.
C is generated. 102 is an erase control circuit, 103 is a write control circuit, 104 is a sense amplifier, 105 is a verify circuit, 114 is an address control circuit, 106 is a row decoder, 107 is a column decoder, 108a, 108b, 1
08c is a latch circuit provided on each bit line BL1, BL2, BL3 and connected to the write control circuit 103, 109 is a source line switching circuit, 110a, 110
b is a source line connecting the sources of the memory cells in common for each memory cell array 112, 111a and 111b are controlled by the output of the row decoder 106, and
10a and 110b are selectively connected to the source line switching circuit 109.
Are connected to the source line selection transistor. here,
The entire device configuration other than that shown in FIG. 1 is basically the same as that of the conventional flash EEPROM shown in FIG.

The power supply voltages VPP (positive voltage) and VBB (negative voltage) for the decoder are supplied from VPP at the time of writing and erasing, VCC at the time of reading, and VPP at the time of writing and erasing verify. Further, the decoder power supply voltage VBB is output to the selected source line by selecting the address signal regardless of the erase control signal.

Next, the operation in the case where the rewriting of the memory cell for one word line in FIG. 1 is performed using the page programming function will be described. Rewriting of a memory cell includes a sequence for latching write information and its address, a sequence for writing "0" regardless of write information, a sequence for erasing, and a sequence for writing write information in order to prevent over-erasing. Divided into

First, a row decoder 1 is activated by an address signal.
06, the information for one word line is stored in the latch circuit 10
8 (108a, 108b, 108c) and latched.

The write data "0" is performed as follows. The word line WL1 is selected by the row decoder 106 according to the latched address signal, and the word line WL1 is selected.
Are supplied with VBB. Then, each latch circuit 108
a, 108b, and 108c are selected, and each of the latch circuits 108a, 108b, and 108c is selected.
c, regardless of the write information latched in the bit line BL.
1, a program voltage is applied to BL2 and BL3. The source line selection transistor 111 a is selected by the address signal through the row decoder 106, and the source line 110 a is grounded by the source line switching circuit 109. As a result, a current flows through all the memory cells for one word line, a tunnel phenomenon occurs, and the threshold voltage of the memory cells is lowered.

Erasure is performed as follows. First,
At the time of erasing, the erasing control signal is enabled, so that the row decoder 106 is in the open state regardless of the address signal, the column decoder 107 is in the open state regardless of the address signal, the positive voltage is applied to the control gate 501 of each memory cell, and the drain 503 is Be opened. The source line selection transistor 111a is selected by the address signal through the row decoder 106, and a high negative voltage is supplied from the source line switching circuit 109 to the source of the memory cell connected to the source line 110a. As a result, electrons are injected into the floating gate 502 of each memory cell corresponding to the word line WL1 due to the tunnel phenomenon, and the threshold value shifts to a higher side to perform erasure.

Writing is performed as follows. First, the row decoder 1 is operated by the latched address signal.
The word line WL1 is selected via 06, and VBB (negative voltage) is supplied. Then, each latch circuit 108a, 1
When the write pulse signal input to the latch circuits 08b and 108c is selected and the write information latched in the latch circuits 108a, 108b and 108c is "0", a program voltage is applied to the bit line BL to which the latch circuit is connected. You. The source line selection transistor 111 a is selected by the address signal through the row decoder 106, and the source line 110 a is grounded by the source line switching circuit 109. As a result, current flows only in the memory cells to be written out of the memory cells for one word line, and the threshold voltage of the memory cells is lowered by the tunnel phenomenon.

Next, the read operation of the memory cell will be described. The address signal is decoded by the column decoder 107 and the row decoder 106, and when selected, the bit line and the word line WL1 become "H". At the time of reading, the control signal is enabled and the latch circuit 108 (10
8a, 108b, and 108c), the bit line BL is selected. Also, the row decoder 10 is controlled by an address signal.
6, the source line selection transistor 111a is selected, and the source line 110a is grounded by the source line switching circuit 109. Then, whether or not a current flows through the memory cell is detected by the sense amplifier 104, and read data “1” and “0” are obtained.

As described above, in the nonvolatile semiconductor memory device according to the first embodiment, the input data from the I / O line is fetched and latched, and the program voltage is applied to each bit line based on the write control signal. There are a plurality of latch circuits for supplying the selected word line because the row decoder selects the word line and connects the source line of the memory cell on the selected word line to the source line switching circuit. After erasing only the memory cells corresponding to, the write information can be collectively written to the memory cells on the selected word line based on the write information latched by the latch circuit. Information can be rewritten to the memory cells in word line units without erasing.

FIG. 2 shows the flash EEPROM of FIG.
It shows a flow of a rewrite sequence of the OM memory array. (Embodiment 2) FIG. 3 is a diagram showing a circuit configuration of a memory array of a flash EEPROM and its peripheral portion according to Embodiment 2 of the present invention.
08a, 108b, and 108c are latch circuits connected to the write control circuit 103 and provided on the bit lines BL1, BL2, and BL3, and 111a and 111b are row decoders 1.
06, the source lines 110a, 110
b is a source line selection transistor for selectively grounding.

The power supply voltages VPP (positive voltage) and VBB (negative voltage) for the decoder are supplied from VPP at the time of writing and erasing, VCC at the time of reading, and VPP at the time of writing and erasing verification. Further, the decoder power supply voltage VBB is output to the selected source line by selecting the address signal regardless of the erase control signal.

Next, the operation in the case where the rewriting of the memory cell for one word line in FIG. 3 is performed by using the page programming function will be described. Rewriting of a memory cell includes a sequence for latching write information and its address, a sequence for writing "0" regardless of write information, a sequence for erasing, and a sequence for writing write information in order to prevent over-erasing. Divided into

First, the row decoder 1 is activated by an address signal.
06, the information for one word line is stored in the latch circuit 10
8 (108a, 108b, 108c) and latched.

The write data "0" is performed as follows. The word line WL1 is selected by the row decoder 106 according to the latched address signal, and the word line WL1 is selected.
Is supplied with VPP. Then, each latch circuit 108
a, 108b, and 108c are selected, and each of the latch circuits 108a, 108b, and 108c is selected.
c, regardless of the write information latched in the bit line BL.
1, a program voltage is applied to BL2 and BL3. The source line 110a is grounded. As a result, a current flows through all the memory cells for one word line, hot electrons are generated, and the threshold voltage of the memory cells is increased.

Erasing is performed as follows. First,
At the time of erasing, the erase control signal is enabled, so that the row decoder 106 is in the open state regardless of the address signal, the column decoder 107 is in the open state regardless of the address signal, the positive voltage is applied to the control gate 501 of each memory cell, and the drain 503 is Be opened. Also, the source line 11
0a is grounded. As a result, electrons are injected into the floating gate 502 of each memory cell corresponding to the word line WL1 due to the tunnel phenomenon, the threshold value shifts to a lower one, and erasing is performed.

Writing is performed as follows. First, the row decoder 1 is operated by the latched address signal.
The word line WL1 is selected via 06, and VPP (positive voltage) is supplied. Then, each latch circuit 108a,
When a write pulse signal input to 108b, 108c is selected and the write information latched in the latch circuits 108a, 108b, 108c is "0", a program voltage is applied to the bit line BL to which the latch circuit is connected. You. The source line 110a is grounded. As a result, current flows only in the memory cells to be written out of the memory cells for one word line, hot electrons are generated, and the threshold voltage of the memory cells is increased.

Next, the read operation of the memory cell will be described. The address signal is decoded by the column decoder 107 and the row decoder 106, and when selected, the bit line and the word line WL1 become "H". At the time of reading, the control signal is enabled and the latch circuit 108 (10
8a, 108b, and 108c), the bit line BL is selected. Also, the row decoder 10 is controlled by an address signal.
6, the source line selection transistor 111a is selected, and the source line 110a is grounded. Then, whether or not a current flows through the memory cell is detected by the sense amplifier 104, and read data “1” and “0” are obtained.

As described above, in the nonvolatile semiconductor memory device according to the second embodiment, the input data from the I / O line is fetched and latched, and the program voltage is applied to each bit line based on the write control signal. There are multiple latch circuits to supply, a row decoder selects a word line,
Since it is configured to supply a positive high voltage to the selected word line, after erasing only the memory cells corresponding to the selected word line, based on the write information latched in the latch circuit, The write information can be written to the memory cells on the selected word line at a time, and the information can be rewritten to the memory cells in word line units without erasing all the memory cells.

It is needless to say that the circuit configuration other than the memory array and its peripheral parts shown in the above embodiment can be variously changed as required.

[0036]

As described above, according to the present invention,
A latch circuit for page programming is provided for each bit line, and a source line connecting a memory cell on a word line selected by an address signal can be connected to a source line switching circuit based on the address signal. Therefore, the page programming can be performed after selectively erasing the write information of the memory cell on the word line including the memory cell to be rewritten,
There is no need to write data in all memories, and the rewriting time can be greatly reduced.

The flash EEPROM according to the present invention
According to OM, a latch circuit for page programming is provided for each bit line, and a negative high voltage can be supplied from a column decoder to a word line selected by an address signal. Since the page programming can be performed after selectively erasing the write information of the memory cells on the word lines including the memory cells, there is no need to write to all memories, and the rewriting time can be greatly reduced. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 shows a flash EE according to a first embodiment of the present invention.
The figure which shows the circuit configuration of the memory array of PROM and its peripheral part

FIG. 2 is a flowchart of a rewrite sequence of a memory array in the flash EEPROM of FIG. 1;

FIG. 3 shows a flash EE according to a second embodiment of the present invention.
The figure which shows the circuit configuration of the memory array of PROM and its peripheral part

FIG. 4 is a diagram showing a circuit configuration of a conventional memory array of a flash EEPROM and its peripheral portion;

FIG. 5 is a flowchart of a memory array rewrite sequence in a conventional flash EEPROM.

FIG. 6 is a sectional view of a memory cell in the memory cell array of FIG. 4;

[Explanation of symbols]

 101 Control Circuit 102 Erase Control Circuit 103 Write Control Circuit 104 Sense Amplifier 105 Verify Circuit 106 Row Decoder 107 Column Decoder 108a, 108b, 108c Latch Circuit 109 Source Line Switching Circuit 110a, 110b Source Line 111a, 111b Source Line Selection Transistor

Claims (2)

[Claims] 1. A flash EEPROM which performs writing by page programming, comprising: a plurality of rows of memory cell arrays in which a plurality of electrically rewritable / erasable nonvolatile memory cells are arranged; and a row for selecting the memory cell arrays. A decoder, a column decoder, a plurality of source lines commonly connecting a source of each memory cell for each of the memory cell arrays, and whether the source line is grounded,
A source line switching circuit for selecting whether to apply a high voltage, a source line selection transistor controlled by an output of the row decoder and selectively connecting the source line to the source line switching circuit, and a memory cell bit. A plurality of latch circuits provided for each line, for latching one write data, and supplying a program voltage to each bit line based on a write control signal; A nonvolatile semiconductor memory device, wherein a negative high voltage is applied to a source line of a memory cell from the source line switching circuit, and information of a memory cell on the same word line is erased. 2. A flash EEPROM which performs writing by page programming, comprising a plurality of rows of memory cell arrays in which a plurality of electrically rewritable / erasable nonvolatile memory cells are arranged, and a row for selecting the memory cell arrays. A decoder, a column decoder, a plurality of source lines for commonly connecting the sources of the memory cells for each of the memory cell arrays, and a source line selection transistor controlled by an output of the row decoder, for selectively grounding the source lines. And a plurality of latch circuits provided for each bit line of the memory cell, each latching one write data, and supplying a program voltage to each bit line based on a write control signal. A negative high voltage is applied from the write control circuit to the selected word line, A nonvolatile semiconductor memory device, wherein information of a memory cell on a selected word line is page-programmed based on latch data of the latch circuit.