JP2002132397A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] When the threshold voltage of a transistor in a circuit is reduced due to scaling rules due to the progress of miniaturization of semiconductor processing technology, the transistor is turned off even if the clock frequency or the power supply voltage is reduced. The current consumption due to the leak current has increased. SOLUTION: In a semiconductor integrated circuit device including a central processing unit and a plurality of peripheral function blocks, a first register group and a part including at least a register defined by a program model included in the central processing unit Of the peripheral function block is configured by a circuit having a first threshold voltage transistor, and the other circuits are configured by a circuit having a second threshold voltage transistor having a voltage lower than the first threshold voltage, The power supply system and the reset system of the voltage circuit are provided with a standby function that can be independently controlled for each of several partial circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device mounting an embedded microprocessor,
In particular, when the miniaturization of semiconductor integrated circuit processing technology advances and the power supply voltage and the threshold voltage of the transistor are reduced due to scaling, it is necessary to achieve both high-speed processing during normal operation and low leakage current during standby. It is about technology.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device on which a built-in microprocessor is mounted, a clock frequency control technique or the like has been used as a technique for reducing power consumption during standby or when a processing load is small. In clock frequency control technology, during normal operation with a high processing load, the CPU operates at the maximum operating frequency at which the central processing unit and peripheral function blocks can operate. Then
The frequency of the clock to the central processing unit and peripheral function blocks was reduced or stopped.

Recently, CMOS technology is often used in semiconductor integrated circuit devices, and power consumption can be reduced to almost zero by stopping a clock. These techniques are disclosed in JP-A-5-46273, JP-A-5-143753, and the like.

In recent years, by controlling a back gate bias voltage applied to a semiconductor substrate forming a transistor, the threshold voltage of the transistor is changed to be low during operation and high during standby, thereby achieving high-speed processing during operation and standby. Techniques for realizing low power consumption at the time have also been proposed. Regarding these techniques, see Japanese Patent Application Laid-Open
No. 108194, for example.

[0005]

However, in a semiconductor integrated circuit device having a processor with a standby function using a conventional clock frequency control technology, as described above, the semiconductor circuit processing technology has been miniaturized, In the generation of 0.15 μm or 0.13 μm or less, which is called deep submicron, the performance cannot be maintained unless the threshold voltage is lowered by power supply voltage scaling. Therefore, even if the clock is stopped, the transistor is turned off. The problem of consuming current due to leakage current is occurring.

A standby function based on back gate / bias voltage control has also begun to be used. However, in the future, with further miniaturization, and in the generation of 0.10 μm or less, when scaling to improve the operation speed of the circuit is performed, the The dependency of the threshold voltage on the gate bias voltage tends to decrease, and the threshold voltage cannot be changed sufficiently even by using the back gate bias voltage control technique. It is becoming difficult to reduce current consumption due to leakage current.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the power supply voltage and the threshold voltage of a transistor due to scaling down of the semiconductor integrated circuit processing technology. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a processor having a standby function that achieves both high-speed processing during normal operation and low leakage current during standby.

[0008]

According to the present invention, a semiconductor integrated circuit device is provided by taking the following means.
This is to solve the above problem.

[0009] Two types of transistors having different threshold voltages are considered for the transistors constituting the circuits of the respective sections. The first threshold voltage is set so that leakage current between the source and the drain when the transistor is off is negligible, and the second threshold voltage is set so as to achieve a target circuit speed. The voltage is set to a voltage at which a sufficiently high saturation current characteristic is obtained, that is, a value lower than the first threshold voltage.

In the central processing unit, a circuit including a register necessary for stopping and restarting a program, that is, a first register group including a register defined by a program model, and a circuit for stopping and restarting a program are not particularly required. This corresponds to a circuit constituting a second register group that is not included in the first register group. That is, for the circuit constituting the first register group, this is constituted by a transistor having a first threshold voltage, and for the circuit constituting the second register group, it is constituted by a transistor having a second threshold voltage. I do.

Further, a power supply system and a reset system are provided independently of each other in a circuit constituting the first register group and a circuit constituting the second register group. Each power supply system can be independently turned on and off, and each reset system has a standby function that can operate independently.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be generally described.

The semiconductor integrated circuit device of the first invention of the present application is
A circuit constituting a first register group including a register defined by a program model in the central processing unit is constituted by a transistor having a first threshold voltage, and a second register not included in the first register group A circuit forming a group includes transistors having a second threshold voltage lower than the first threshold voltage, and a first power supply system and a first reset system are provided for a circuit forming the first register group. And a second register group is provided with respect to a circuit constituting the second register group.
Power system and a second reset system, the first power system and the second power system can be turned on and off independently, and the first reset system and the second reset system Is provided with a stand-by function which enables the independent operation of.

The operation according to the first invention is as follows. The first threshold voltage is set so that the leakage current between the source and the drain when the transistor is off is negligible, and the second threshold voltage is high enough to realize a target circuit speed. It is set to a voltage at which a saturation current characteristic is obtained, that is, a value lower than the first threshold voltage. Thus, the transistor having the first threshold voltage can form a circuit having a low speed but a small leakage current at the time of stop, and the transistor having the second threshold voltage has a leakage current at the time of stop. Large but fast circuits can be constructed.

Among the registers included in the central processing unit, registers such as general-purpose registers, a stack pointer, a program counter, and a processor status register defined by a program model, and the internal state of the central processing unit are held. A transistor forming a register, such as a state machine resist, is configured by a transistor having a first threshold voltage, and other circuits are configured by a transistor having a second threshold voltage. A first power supply system and a first reset system are connected to the circuit to be configured, and a second power supply system and a second reset system are connected to other circuits.

At the time of starting the system, all the first and second power supply systems of the semiconductor integrated circuit device are turned on, and all of the first and second reset systems are reset. Operate the reset processing in the system.

When the processing load on the central processing unit is large and normal processing is required after the system is started, normal operation is performed with power supplied to both the first power supply system and the second power supply system. Let it do.

Next, when there is no processing load on the central processing unit and the processing waits, the power is supplied only to the first power supply system, and the second power supply system is turned off to be in a standby state. .

Since the first power supply system is connected only to a circuit composed of a transistor having a first threshold voltage, which has a small leakage current at the time of stop, the supply of the clock is stopped so that the leakage current can be reduced. Can be suppressed.

Next, when the processing load occurs again, the second
The power is again supplied to the power supply system, and the circuit whose power is cut off is reset by the reset signal in the second reset system, and the clock supply is started. Registers defined in the program model in the central processing unit, registers holding the operating state, and peripheral circuits required in the standby state are also energized in the standby state, and the state is saved. It is possible to continue execution from the state before the standby state. Also,
In the circuit including the transistor having the second threshold voltage, the power supply system and the reset system are separated from the circuit including the transistor having the first threshold voltage.
The operation starts from the initial state after the standby state is released.

As for the circuit constituted by the transistor having the second threshold voltage, it is possible to continue the operation from the initial state after releasing the standby state by allocating a circuit that gives priority to the operation speed rather than the state holding. . Regarding the part where the operation speed is important and the state holding is necessary, before the transition to the standby state, after the data is saved from the register in the circuit of the second threshold voltage to the register in the circuit of the first threshold voltage, Enter the standby state and restore after returning from the standby state.

As described above, it is possible to set the first threshold voltage to a value at which the leakage current at the time of standby can be tolerated, and reduce the second threshold voltage according to the miniaturization scaling of the semiconductor processing technology to realize high-speed operation. Thus, it is possible to achieve both high-speed processing during normal operation and low leakage current during standby.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
In the first aspect, the circuit configuring the plurality of peripheral function blocks includes a first peripheral function circuit unit including the first threshold voltage transistor and a transistor having the second threshold voltage. A second peripheral function circuit, further comprising a third power supply system and a third reset system, wherein the first peripheral function circuit unit is configured to include the first power supply system and the first reset circuit. System and the second
Is connected to the third power supply system and the third reset system so that the first power supply system, the second power supply system, and the third power supply system can be turned on and off independently. And a standby function that enables the first reset system, the second reset system, and the third reset system to operate independently.

The operation according to the second invention is as follows. For the peripheral function block, the first and second working memories such as a timer, an interrupt controller, and an SRAM which need to operate and save the state during standby are used.
And a second peripheral such as a serial interface, a DSP (Digital Signal Processor), and some remaining working memory which require high-speed operation during normal operation but can be stopped during standby. It is divided into a functional circuit part. The first peripheral function circuit section
, And the second peripheral function circuit section is configured by a transistor having a second threshold voltage. The first peripheral function circuit connects the first power supply system and the first reset system in the same manner as for the first register group defined in the above-described program model. The unit connects a separate third power supply system and a third reset system.

As described above, when the central processing unit has no processing load and waits for processing, the first power supply system continues to supply power, the second power supply system shuts off the power supply and enters standby mode. State. Then, the third power supply system shuts off the power supply or keeps the power supply as needed. Since power is supplied to the first power supply system, the first peripheral function circuit unit such as a timer and an interrupt controller connected to the first power supply system maintains its driving state even in the standby state. That is, it is possible to wait for an external interrupt signal for releasing the standby state. At this time, the circuit including the first register group driven by the first power supply system and the first peripheral function circuit unit are configured by transistors having a first threshold voltage set relatively high, Since the transistor having the first threshold voltage has a sufficiently small leakage current, the total leakage current value can be suppressed.

When the third power supply system is cut off in the standby state, the leak current in the second peripheral function circuit section can be cut off, and the current consumption can be reduced. Third
When the power supply system is restored, the second peripheral function circuit unit is initialized by the third reset system.

When the standby time is short or when the standby time is unknown and the operation of the peripheral function circuit section is required immediately after the return, the third power supply system can be kept connected.

As described above, it is possible to more effectively achieve both high-speed processing during normal operation and low leakage current during standby.

A semiconductor integrated circuit device according to a third aspect of the present invention comprises:
In the second invention, the third power supply system and the third power supply system are connected to each other.
Are a plurality of independent power supply systems and a reset system for each of the second peripheral function blocks.
Power supply system and the second power supply system, and the third power supply system can be independently turned on and off in an individual state for each of the second peripheral function blocks. A second reset system and a standby function enabling the second peripheral system to operate independently of the third reset system in an individual state for each of the second peripheral function blocks.

The operation of the third invention is as follows. Regarding the second peripheral function block, this requires a serial interface, DSP which requires high-speed operation during normal operation but can be stopped during standby.
(Digital Signal Processor), some of the remaining working memory. At the time of standby, there are a plurality of combinations as to which and which of the third power supply system are to be cut off together with the second power supply system. What combination of standby modes should be selected according to conditions, situations, and the like. For example, a mode in which the power supply system for the serial interface is cut off together with the second power supply system,
A mode in which the power supply system for P is cut off, a mode in which the power supply system for working memory is cut off together with the second DSP, and any one of the power supply systems in the second peripheral function circuit unit is cut off together with the second power supply system. And a mode in which three power supply systems of the second peripheral function circuit unit are cut off together with the second power supply system.

The current consumption can be adjusted in accordance with what combination of modes is selected, and the compatibility between high-speed processing during normal operation and low leakage current during standby is made even more effective. Can be.

(Specific Embodiment) Hereinafter, a specific embodiment of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is an example of a configuration diagram of a semiconductor integrated circuit device according to a first embodiment. 1
Reference numeral 01 denotes a semiconductor integrated circuit device, which is a framework generally called an LSI or a chip, and is composed of a plurality of silicon substrates integrated on one silicon substrate or mounted on one package. Reference numeral 102 denotes a central processing unit, which includes a control unit 103 and a data path unit 104. The control unit 103 includes a plurality of registers and combinational circuits.
1 is a stack pointer (SP), 112 is a program counter (PC), and 113 is a processor status register (PSR). These components 111 to 113
Is a register defined in the program model,
Data for determining the operation of the central processing unit 102 is held. Reference numeral 114 denotes a group of state machine registers that determine and hold the internal state of the control unit 103, 115 denotes a temporary data holding register group, and 116 denotes a combination circuit unit. State machine registers 114 are not visible to software running on central processing unit 102, but are used to determine the operation of central processing unit 102. The temporary data holding register group 115 is a register group for temporarily holding data when the control unit 103 performs a pipeline process or the like. 121 to 126 and 140 are peripheral function blocks connected to the central processing unit 102 via the on-chip bus 130. 121 is a timer, 122
Is an interrupt controller, 123 is a serial interface, 124 is a DSP (Digital Signal Processor), and 125 and 126 are on-chip SRAMs. Reference numeral 140 denotes an operation mode control unit which controls the clock system, the power system, and the reset system for each block in the semiconductor integrated circuit device 101 according to the control from the central processing unit 102 and the interrupt controller 122. Processing such as power on / off, clock supply / stop, and reset.

FIG. 2 is an example of a diagram showing a threshold voltage type, a power supply system, a reset system, and a clock system of circuits in the semiconductor integrated circuit device 101 shown in FIG. 1 according to the first embodiment. In FIG. 2, on-chip bus 130
Are omitted for clarity of the drawing.

The semiconductor integrated circuit device 101 is composed of transistors having two kinds of threshold voltages, a first threshold voltage and a second threshold voltage. The general-purpose register 110, the stack pointer 111, the program counter 112, the processor state register 113, and the state machine register group 114 are a first register group, and the temporary data holding register group 115 is a second register group. Also,
The timer 121, the interrupt controller 122, and the on-chip SRAM 125 are a first peripheral function circuit unit, and the serial interface 123, the DSP 124, and the on-chip SRAM 126 are a second peripheral function circuit unit.
The first register group, the first peripheral function circuit unit, and the operation mode control unit 140 are configured by transistors having a first threshold voltage. On the other hand, the second group of registers, the combinational circuit section 116, the data path section 104, and the second peripheral function circuit section are composed of transistors having a second threshold voltage. In FIG. 2, the hatched blocks are blocks including transistors having the first threshold voltage.

Here, the first threshold voltage and the second threshold voltage will be described. FIG. 4 is a diagram illustrating an example of the relationship between the threshold voltage of the transistor, the delay time, and the leak current. The horizontal axis indicates the threshold voltage of the transistor. The graph on the left side of the vertical axis and the black circle represent the leak current, which is a plot of the leak value per unit gate width when the transistor is off. The off-leak current varies logarithmically with a change in the threshold voltage. The graph on the right side of the vertical axis and the white circle represent the delay time, which is the delay time of a standard logic gate under a standard wiring load. As shown in FIG. 4, for example, when the threshold voltage is set as high as 0.5 V, the off-leakage current value becomes small as 0.01 nA / μm, but the delay value is large as 90 ps, that is, the circuit operation is slow. become. On the other hand, if the threshold voltage is set as low as 0.2 V, the delay value becomes 6
Although it is as small as 0 ps, that is, the circuit operation speeds up, the off-leak current value is as large as 10 nA / μm. Here, for example, the first threshold voltage is set as high as 0.5 V, and the second threshold voltage is set as 0.2 V, which is lower than the first threshold voltage. Note that the threshold voltage of a transistor is determined by a profile in a semiconductor manufacturing process.

Further, in FIG. 2, 201 is a first power system, 202 is a second power system, 203 is a third power system, 211 is a first reset system, 212 is a second reset system, 213 Is a third reset system. First
The power supply system 201 and the first reset system 211 of
A general-purpose register 110 comprising a transistor having the first threshold voltage, a stack pointer 111,
Program counter 112, processor status register 113, state machine register group 114, timer 121, interrupt controller 122, and on-chip SR
It is connected to AM125. The second power supply system 202 and the second reset system 212 include a data path unit 104 included in the central processing unit 102 in the circuit including the transistor having the second threshold voltage, and a temporary data holding unit. Register group 115 and combination circuit section 116
It is connected to the. The third power supply system 203 and the third reset system 213 are connected to a serial interface 123, a DSP 124, and an on-chip SRAM 126, which are peripheral function blocks composed of the transistor circuit of the second threshold voltage.

Here, the clock system to each component block is omitted, but the clock system is individually connected to each of the first power system 201, the second power system 202, and the third power system 203. I have. The power supply system, the reset system, and the clock system are controlled by the operation mode control unit 140 based on signals from the central processing unit 102 and the interrupt controller 122 to turn on / off the power and supply / stop the clock. And processing such as execution of reset. Further, the semiconductor integrated circuit device 10 is controlled so that power is always supplied to the operation mode control unit 140.
1 is directly connected to the power input.

FIGS. 5A and 5B are diagrams showing an example of a state of power supply to each power supply system and a current consumption in each of the standby modes in the semiconductor integrated circuit device shown in FIGS. 1 and 2. FIG. During normal operation, power is supplied to the first power supply system 201, the second power supply system 202, and the third power supply system 203. In the standby 1 mode, power is supplied to the first power supply system 201 and the third power supply system 203, and the second power supply system 202 is cut off. Standby 2
In the mode, power is supplied to the first power supply system 201,
The second power supply system 202 and the third power supply system 203 are shut off.

The bar graph in FIG. 5A shows the current consumption in each mode. 400-500m during normal operation
A consumption current is consumed.

When all clocks are stopped as a prerequisite operation for shifting to the standby state, about 3/10 of about 1/10
It is about 5 mA. This is because even if the operation of all the circuits in the circuit is stopped, the circuit portion constituted by the transistor having the second threshold voltage, that is, the temporary data holding register group 11
5, in the combination circuit unit 116, the data path unit 104, the serial interface 123, the DSP 124, and the on-chip SRAM 126, even if the circuit is completely quiescent, a current consumption occurs due to a leak current of an off transistor.

Here, the operation mode control unit 140
By shutting off the second power supply system 202 or the third power supply system 203 and shifting to the standby 1 mode or the standby 2 mode, these leak currents are interrupted, and the current consumption in the standby state is reduced to 25 mA or almost 0 mA.
Can be reduced. For example, the second power supply system 2
In the standby 1 mode in which the second power supply system 202 is shut off, the current can be reduced to 25 mA. In the standby 2 mode in which the second power supply system 202 and the third power supply system 203 are shut off, the current can be reduced to 0 mA. Note that the leakage current of the transistor having the first threshold voltage is about 1/1000 as shown in FIG. 4 when compared with the transistor having the second threshold voltage, and is almost 0 mA.
It is weak enough to be considered.

When the mode is shifted to the standby mode, the power supply is cut off, so that all the values held in the registers included therein are erased and the circuit is in an undefined state. Therefore, at the time of return, the second power supply system 20
2 has been shut down, the registers in the circuit are initialized by the second reset system 212, and if the third power supply system 203 has been shut down, the circuit is initialized by the third reset system 213. Initialize the register inside. As for the central processing unit 102, a general-purpose register 110 storing information necessary for continuing the processing, a stack
The values of the pointer 111, the program counter 112, the processor status register 113, and the state machine register group 114 are held in a conductive state by the first power supply system 201, and are set to NO before the transition to the standby mode.
By executing the P (no operation) instruction and flushing all the data being pipelined, the second reset system 212 enables the continuous execution by initialization. Regarding the third power supply system 203 connected to the peripheral function block, if it is necessary to save the state before the transition to the standby mode, the on-chip SRAM 12
5. The value of the register necessary for 5 is saved, and the data is restored after returning from standby. Since the data is transferred within the semiconductor integrated circuit device 101, it is possible to perform high-speed save / restore processing.

As an example, a flow when it is determined that there is no processing in the central processing unit 102 for 5 seconds will be described. First, the timer 121 is set to cause an interrupt to the interrupt controller 122 after 5 seconds. After executing several NOP instructions, the operation mode control unit 140 is instructed to shift to the standby 2 mode. Then, the operation mode control unit 14
0, the second power supply system 202 and the third power supply system 2
03 is shut off. Five seconds later, an interrupt request is generated from the timer 121, a return signal is output from the interrupt controller 122 to the operation mode control unit 140, and according to the return signal, the operation mode control unit 140
02 and the third power supply system 203, and immediately thereafter,
Second reset system 212 and third reset system 2
13, the corresponding block is initialized. Thereafter, the processing from the state before the transition to the standby mode is continued.

The standby 1 mode is used when the standby time is short or when the standby time is unknown and the operation of the peripheral function block is required immediately after the return.

As described above, according to the first embodiment,
Registers that need to hold the internal state and registers defined by the program model in the central processing unit,
Peripheral function blocks that need to operate and save the state even during the standby state are constituted by a high threshold voltage first threshold voltage transistor circuit, and a portion requiring speed is a low threshold voltage second threshold voltage transistor circuit. In addition, the power supply system and the reset system connected thereto are made independent and individually controlled, and the clock stop, the power supply cutoff / conduction (input), and the partial reset are performed according to the processing request to the central processing unit. By doing so, the semiconductor integrated circuit processing technology has been miniaturized, and even when the power supply voltage and the threshold voltage of the transistor have been lowered due to scaling, both high-speed processing during normal operation and low leakage current during standby are compatible. A processor with a standby function can be provided.

In the first embodiment, for simplicity of description, only the standby mode is mainly described in the standby mode. However, the clock is partially changed according to the processing load conventionally used. Needless to say, it is possible to stop at the same time or to use it together with the method of controlling the frequency.

Although the microprocessor is described as an example of the central processing unit, it is needless to say that the DSP can be easily applied as a central processing unit.

(Embodiment 2) FIG. 1 is an example of a configuration diagram of a semiconductor integrated circuit device according to Embodiment 2 of the present invention. The description is omitted because it is the same as that described in the first embodiment.

FIG. 3 is an example of a diagram showing a threshold voltage type, a power supply system, a reset system, and a clock system of the circuits in the semiconductor integrated circuit device 101 shown in FIG. 1 according to the first embodiment. In FIG. 3, on-chip bus 130
Are omitted for clarity of the drawing.

The semiconductor integrated circuit device 101 is composed of transistors having two kinds of threshold voltages, a first threshold voltage and a second threshold voltage. The general-purpose register 110, the stack pointer 111, the program counter 112, the processor state register 113, and the state machine register group 114 are a first register group, and the temporary data holding register group 115 is a second register group. Also,
The timer 121, the interrupt controller 122, and the on-chip SRAM 125 are a first peripheral function circuit unit, and the serial interface 123, the DSP 124, and the on-chip SRAM 126 are a second peripheral function circuit unit.
The first register group, the first peripheral function circuit unit, and the operation mode control unit 140 are configured by transistors having a first threshold voltage. On the other hand, the second group of registers, the combinational circuit section 116, the data path section 104, and the second peripheral function circuit section are composed of transistors having a second threshold voltage. The hatched blocks in FIG. 3 are blocks including transistors having the first threshold voltage.

FIG. 4 is a diagram showing an example of the relationship between the threshold voltage of the transistor, the delay time, and the leak current. This figure is the same as that used in the first embodiment, and a detailed description is omitted.

In FIG. 3, reference numeral 201 denotes a first power supply system;
202 is a second power supply system, 301 is a third power supply system for the serial interface 123, and 302 is the DSP 12
4 is a third power supply system, 303 is an on-chip SRAM 1
26, a third reset system for the serial interface 123, and a DSP 211 for the serial interface 123.
Reference numeral 312 denotes a second reset system for the serial interface 123, reference numeral 311 denotes a third reset system for the DSP 124, and reference numeral 313 denotes a third reset system for the on-chip SRAM 126. First power supply system 201 and first reset system 211
Is a general-purpose register 110 comprising a transistor having the first threshold voltage, and a stack pointer 11
1, a program counter 112, a processor status register 113, a state machine register group 114, a timer 121, an interrupt controller 122, and an on-chip SRAM 125. Second power supply system 20
The second and second reset systems 212 are provided in the data path unit 10 included in the central processing unit 102 in the circuit constituted by the transistors having the second threshold voltage.
4. It is connected to the temporary data holding register group 115 and the combination circuit section 116. Third power supply system 301 and third reset system 31 for serial interface
1 is connected to the serial interface 123 and DS
The third power supply system 302 and the third reset system 312 for P are connected to the DSP 124, and the on-chip SRAM
The third power supply system and the third reset system are connected to the on-chip SRAM 126.

Here, although the clock system to each component block is omitted, the first power system 201, the second power system 202, and the third power systems 301, 302, 3
03 are individually connected to a clock system. The power supply system, the reset system, and the clock system are controlled by the operation mode control unit 140 based on signals from the central processing unit 102 and the interrupt controller 122 to turn on / off the power and supply / stop the clock. And processing such as execution of reset. The operation mode control unit 140 is directly connected to a power input to the semiconductor integrated circuit device 101 so that power is always supplied to the operation mode control unit 140.

FIGS. 6A and 6B are diagrams showing an example of a power supply conduction state to each power supply system and a current consumption in each standby mode in the semiconductor integrated circuit device shown in FIGS. 1 and 3. FIG. During normal operation, a first power supply system 201, a second power supply system 202, a third power supply system 301 for a serial interface, and a third power supply system 302 for a DSP
In addition, power is supplied to the third power supply system 303 for the on-chip SRAM. In the standby 1 mode, the first power supply system 201 and the third power supply systems 301, 302, 3
03 is turned on, and the second power supply system 202 is cut off. In the standby 2 mode, the first power supply system 201
In addition, power is supplied to the third power supply systems 301 and 302, and the second power supply system 202 and the third power supply system 303 for the on-chip SRAM are cut off. In the standby 3 mode, power is supplied to the first power supply system 201 and the third power supply systems 301 and 303, and the second power supply system 20
2 and the third power supply system 302 for the DSP is shut off. In the standby 4 mode, power is supplied to the first power supply system 201, and the second power supply system 202 and the third power supply systems 301, 302, and 303 are cut off.

The bar graph in FIG. 6A shows the current consumption in each mode. 400-500m during normal operation
A consumption current is consumed. When all clocks are stopped as a prerequisite operation for shifting to the standby state, about 1
It is about 35/10 mA, which is about / 10. This is because even if the operation of all the circuits in the circuit is stopped, the circuit portion composed of the transistor having the second threshold voltage, that is, the temporary data holding register group 115, the combination circuit portion 116, the data path portion 10
4. This is because, in the serial interface 123, the DSP 124, and the on-chip SRAM 126, even when the circuit is completely quiescent, a current consumption occurs due to a leak current of an off transistor.

Here, the operation mode control unit 140
Second power supply system 202 or third power supply system 301, 3
02, 303, and transition to the standby 1 mode, standby 2 mode, standby 3 mode, or standby 4 mode to interrupt these leak currents, thereby reducing the current consumption in the standby state to 25 mA or 15 mA.
mA or almost 0 mA. For example, in the standby 1 mode in which the second power supply system 202 is cut off, the current can be reduced to 25 mA. In the standby 2 mode in which the second power supply system 202 and the third power supply system 303 for the on-chip SRAM are cut off. 15mA
And the second power supply system and D
Standby 3 for shutting off third power supply system 302 for SP
In the mode, it is possible to reduce to 15 mA.
Power supply system 202 and all third power supply systems 301,
In the standby 4 mode in which 302 and 303 are cut off, it is possible to reduce the current to almost 0 mA. Note that the leakage current of the transistor having the first threshold voltage is about 1/1000 as shown in FIG. 4 when compared with the transistor having the second threshold voltage, and is almost 0 mA.
This is a leak current that can be considered as.

When the mode shifts to the standby mode, the power supply is cut off, so that all the values held in the registers included therein are erased and the circuit is in an undefined state. Therefore, at the time of return, the second power supply system 20
2 has been shut down, the registers in the circuit are initialized by the second reset system 212, and if the third power supply system 301, 302 or 303 has been shut off, The reset system 311, 312 or 313 initializes the registers in the circuit. As for the central processing unit 102, the general-purpose register 110 storing information necessary for continuing the processing, the stack pointer 111, the program counter 112, the processor status register 113, and the state machine register group 114 are connected to the first power supply. The value is held in a conductive state by the system 201 and the NOP
(No operation) By executing the instruction and flushing all the data being pipelined, the second
The initialization by the reset system 212 enables continuous execution. Regarding the third power supply system 301, 302 or 303 connected to the peripheral function block, when it is necessary to save the state before the transition to the standby mode, the value of the register required in the on-chip SRAM 125 is saved, and Restore data after returning from. Since the data is transferred within the semiconductor integrated circuit device 101, it is possible to perform high-speed save / restore processing.

As an example, a flow when it is determined that there is no processing in the central processing unit 102 for 5 seconds will be described. First, the timer 121 is set to cause an interrupt to the interrupt controller 122 after 5 seconds, and after executing several NOP instructions, the operation mode control unit 140 is instructed to shift to the standby 4 mode. Then, the operation mode control unit 14
0 shuts off the second power supply system 202 and all the third power supply systems 301, 302, 303. Five seconds later, an interrupt request is generated from the timer 121, a return signal is output from the interrupt controller 122 to the operation mode control unit 140, and according to the return signal, the operation mode control unit 140
First, the second power supply system 202 and all the third power supply systems 301, 302, and 303 are turned on, and immediately thereafter, the second power supply system
The corresponding block is initialized by the reset system 212 and all the third reset systems 311, 312 and 313. Thereafter, the processing from the state before the transition to the standby mode is continued.

The respective modes of standby 1, standby 2 and standby 3 are properly used according to the conditions and conditions for peripheral function blocks in the standby operation. When the standby time is short or when the standby time is unknown and the operation of the peripheral function block is required immediately after the return, the standby 1 mode is used. Although the amount of current reduction is small, all peripheral function blocks can be used immediately after the return operation of the central processing unit 102. The standby 2 mode is used when it is difficult to save data and register setting values in the DSP 124 or when it is necessary to perform processing using the DSP 124 immediately after returning from the standby mode. In the standby 3 mode, work data and a program code to be executed at high speed are written on the on-chip SRAM 126, and are used when it is necessary to perform processing using the work data and the program code after returning from the standby mode. . As described above, by using the standby mode properly according to the condition and the situation, it is possible to realize a more effective standby in suppressing the current consumption.

As described above, according to the second embodiment, the registers defined by the program model in the central processing unit and the registers which need to hold the internal state, the operation and the state saving even during the standby state A peripheral function block that needs to be configured by a transistor circuit of a first threshold voltage having a high threshold voltage, and a portion requiring speed is configured by a transistor circuit of a second threshold voltage having a low threshold voltage,
The reset system and the power supply system connected to these are made independent, especially for each peripheral function block, and they are individually controlled. In response to a processing request to the central processing unit, the clock stop and power cutoff / Continuity (closing)
And by performing a partial reset, the miniaturization of semiconductor integrated circuit processing technology has progressed, and even when the power supply voltage and the threshold voltage of the transistor have been lowered due to scaling, high-speed processing during normal operation and low leakage during standby A processor with a standby function compatible with current can be provided.

In the second embodiment, for the sake of simplicity, only the standby mode is mainly described in the standby mode, but the clock is partially changed according to the processing load conventionally used. Needless to say, it is possible to stop at the same time or to use it together with the method of controlling the frequency.

Although the microprocessor has been described as an example of the central processing unit, it is needless to say that the DSP can be easily applied as a central processing unit.

[0064]

According to the present invention with respect to a semiconductor integrated circuit device, the operation speed of registers necessary for stopping and restarting a program and registers for determining state transitions and the like in registers in the central processing unit is inferior. Is constituted by a circuit with a transistor having a first threshold voltage at which a leakage current becomes negligible at the time of standby, and
And a second threshold voltage transistor circuit having a lower scaling voltage and a lower threshold voltage in accordance with the progress of miniaturization of semiconductor processing technology, and an independent power supply system and a reset system are connected to each partial circuit in accordance with the standby mode. By performing clock initialization, power supply, and initialization by resetting, it is possible to achieve both high-speed processing during normal operation and low leakage current during standby.

In particular, the peripheral function blocks, which need to operate and store the state in the standby mode, are constituted by transistors of the first threshold voltage, and the circuits in the peripheral function blocks which require high-speed operation. The part is constituted by a circuit constituted by a transistor having a second threshold voltage, and the peripheral function block constituted by a circuit constituted by a transistor having a first threshold voltage is constituted by a part constituted by a transistor having a first threshold voltage of the central processing unit. Standby mode which is connected to a common power supply system and reset system, keeps energizing even in standby mode, and requires an independent power supply system and reset system for the peripheral function circuit section composed of the second threshold voltage transistor. By controlling these according to the It is possible to have.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a configuration of a semiconductor integrated circuit device according to a first embodiment and a second embodiment of the present invention;

FIG. 2 is a block diagram showing an example of a threshold voltage type, a power supply system, and a reset system of a circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing an example of a threshold voltage type, a power supply system, and a reset system of a circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 4 is a characteristic diagram showing an example of a relationship between a threshold voltage of a transistor, a delay time, and a leak current in the first and second embodiments of the present invention.

FIG. 5 is a diagram showing an example of a power supply conduction state to each power supply system and a current consumption in each standby mode of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a diagram showing an example of a state of power supply to each power supply system and a current consumption in each standby mode of the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 101 semiconductor integrated circuit device 102 central processing unit 110 general-purpose register (first register group) 111 stack pointer (first register group) 112 program counter (first register group) 113 processor status register (first) Register group) 115 Temporary data holding register group (second register group) 121 Timer (first peripheral function circuit section) 122 Interrupt controller (first peripheral function circuit section) 123 Serial interface (second peripheral function) Circuit) 124 DSP (Digital Signal Processor)
(Second peripheral function circuit section) 125 On-chip SRAM (first peripheral function circuit section) 126 On-chip SRAM (second peripheral function circuit section) 201 First power supply system 202 Second power supply system 203 Third Power system 211 first reset system 212 second reset system 213 third reset system 301 power system for serial interface (third power system for each second peripheral function block) 302 power system for DSP Third power supply system for each second peripheral function block 303 Power supply system for on-chip SRAM (third power supply system for each second peripheral function block) 311 Reset system for serial interface (second system)
312 A reset system of the DSP (individual third reset system of each second peripheral function block) 313 A reset system of the on-chip SRAM (individual third reset system of each second peripheral function block) 3rd reset system)

Claims (3)

[Claims] 1. A circuit forming a first register group including a register defined by a program model in a central processing unit is configured by a transistor having a first threshold voltage, and is included in the first register group. A circuit forming a second register group is formed by a transistor having a second threshold voltage lower than the first threshold voltage, and a first power supply system and a second power supply system are connected to the circuit forming the first register group. 1 reset system, a second power supply system and a second reset system are provided for a circuit constituting the second register group, and the first power supply system and the second power supply system are connected to each other. A semiconductor integrated circuit device having a standby function that can be turned on and off independently and that the first reset system and the second reset system can operate independently. 2. A circuit configuring the plurality of peripheral function blocks includes a first peripheral function circuit unit including the transistor having the first threshold voltage, and a transistor having the second threshold voltage. A second peripheral function circuit, further comprising a third power supply system and a third reset system, wherein the first peripheral function circuit section includes the first power supply system and the first power supply system.
, The second peripheral function circuit section is connected to the third power supply system and the third reset system, and the first power supply system, the second power supply system, and the third A power supply system that can be turned on and off independently, and a standby function that enables the first reset system, the second reset system, and the third reset system to operate independently. The semiconductor integrated circuit device according to claim 1. 3. The third power supply system and the third reset system are a plurality of power supply systems and a reset system which are independent for each of the second peripheral function blocks, and wherein the first power supply system and the second A power supply system and the third power supply system can be independently turned on and off in an individual state for each of the second peripheral function blocks, and the first reset system and the second reset system are connected to each other. , And the third peripheral function block in an individual state.
3. The semiconductor integrated circuit device according to claim 2, further comprising a standby function enabling the reset system to operate independently.