JP2002124866A - Semiconductor integrated circuit - Google Patents

Abstract

[PROBLEMS] To reduce the area of a semiconductor integrated circuit for supplying power corresponding to a threshold voltage. SOLUTION: A power supply 5 corresponding to a threshold voltage is applied to a logic block 6 including a MOS transistor which inputs a logic signal 8a, 8b to a gate and a body independently of each other. By inputting a logic signal to the body and the gate, a single MOS transistor can realize a logic function normally composed of two MOS transistors, thereby reducing the area of the semiconductor integrated circuit. Further, stable characteristics and yield can be obtained by the second power supply line 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for use in portable equipment and the like, which is required to have low power consumption, small chip area, and low cost.

[0002]

2. Description of the Related Art In recent years, many portable devices powered by a battery have become widespread. However, in semiconductor integrated circuits used in these devices, further reduction in power consumption is strongly required in order to extend the driving time of the battery. Has been requested. In addition, the performance of semiconductor integrated circuits is required to be higher in order to improve the functions of portable devices year by year. At the same time, there is a demand from semiconductor integrated circuit manufacturers to reduce the chip area as much as possible in order to reduce the cost and increase the yield of the semiconductor integrated circuit.

A MOS transistor is an element composed of four terminals: a source, a drain, a gate, and a body. When a logic circuit is conventionally formed using a MOS transistor, the terminal used for transmitting a logic signal is a source. , Drain and gate. FIG. 22 shows the handling of the body of an n-channel MOS transistor in a conventional semiconductor integrated circuit. In FIG. 22A, the body is fixed at the ground potential. This is the most common body connection method in a CMOS logic circuit. In FIG. 22B, a bias voltage supplied from a bias generation circuit is applied to the body. This is used to change the threshold voltage by changing the bias voltage during operation and non-operation of the circuit, and to reduce off-leak current during non-operation. In FIG. 22C, the body is connected to the source. This is mainly used to fix the potential of the body in a MOS transistor formed on a thin silicon layer (SOI) on an insulating film. In FIG. 22D, the body and the gate are connected. This is DT-MOSFET (Dynamic Threshold MOSF
ET), which is characterized in that the leakage current is small when the MOS transistor is off, and the on-current is large when the MOS transistor is on. This structure is disclosed in
It is used in 814 public information. FIG. 22E shows FIG.
It has the same characteristics as (d), in which the gate and the body are connected via a MOS transistor so that the leakage current is small when off and the on-current is large when the MOS transistor is on. This structure is used in the public information of JP-A-08-265123.

Japanese Patent Application Laid-Open No. Hei 9 (1999) -90131 discloses a technique in which a signal is independently applied to each of a gate and a body to achieve a function of combining two switches with one MOS transistor.
JP-A-162408 and JP-A-10-335655. However, there is a problem that the yield is deteriorated due to a variation in threshold voltage for each manufacturing process, and a current (leakage current) flowing through a MOS transistor which is originally functionally off during operation increases, thereby increasing power consumption. There was a point.

[0005]

However, in the above-described conventional configuration, on / off of the current between the source and the drain is controlled substantially only by the gate terminal, and one MO is controlled.
S transistors could only perform the same function as a single switch.

In addition, there is a conventional technique in which a single MOS transistor performs a function of combining two switches by independently applying a signal to each of a gate terminal and a body terminal. There is a problem that power consumption increases.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems and aims at reducing the number of MOS transistors constituting a logic circuit and reducing the area of a semiconductor integrated circuit.
The purpose is to improve yield and reduce power consumption.

[0008]

A semiconductor integrated circuit according to a first aspect of the present invention supplies a first power supply line for supplying a first potential and a second potential higher than the first potential. Second
, A third power supply line for supplying a third potential, and p
Channel type MOS transistor and / or n-channel type MOS
A logic block including a transistor;
The circuit for converting the potential of the logic block into the second potential is included on the same chip as the logic block.

A logic block constituting this semiconductor integrated circuit inputs a low-level or high-level logic signal independently to the gate and body of a MOS transistor, and outputs a logic signal by a combination of input logic signals.
It is characterized by including at least one S transistor. By using the effect that the threshold voltage of the MOS transistor changes according to a signal applied to the body, a complicated logic operation can be performed by one MOS transistor. As a result, the operation conventionally configured using two or more MOS transistors can be performed by one MOS transistor.

Also, by mounting a circuit for converting a third potential supplied from the outside to a second potential on the same chip as the logic block, the threshold voltage of the MOS transistor varies from chip to chip due to manufacturing variations. At this time, by changing the value of the second potential for each chip, variation in delay time for each chip can be reduced, and the yield can be increased.

As described above, according to the first aspect of the present invention, the number of MOS transistors constituting a logic circuit can be reduced, the area of a semiconductor integrated circuit can be reduced, and variation in delay time between chips can be reduced. You can increase the yield by reducing it.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit including a circuit for detecting a threshold voltage of a MOS transistor in a chip. The value of the second potential is varied according to the detected threshold voltage value. As a result, even when the threshold voltage dynamically changes due to a chip temperature change, the change in delay time can be reduced, and the yield can be increased.

As described above, according to the second aspect of the present invention, the number of MOS transistors constituting a logic circuit can be reduced, the area of a semiconductor integrated circuit can be reduced, and the variation in delay time between chips can be reduced. You can increase the yield by reducing it.

According to a third aspect of the present invention, there is provided the semiconductor integrated circuit according to the first and second aspects of the present invention, wherein a threshold voltage of an n-channel type MOS transistor to which a logic signal is independently applied to a gate and a body is defined by: When a low-level signal is applied to the body, it is set to be larger than the logical amplitude, and when a high-level signal is applied to the body, it is set to be smaller than the logical amplitude.

Even when a high-level signal is applied to the gate, when a low-level signal is applied to the body, the threshold voltage is larger than the logic amplitude and is always larger than the gate-source voltage. Not flowing. When the high-level signal is applied to the body, the threshold voltage becomes smaller than the logical amplitude. Therefore, a current flows between the source and the drain only when the high-level signal is applied to the gate and the high-level signal is applied to the body.

As described above, normally two n-channel MOSs
The AND function constituted by connecting the transistors in series can be constituted by one n-channel MOS transistor, and the number of n-channel MOS transistors constituting the semiconductor integrated circuit can be reduced.

According to the third aspect of the present invention, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

A semiconductor integrated circuit according to a fourth aspect of the present invention is the semiconductor integrated circuit according to the first and second aspects of the present invention, wherein a threshold voltage (usually a negative voltage) of a p-channel MOS transistor to which a logic signal is independently applied to a gate and a body. Is set so that its absolute value is larger than the logic amplitude when a high-level signal is applied to the body, and is set smaller than the logic amplitude when a low-level signal is applied to the body. It is composed.

Even when a low-level signal is applied to the gate, when a high-level signal is applied to the body, the absolute value of the threshold voltage is larger than the logical amplitude and is always larger than the absolute value of the gate-source voltage. -No current flows between the drains. When the low-level signal is applied to the body, the absolute value of the threshold voltage becomes smaller than the logical amplitude. Therefore, the current flows between the source and the drain only when the low-level signal is applied to the gate and the low-level signal is applied to the body. Flows.

As described above, the AND function normally formed by connecting two p-channel MOS transistors in series can be formed by one p-channel MOS transistor, and the p-channel MOS transistor forming the semiconductor integrated circuit can be formed. The number of transistors can be reduced.

According to the fourth aspect of the present invention, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit according to the first and second aspects of the present invention, wherein a threshold voltage of an n-channel MOS transistor in which a logic signal is independently applied to a gate and a body is set to When a low-level signal is applied to the body, it is set to be smaller than the logical amplitude and set to be positive, and when a high-level signal is applied to the body, the threshold voltage is set to a negative value. .

Accordingly, when a high-level signal is applied to the body, a current flows even when a low-level signal is applied to the gate, and when a high-level signal is applied to the gate, the current is reduced to the signal level of the body. Regardless, current flows. Therefore, when a high-level signal is applied to the gate or a high-level signal is applied to the body, a current flows between the source and the drain. When both the gate and the body are at low level, no current flows between the source and the drain.

As described above, the OR function usually formed by connecting two n-channel MOS transistors in parallel can be constituted by one n-channel MOS transistor.
The number of n-channel MOS transistors included in a semiconductor integrated circuit can be reduced. Thus, according to the invention of claim 5, the number of MOS transistors constituting the logic circuit can be reduced, and the area of the semiconductor integrated circuit can be reduced.

According to a sixth aspect of the present invention, there is provided the semiconductor integrated circuit according to the first and second aspects of the present invention, wherein a threshold voltage of a p-channel MOS transistor to which a logic signal is independently applied to a gate and a body is set to be equal to the body voltage. When a high-level signal is applied to the body, its absolute value is set to be smaller than the logic amplitude and negative, and when a high-level signal is applied to the body, the threshold voltage is set to a positive value. It is composed.

Thus, when a low-level signal is applied to the body, a current flows even when a high-level signal is applied to the gate, and when a low-level signal is applied to the gate, the current changes to the signal level of the body. Regardless, current flows. Therefore, when a low-level signal is applied to the gate or a low-level signal is applied to the body, a current flows between the source and the drain.

As described above, two p-channel MOS transistors are usually used.
The OR function constituted by connecting the transistors in parallel can be constituted by one p-channel MOS transistor, and the number of p-channel MOS transistors constituting the semiconductor integrated circuit can be reduced.

Thus, according to the invention of claim 6, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

A semiconductor integrated circuit according to a seventh aspect of the present invention is an AND type nMOSFET, an OR type nMOSFET, an AND type pMOSFET, an OR type nMOSFET used in the third, fourth, fifth and sixth aspects of the present invention.
-Type pMOSFET and an n-channel MOSFET having a body not connected or connected to a first power supply line or connected to a source or connected to a second power supply line or connected to a gate, and having a positive threshold voltage and smaller than the logic amplitude And body not connected or first
Connected to the power supply line or connected to the source or connected to the second power supply line or connected to the gate terminal, and includes a p-channel MOSFET having a negative threshold voltage and an absolute value smaller than the logic amplitude. A more complicated logic can be configured by configuring a logic circuit by combining these.

According to the seventh aspect of the present invention, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

A semiconductor integrated circuit according to an eighth aspect of the present invention comprises the semiconductor integrated circuit according to the first to seventh aspects formed on a thin film silicon layer formed on an insulator.

This is called an SOI MOS transistor.
This makes it possible to prevent the latch-up from occurring even if a positive bias is applied to the body because the elements are completely insulated and separated from each other, and it is easy to change the potential of the body for each MOS transistor. There is an advantage that it can be integrated.

As described above, according to the eighth aspect of the present invention, the number of MOS transistors constituting the logic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and a higher level can be achieved without causing latch-up. There is an advantage that it can be integrated.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit, a first power supply line for supplying a first potential and a second power supply for supplying a second potential higher than the first potential are provided. A p-channel MOS transistor and / or an n-channel MOS transistor on a line and a thin film silicon layer formed on an insulator, wherein the first logic signal is a low level signal and the second logic signal is a high level An nMOS circuit block including at least one n-channel MOS transistor that inputs a logic signal independently to a gate and a body of a MOS transistor and outputs a logic signal by a combination of input logic signals. And a precharge circuit.

The precharge circuit has one end connected to the second power supply line and the other end connected to the output node. When the precharge signal is a signal for turning on a circuit, the potential of the output node is charged to a second potential.

The nMOS circuit block is an AND type nMOSFET, OR type
It is configured to include at least one or both of nMOSFETs. The nMOS circuit block has a function of blocking a current flow while the precharge circuit is on, and has one end connected to the output node and the other end connected to the first power supply line.

When the precharge signal is a signal for turning off the precharge circuit, the potential of the output node depends on whether or not there is a conduction path between the output node and the first power supply line in the nMOS circuit block. Is maintained at the potential of 2 /
A logic circuit can be formed by being reduced to the first potential.

By using this dynamic circuit method, there is an advantage that a DC current (leakage current) flowing from the second power supply line to the first power supply line when the precharge signal is on is suppressed. .

According to the ninth aspect of the present invention, the number of MOS transistors constituting the dynamic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be reduced. is there.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit, the precharge circuit according to the ninth aspect of the present invention is replaced by a p-channel MOS transistor (DT-M
OSFET).

The DT-MOSFET is a MOS whose body is connected to the source.
Compared to a transistor, the current (leakage current) flowing when the gate-source voltage is zero at the same threshold voltage is small, so that there is an advantage that the leakage current can be further reduced.

As described above, according to the tenth aspect of the present invention, the number of MOS transistors constituting the dynamic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be reduced. is there.

A semiconductor integrated circuit according to an eleventh aspect of the present invention includes a circuit for blocking current in the nMOS circuit block while the precharge circuit according to the ninth aspect is on, and the nMOS circuit block and the first power supply line. Prepare between. The current blocking circuit includes an n-channel MOS transistor having both a gate and a body connected to the precharge signal, a drain connected to the nMOS circuit block, and a source connected to a first power supply line. A semiconductor integrated circuit according to claim 9 or 10.

As described above, according to the eleventh aspect of the present invention, it is possible to configure a circuit that can easily block the current of the nMOS circuit block during the precharge period, and to reduce the circuit scale and the power consumption.

According to a twelfth aspect of the present invention, in the semiconductor integrated circuit, a first power supply line for supplying a first potential and a second power supply for supplying a second potential higher than the first potential are provided. A p-channel MOS transistor and / or an n-channel MOS transistor on a line and a thin film silicon layer formed on an insulator, wherein the first logic signal is a low level signal and the second logic signal is a high level A logic signal is input to a gate and a body of a MOS transistor independently of each other, and a logic block including at least one MOS transistor that outputs a logic signal according to a combination of input logic signals is ANDed. PMOSFET and AND nMO
It is configured to include a tri-state inverter circuit using SFETs.

The source of the AND type nMOSFET is connected to the first power supply line, the drain is connected to the output terminal, one of the gate and the body is connected to the input terminal, and the other is connected to the selection signal terminal.

The source of the AND type pMOSFET is connected to the second power supply line, the drain is connected to the output terminal, one of the gate and the body is connected to the input terminal, and the other is the inverted signal terminal of the selection signal. Thus, a tri-state inverter circuit is provided in which the output terminal is in a high impedance state when the selection signal is at a low level, and the output terminal is an inverted signal of the input signal when the selection signal is at a high level. Usually, a tri-state inverter circuit composed of four MOSFETs can be composed of two MOS transistors by using an AND pMOSFET and an AND nMOSFET.

As described above, according to the twelfth aspect, the number of MOS transistors constituting the tri-state inverter circuit can be reduced, and the area of the semiconductor integrated circuit can be reduced.

According to a thirteenth aspect of the present invention, there is provided a semiconductor integrated circuit including a flip-flop circuit using the tri-state inverter circuit according to the eleventh aspect.

By using a tri-state inverter circuit having a small number of MOS transistors, the number of MOS transistors can be smaller than that of a normal flip-flop circuit.

As described above, according to the thirteenth aspect, the number of MOS transistors constituting the flip-flop circuit can be reduced, and the area of the semiconductor integrated circuit can be reduced.

A semiconductor integrated circuit according to claim 14 of the present invention, wherein a first power supply line for supplying a first potential and a second power supply for supplying a second potential higher than the first potential are provided. A p-channel MOS transistor and / or an n-channel MOS transistor on a line and a thin film silicon layer formed on an insulator, wherein the first logic signal is a low level signal and the second logic signal is a high level A logic signal is input to a gate and a body of a MOS transistor independently of each other, and a logic block including at least one MOS transistor that outputs a logic signal according to a combination of input logic signals is ANDed. PMOSFET and AND nMOSFET
And a Muller C element comprising a latch circuit.

The source of the AND pMOSFET is connected to the second power supply line, the drain is connected to the output terminal, one of the gate and the body is connected to the first input terminal, and the other is connected to the second input terminal. I do.

The source of the AND type nMOSFET is connected to the first power supply line, the drain is connected to the output terminal, one of the gate and the body is connected to the first input terminal, and the other is connected to the second input terminal. I do. The latch circuit is connected to the output terminal.

The Muller C element is an important circuit used for asynchronous circuit design without using a clock signal.
When both the input terminal and the second input terminal are at the high level or the low level, the output terminals are at the low level,
Although it changes to a high level, when the signal level of the first input terminal is different from the signal level of the second input terminal, the output terminal retains the previous value.

Usually, Muller's C element composed of four MOSFETs and one latch circuit is an AND type pMOSFET, an AND type
By using the nMOSFET, it can be constituted by two MOS transistors and a latch circuit.

According to the fourteenth aspect of the present invention, the number of MOS transistors constituting the Muller C element can be reduced, and the area of the semiconductor integrated circuit can be reduced.

According to a fifteenth aspect of the present invention, in the semiconductor integrated circuit according to any one of the ninth to thirteenth aspects, a first power supply line for supplying a first potential and the first power supply line are provided. A second power supply line for supplying a second potential higher than the first potential, and a third power supply line for supplying a third potential, wherein the third potential corresponds to an in-chip threshold voltage. And a power supply circuit for converting the potential to the second potential.

As a result, the second potential is set according to the threshold voltage in the chip, so that it is possible to improve the delay characteristic variation due to manufacturing variations and the yield.

A semiconductor integrated circuit according to a sixteenth aspect of the present invention is the semiconductor integrated circuit according to the first to fifteenth aspects, wherein the logic amplitude is equal to or less than a junction potential of a diode between a drain and a body and between a source and a body. It is configured by setting.

Thus, there is an advantage that the pn junction leakage current between the body and the source and between the body and the drain is reduced even when the potential between the source and the body is biased to the magnitude of the logic amplitude.

As described above, according to the sixteenth aspect of the present invention, the number of MOS transistors constituting the logic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the pn
There is an advantage that the junction leak current can be reduced.

[0063]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 are drawings for explaining a first embodiment of the present invention. In the first embodiment, three power supply lines and a p-type MOS transistor and / or an n-type M
It is composed of a logic block composed of OS transistors and a variable power supply. In FIG. 1, 4 is a first power supply line, 5 is a second power supply line, 6 is a logic block, 25 is a variable power supply, and 7 is a MOS.
A transistor, 8a is a logic signal applied to the gate, 8b is a logic signal applied to the body, G is a gate terminal, and B is a body terminal. Logic signals 8a and 8b are independently applied to the gate terminal G and the body terminal B of the MOS transistor 7, respectively.

In the case of an AND type nMOSFET or an AND type pMOSFET, when the threshold voltage varies from chip to chip due to manufacturing variations, the characteristics are greatly changed. FIG. 2 illustrates this. In the ideal case of Fig. 2 (a), if the gate-source voltage is VGS, the drain-source voltage is Vdd, and the body-source voltage is VBS, the leakage current when VGS = Vdd, VBS = 0 is considered. Therefore, the threshold voltage Vth is set higher than the power supply voltage Vdd (this is referred to as a threshold margin). Further, the power supply voltage Vdd is set to be sufficiently higher than the threshold voltage Vtbias at the time of the body positive bias so that the current during operation becomes sufficiently large (hereinafter, Vdd-Vtbias is referred to as a drive voltage). In order to sufficiently increase the threshold margin and the drive voltage, it is important to develop a device in which the change in the threshold voltage at the time of bias is large.

Here, consider a case where the threshold voltage is higher than ideal due to manufacturing variations when the power supply voltage is fixed (FIG. 2B). At this time, the threshold margin increases, but the drive voltage decreases. As a result, the drive current is reduced, and the delay time is increased. Next, consider the case where the threshold voltage is lower than ideal due to manufacturing variations (FIG. 2 (c)). At this time, the drive voltage increases and the delay time decreases, but the threshold margin decreases, and the current (leakage current) flowing when VGS = Vdd and VBS = 0, which are originally off, increases. In the worst case, it may cause a malfunction.

In the embodiment of the present invention, the variation in the threshold voltage of the MOS transistor is dealt with by incorporating a power supply circuit for supplying a logic amplitude suitable for each chip to the logic block. When the threshold voltage in the chip becomes larger than the initially expected value, the logic amplitude is increased accordingly, and when the threshold voltage becomes smaller, the logic amplitude is set smaller. At the time of chip inspection, the threshold voltage of the MOSFET inside the chip is measured, and a circuit that sets the power supply voltage to give the appropriate logic amplitude for each chip using a method such as fuse trimming is incorporated into the chip, and the threshold margin and drive The voltage can be balanced.

FIG. 3 is a graph showing the relationship between the body-source voltage and the threshold voltage of an n-channel MOS transistor. As a voltage higher than the source is applied to the body, the threshold voltage decreases. By utilizing this characteristic, one MOS transistor can be designed by designing the device so that the threshold voltage changes with the logic amplitude between the low level and the high level of the logic signal applied to the body and the sign changes. Thus, usually two or more MOS transistors can perform necessary operations.

A logic signal is input to the gate and the body independently of each other, and a MOS transistor that outputs a logic signal according to a combination of the input logic signals is integrated, so that the number of MOS transistors constituting the logic circuit can be reduced. The area of the integrated circuit can be reduced, and the variation in delay time between chips can be reduced to increase the yield.

(Second Embodiment) FIG. 4 is a view for explaining a second embodiment of the present invention.

In the second embodiment, three power supply lines and a p-type MOS
The logic block includes transistors and / or n-type MOS transistors, a power supply circuit, and a threshold voltage detection circuit. 4, reference numeral 4 denotes a first power supply line, 5 denotes a second power supply line, 26 denotes a third power supply line, 6 denotes a logic block, and 7 denotes a MOS.
A transistor, 8a is a logic signal applied to the gate, 8b is a logic signal applied to the body, 27 is a power supply circuit, 28 is a threshold voltage detection circuit, G is a gate terminal, and B is a body terminal. MO
Logic signals 8a and 8b are independently applied to the gate terminal G and the body terminal B of the S transistor 7, respectively.

In the embodiment of the present invention, a power supply circuit for detecting a threshold voltage of a MOS transistor to be referred to for each chip and supplying a logic amplitude suitable for each chip to a logic block is incorporated. The embodiment of the present invention is characterized in that it can cope with a case where the threshold voltage changes due to the temperature as compared with the first embodiment.

As described above, according to the present embodiment, the number of MOS transistors constituting the logic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the variation in delay time between chips can be reduced. The yield can be increased.

(Third Embodiment) The third embodiment is similar to the first embodiment.
Alternatively, the present invention relates to a logic block of a semiconductor integrated circuit having a power supply line according to the second embodiment.

FIG. 5 is a drawing showing characteristics of an AND type nMOSFET used in the third embodiment of the present invention. Fig. 5 (a) is AND
1 shows a circuit configuration of a type nMOSFET. G is a gate terminal, D is a drain terminal, S is a source terminal, and B is a body terminal. VGS represents a gate-source voltage, VBS represents a body-source voltage, and Ids represents a current flowing from the drain D to the source S. The gate G and the body B have logic signals respectively.
8a and the logic signal 8b are added.

FIG. 5B shows the relationship between the threshold voltage of the AND type nMOSFET and the voltage between the body and the source. VTH represents the threshold voltage of the AND nMOSFET. As shown in FIG. 5B, the body B and the source
When the voltages applied to S are equal and the body-source voltage VBS is zero, the threshold voltage VTH is set to be larger than the logical amplitude. Then, the threshold voltage VTH is set to be smaller than the logic amplitude when the body-source voltage VBS changes to the magnitude of the logic amplitude. Such setting of the magnitude of the threshold voltage of the MOS transistor can be made by changing the concentration of the impurity implanted into the channel region.

FIG. 5C shows an AND type in which a low-level potential is applied to the source S and a high-level potential is applied to the drain D.
Indicates the operating characteristics of the nMOSFET. The top graph in FIG. 5C shows the transition of the logic signal 8a, and the second graph shows the logic signal 8b.
The third graph shows changes in the threshold voltage VTH and the gate-source voltage VGS, and the fourth graph shows the current Ids flowing from the drain D to the source S. The current Ids is when the gate-source voltage VGS is larger than the threshold voltage VTH (VGS> VTH)
Flows to An area (I) in the middle of FIG. 5C shows a case where the logic signals 8a and 8b are both at the low level. At this time, the threshold voltage
VTH is larger than the logic amplitude and the gate-source voltage VG
Since S is zero, no current Ids flows. In the area (II), the logic signal 8a changes from a low level to a high level. Along with this, VGS changes up to the magnitude of the logic amplitude. However, the current Ids does not flow because the threshold voltage VTH is larger than the logic amplitude. In the area (III), the logic signal 8b changes from a low level to a high level. As a result, the body-source voltage VBS changes to the magnitude of the logic amplitude, so the threshold voltage VBS
TH changes below the logic amplitude. At this time, since the gate-source voltage VGS becomes larger than the threshold voltage VTH, the current Ids
Flows. In the area (IV), the logic signal 8a changes from the high level to the low level again. At this time, VGS becomes zero and becomes smaller than the threshold voltage VTH, so that no current Ids flows. Thus, the current Ids flows only when the logic signal 8a is at the high level and the logic signal 8b is at the high level.

Such an operation is realized by connecting two nMOS transistors in series in the case of a normal method in which no logic signal is applied to the body. The present invention can be realized by one nMOS transistor by applying a logic signal not only to the gate but also to the body and setting the threshold voltage appropriately.

As described above, according to the present embodiment, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

(Fourth Embodiment) The fourth embodiment is a first embodiment.
Alternatively, the present invention relates to a logic block of a semiconductor integrated circuit having a power supply line according to the second embodiment.

FIG. 6 is a drawing showing the characteristics of the AND pMOSFET used in the fourth embodiment of the present invention. FIG. 6 (a) shows AND
1 shows the circuit configuration of a pMOSFET. G is a gate terminal, D is a drain terminal, S is a source terminal, and B is a body terminal. VGS represents a gate-source voltage, VBS represents a body-source voltage, and Ids represents a current flowing from the drain D to the source S. The logic signals 8a and 8b are applied to the gate G and the body B, respectively.

FIG. 6B shows the relationship between the threshold voltage of the AND pMOSFET and the body-source voltage VBS. VTH is AND type pMOSFE
Indicates the threshold voltage of T. In a p-channel MOS transistor, a high potential is normally applied to the source S, and a positive bias is applied when the potential of the body B becomes lower than the potential of the source S. Therefore, the negative value of the body-source voltage is shown in the graph. -VBS
Is shown. Further, in a normal enhancement-type p-channel MOS transistor, the threshold voltage is defined by a negative value, and therefore, a negative value of the threshold voltage -VTH is shown in the graph.

As shown in FIG. 6B, the body B and the source S
And the negative value of the body-source voltage
When VBS is zero, the negative value -VTH of the threshold voltage is set larger than the logic amplitude. Then, the negative value -VTH of the threshold voltage is set to be smaller than the logical amplitude when the negative value -VBS of the body-source voltage changes to the magnitude of the logical amplitude. Such setting of the magnitude of the threshold voltage of the MOS transistor can be made by changing the concentration of the impurity implanted into the channel region.

FIG. 6C shows an AND type in which a high-level potential is applied to the source S and a low-level potential is applied to the drain D.
Indicates the operating characteristics of the pMOSFET. The top graph in FIG. 6C shows the transition of the logic signal 8a, and the second graph shows the logic signal 8b.
The third graph shows the change in the negative value of the threshold voltage -VTH and the negative value of the gate-source voltage -VGS. The fourth graph shows the negative value of the current flowing from the drain D to the source S. -Ids
Represents The current -Ids is the negative value of the gate-source voltage -VGS
Is larger than the negative threshold voltage -VTH (-VGS> -VTH). The middle area (I) in FIG. 6C shows the logic signal 8a and the logic signal 8
b indicates a high level. At this time, since the negative value -VTH of the threshold voltage is larger than the logical amplitude and the negative value -VGS of the gate-source voltage is zero, no current -Ids flows. In the area (II), the logic signal 8a changes from a high level to a low level. Accordingly, -VGS changes to the magnitude of the logic amplitude. However, since the negative value -VTH of the threshold voltage is larger than the logic amplitude, the current -Ids does not flow. In the area (III), the logic signal 8b changes from the high level to the low level. Accordingly, the negative value -VBS of the body-source voltage changes up to the magnitude of the logic amplitude, and thus the negative value -VTH of the threshold voltage changes below the logic amplitude. At this time, the current -Ids flows because the negative value -VGS of the gate-source voltage is larger than the negative value -VTH of the threshold voltage. In the area (IV), the logic signal 8a changes from low level to high level again. Then -V
Since GS becomes zero and becomes smaller than the negative value -VTH of the threshold voltage, no current -Ids flows. Thus, the current -Ids flows only when the logic signal 8a is at the low level and the logic signal 8b is at the low level.

Such an operation is realized by connecting two pMOS transistors in series in the case of a normal method in which no logic signal is applied to the body. The present invention can be realized by one pMOS transistor by applying a logic signal not only to the gate but also to the body and setting the threshold voltage appropriately.

As described above, according to the present embodiment, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

(Fifth Embodiment) The fifth embodiment is similar to the first embodiment.
Alternatively, the present invention relates to a logic block of a semiconductor integrated circuit having a power supply line according to the second embodiment.

FIG. 7 is a drawing showing characteristics of the OR type nMOSFET used in the fifth embodiment of the present invention. Fig. 7 (a) shows the OR type
Indicates the circuit configuration of the nMOSFET. G is a gate terminal, D is a drain terminal, S is a source terminal, and B is a body terminal. Also,
VGS represents a gate-source voltage, VBS represents a body-source voltage, and Ids represents a current flowing from the drain D to the source S.
A logic signal 8 is applied to the gate G and the body B, respectively.
a, a logic signal 8b is added.

FIG. 7B shows the relationship between the threshold voltage of the OR type nMOSFET and the voltage between the body and the source. VTH represents a threshold voltage of the OR type nMOSFET. As shown in FIG. 7B, the body B and the source
When the voltages applied to S are equal and the body-source voltage VBS is zero, the threshold voltage VTH is positive and smaller than the logic amplitude. Then, the threshold voltage VTH is set to a negative value when the body-source voltage VBS changes to the magnitude of the logic amplitude. Such setting of the magnitude of the threshold voltage of the MOS transistor can be made by changing the concentration of the impurity implanted into the channel region.

FIG. 7C shows an OR type n when a low-level potential is applied to the source S and a high-level potential is applied to the drain D.
Indicates operating characteristics of MOSFET. The top graph in FIG. 7C shows the transition of the logic signal 8a, and the second graph shows the logic signal 8b.
, The third graph shows changes in the threshold voltage VTH and the gate-source voltage VGS, and the fourth graph shows the current Ids flowing from the drain D to the source S. The current Ids is when the gate-source voltage VGS is larger than the threshold voltage VTH (VGS> VTH)
Flows to An area (I) in the middle of FIG. 7C shows a case where the logic signals 8a and 8b are both at the low level. At this time the gate
Since the source-to-source voltage VGS is zero and smaller than the threshold voltage VTH, no current Ids flows. In the area (II), the logic signal 8a changes from a low level to a high level. With this, VGS
Changes to the magnitude of the logic amplitude and becomes larger than the threshold voltage VTH, so that the current Ids flows. Logic signal 8 in region (III)
b changes from a low level to a high level. Accordingly, the body-source voltage VBS changes to the magnitude of the logic amplitude, and thus the threshold voltage VTH changes to a negative value. At this time, a larger current Ids flows because the difference between the gate-source voltage VGS and the threshold voltage VTH increases. In the area (IV), the logic signal 8a changes from the high level to the low level again.
At this time, VGS becomes zero, but the current Ids flows because it is larger than the threshold voltage VTH. Thus, when the logic signal 8a is at the high level or the logic signal 8b is at the high level, the current Ids flows.

Such an operation is realized by connecting two nMOS transistors in parallel in the case of a normal method in which no logic signal is applied to the body. The present invention can be realized by one nMOS transistor by applying a logic signal not only to the gate but also to the body and setting the threshold voltage appropriately.

As described above, according to the present embodiment, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

(Sixth Embodiment) The sixth embodiment is a first embodiment.
Alternatively, the present invention relates to a logic block of a semiconductor integrated circuit having a power supply line according to the second embodiment.

FIG. 8 is a drawing showing the characteristics of the OR type pMOSFET used in the sixth embodiment of the present invention. Fig. 8 (a) shows the OR type
Indicates the circuit configuration of the pMOSFET. G is a gate terminal, D is a drain terminal, S is a source terminal, and B is a body terminal. Also,
VGS represents a gate-source voltage, VBS represents a body-source voltage, and Ids represents a current flowing from the drain D to the source S.
A logic signal 8 is applied to the gate G and the body B, respectively.
a, a logic signal 8b is added.

FIG. 8B shows the relationship between the threshold voltage of the OR pMOSFET and the body-source voltage VBS. VTH represents a threshold voltage of the OR type nMOSFET. In a p-channel MOS transistor, a high potential is normally applied to the source S, and the potential of the body B is
When the potential becomes lower than the potential, the positive bias is applied. Therefore, the negative value of the body-source voltage -VBS is shown in the graph. Further, in a normal enhancement-type p-channel MOS transistor, the threshold voltage is defined by a negative value, and therefore, a negative value of the threshold voltage -VTH is shown in the graph.

As shown in FIG. 8B, the body B and the source S
And the negative value of the body-source voltage
When VBS is zero, the negative value -VTH of the threshold voltage is positive and smaller than the logic amplitude. Then, the negative value -VTH of the threshold voltage is set to be a negative value when the negative value -VBS of the body-source voltage changes to the magnitude of the logic amplitude. Such setting of the magnitude of the threshold voltage of the MOS transistor can be made by changing the concentration of the impurity implanted into the channel region.

FIG. 8C shows an OR type p when a high-level potential is applied to the source S and a low-level potential is applied to the drain D.
Indicates operating characteristics of MOSFET. The top graph in FIG. 8C shows the transition of the logic signal 8a, and the second graph shows the logic signal 8b.
The third graph shows the change in the negative value of the threshold voltage -VTH and the negative value of the gate-source voltage -VGS. The fourth graph shows the negative value of the current flowing from the drain D to the source S. -Ids
Represents The current -Ids is the negative value of the gate-source voltage -VGS
Is larger than the negative threshold voltage -VTH (-VGS> -VTH). In FIG. 8C, the middle area (I) shows the logic signal 8a and the logic signal 8
b indicates a high level. At this time, the negative value -VGS of the gate-source voltage is zero, and the current -Ids does not flow because it is smaller than the negative value -VTH of the threshold voltage. In the area (II), the logic signal 8a changes from a high level to a low level. Accordingly, -VGS changes to the magnitude of the logic amplitude.
At this time, the current -Ids flows because the negative value -VGS of the gate-source voltage becomes larger than the negative value -VTH of the threshold voltage. In the area (III), the logic signal 8b changes from the high level to the low level. Accordingly, the negative value -VBS of the body-source voltage changes to a negative value. At this time, a larger current -Ids flows because the difference between the negative value -VGS of the gate-source voltage and the negative value -VTH of the threshold voltage increases. In the area (IV), the logic signal 8a changes from low level to high level again. At this time, -VGS becomes zero, but the negative threshold voltage -V
Current -Ids flows because it is larger than TH. Thus, when the logic signal 8a is at the low level or the logic signal 8b is at the low level, the current -Ids flows.

Such an operation is realized by connecting two pMOS transistors in parallel in the case of a normal method in which no logic signal is applied to the body. The present invention can be realized by one pMOS transistor by applying a logic signal not only to the gate but also to the body and setting the threshold voltage appropriately.

As described above, according to the present embodiment, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

(Seventh Embodiment) The seventh embodiment is a first embodiment.
Alternatively, the present invention relates to a logic block of a semiconductor integrated circuit having a power supply line according to the second embodiment.

FIG. 9 is a drawing showing a seventh embodiment of the present invention.

FIG. 9A shows one AND-type nMOSFET, three low-threshold-voltage single-input pMOSFETs, and a low-threshold-voltage single-input nMOSFET.
Is a two-input AND circuit configured using one. 4 in the figure
Is the first power supply line, 5 is the second power supply line, 6 is the logic block, MAN1 is an AND nMOSFET, MP1, MP2, and MP3 are single-input pMOSFETs, and MN1 is a single-input type. Indicates nMOSFET. Ain, Bin, NY, and Y in the figure represent logic signals. A normal CMOS circuit requires six MOSFETs, but by using an AND-type MOSFET, it can be configured with five MOSFETs.

FIG. 9B shows an AND nMOSFET and an OR nMOSFE.
T, two-input AND using one low-threshold voltage single-input nMOSFET and one low-threshold voltage single-input pMOSFET
Circuit. 4 is a first power line, 5 is a second power line, 6 is a logic block, MAN1 is an AND nMOSFET,
MOP1 is an OR-type pMOSFET, MP1 is a single-input pMOSFET, and MN1 is a single-input nMOSFET. In this case, the number of MOSFETs can be reduced to two-thirds compared to the conventional configuration.

The operation of the AND circuit having the configuration shown in FIG. 9A was verified by simulation. The characteristics of the MOSFET are as follows.

Power supply voltage: 0.5 V Gate length: 0.18 μm AND nMOSFET threshold voltage Zero bias: 0.56 V Threshold voltage at positive bias of 0.5 V: 0.46 V Single input pMOSFET threshold voltage: -0.3 V -Single-input nMOSFET threshold voltage: 0.3 V FIG. 10 shows a change in the logic signal NY when the logic signal Ain and the logic signal Bin change. At this time, the delay time from the rising transition of the logic signal Ain to the falling transition of the logic signal NY was 1.1 ns. In order to improve the circuit speed, it is necessary to design the device so that the threshold voltage of the AND type nMOSFET at the time of forward bias becomes smaller. This can be achieved by adjusting the concentration of impurity implantation into the body and channel regions so that the substrate bias effect coefficient γ becomes larger.

As described above, according to the present embodiment, the number of MOS transistors constituting a logic circuit can be reduced, and the area of a semiconductor integrated circuit can be reduced.

(Eighth Embodiment) FIG. 11 shows an eighth embodiment of the present invention.
It is a drawing explaining an embodiment. FIG. 11 (a) shows bulk M
FIG. 11B is a cross-sectional view of an OSFET, and FIG. 11B is a cross-sectional view of a MOS transistor (SOI MOSFET) formed in a thin silicon layer (SOI) on a buried oxide film as an insulator. In the figure, 9 is an element isolation layer made of an insulator, 10 is a gate region, 1
1 is a source region, 12 is a drain region, 13 is a body region, 14 is a channel region, 15 is a buried oxide film region,
Reference numeral 16 denotes a substrate area. SOI MOSFETs have the advantage of not latch-up because each element is completely insulated. Further, there is an advantage that it is easy to control the body for each MOSFET.

As described above, according to the present embodiment, the number of MOS transistors constituting the logic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and each MOS transistor does not cause latch-up. There is an advantage that the body can be controlled.

(Ninth Embodiment) Power is supplied from a first power supply line and a second power supply line, and a logic signal is input independently to a gate and a body of a MOS transistor formed by SOIMOS. At least one MOS transistor that outputs a logic signal according to a combination of signals
A precharge circuit and an nMO
The configuration includes at least one or more S circuit blocks.

FIGS. 12 and 13 are views for explaining a ninth embodiment of the present invention. FIG. 12 shows the configuration of the ninth embodiment of the present invention. In the figure, 4 is a first power supply line, 5 is a second power supply line, 6 is a logic block, 18 is an nMOS circuit block, 1
Reference numeral 9 denotes an output node, reference numeral 20 denotes an input logic signal, reference numeral 17 denotes a precharge circuit, and reference numeral 29 denotes a circuit for blocking the current of the nMOS circuit block. PR represents a precharge signal, DS represents a current blocking signal, and OUT represents a logic signal at the output node 19. FIG. 13 is a diagram for explaining the operation.

In the AND type nMOSFET and the AND type pMOSFET, when a high level signal is applied to only one of the body and the gate, a leak current flows because the difference between the threshold voltage and the gate-source voltage is small. There is a problem that it becomes easier. The configuration shown in FIG. 12 is generally called a dynamic circuit. However, when this configuration is used in the present invention, the leak current can be further reduced. While the precharge circuit turns on the precharge circuit by the precharge signal PR (hereinafter referred to as a precharge period), the input signals may be controlled to be all at a low level, but as shown in FIG. A current signal of the nMOS circuit block is blocked by the DS signal for blocking the current for a period, and the input logic signal 20 receives a normal predetermined signal. At this time, the output terminal OUT is charged to a high level. Precharge signal PR
Accordingly, the input logic signal 20 changes to a predetermined level during a signal in which the precharge circuit is turned off (hereinafter referred to as a discharge period). At this time, if there is a conductive path between the output terminal OUT and the first power supply line 4 through the nMOS circuit block, the charges accumulated in the output terminal 19 are discharged, and the output terminal 19 becomes low level. Output terminal 19
When there is no conductive path between the output terminal 19 and the first power supply line 4, the output terminal 19 remains at the high level. Thus, a logic circuit can be formed. Precharge circuit 1
7 is a circuit having a small leakage current, for example, a MOSF having a high threshold voltage.
By using ET or the like, the leakage current during the discharge period can be reduced. The discharge period needs to be set sufficiently shorter than the time during which the output terminal 19 falls below the logical threshold voltage due to the leakage current of the nMOS circuit block 18.

As described above, according to the present embodiment, the number of MOS transistors constituting the dynamic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be further reduced. .

(Tenth Embodiment) FIG. 14 is a drawing showing a tenth embodiment of the present invention. As the precharge circuit in the ninth embodiment, a p-type MOSFET having a gate and a body connected is used. In the figure, 4 is the first power supply line and 5 is the second power supply line.
Reference numeral 6 denotes a logic block, reference numeral 18 denotes an nMOS circuit block, reference numeral 19 denotes an output node, reference numeral 20 denotes an input logic signal, and reference numeral 21 denotes a p-type MOSFET connecting a gate and a body. Also PR
Represents a precharge signal, and OUT represents a logic signal of the output node 19.

The MOSFET connecting the gate and the body is a DT-MOS
It is called FET (Dynamic Threshold MOSFET). DT-MO
SFETs have the characteristic that the leakage current flowing when off is small and the current flowing when on is large. Therefore, by configuring the precharge circuit with the p-type MOSFET 21 having the gate and the body connected, it is possible to shorten the precharge period, increase the speed of the circuit, and reduce the leakage current during the discharge period.

As described above, according to the present embodiment, there are advantages that the number of MOS transistors constituting the dynamic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be reduced. .

(Eleventh Embodiment) FIG. 15 is a view for explaining an eleventh embodiment of the present invention. As a current blocking circuit of the nMOS circuit block in the ninth embodiment, an n-type MOSFET having a gate and a body connected is used. In the figure, 4 is a first power line, 5 is a second power line, 6 is a logic block,
18 is an nMOS circuit block, 19 is an output node, 20 is an input logic signal, 21 is a p-type MO having a gate and a body connected.
SFET 30 indicates an n-type MOSFET having a gate and a body connected. PR is a precharge signal, OUT is output node 1
9 represents a logic signal.

The current blocking circuit is constituted by an n-type MOSFET 30 having a gate and a body connected to a precharge signal, thereby shortening the discharge period and increasing the speed of the circuit, and reducing the leakage current during the precharge period. Can be performed.

As described above, according to the present embodiment, there are advantages that the number of MOS transistors constituting the dynamic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be reduced. .

(Twelfth Embodiment) FIGS. 16 and 17 are views for explaining a twelfth embodiment of the present invention. FIG.
(a) shows a schematic diagram of the tri-state inverter circuit. FIG. 16B shows a truth table of the tri-state inverter circuit. FIG. 16C shows a circuit configuration of a conventional tri-state inverter. In the figure, 4 is a first power supply line,
5 is a second power supply line, 6 is a logic block, MP1 and MP2 are single-input pMOSFETs, MN1 and MN2 are single-input nMOSFETs, IN is an input signal, OUT is an output signal, SEL is a selection signal, and / SEL is inverted. Is a selection signal. FIG. 17 shows a circuit configuration of the twelfth embodiment of the present invention.

The conventional tri-state inverter circuit has four
In this invention, an AND pMOSFET
And one AND-type nMOSFET
It can be composed of two MOSFETs.

As described above, according to the present embodiment, the number of MOS transistors constituting the tri-state inverter circuit can be reduced, and the area of the semiconductor integrated circuit can be reduced.

(Thirteenth Embodiment) FIG. 18 is a drawing showing a thirteenth embodiment of the present invention. FIG. 18 shows a configuration of a flip-flop circuit. In the figure, reference numeral 22 denotes a tristate inverter circuit according to the twelfth embodiment, and reference numeral 23 denotes an inverter circuit. By using the tri-state inverter circuit 22 shown in the twelfth embodiment of the present invention as a tri-state inverter circuit, the number of MOSFETs configured is reduced from 20 to 12 when the conventional tri-state inverter circuit is used. can do.

As described above, according to the present embodiment, the number of MOS transistors constituting the flip-flop circuit can be reduced, and the area of the semiconductor integrated circuit can be reduced.

(Fourteenth Embodiment) FIGS. 19 and 20 are views for explaining a fourteenth embodiment of the present invention. FIG.
(a) shows a truth table of Mueller's C element. Müller's C
The element is a basic element used in an asynchronous circuit that does not use a clock. FIG. 19 (b) shows a conventional Mueller C
1 shows a circuit configuration of an element. In the figure, 4 is a first power supply line, 5 is a second power supply line, 6 is a logic block, and MP1 to MP4 are single-input pM.
OSFETs, MN1 to MN4 are single-input nMOSFETs, A and B are input logic signals, and OUT is an output logic signal. FIG. 20 shows a circuit configuration of a Mueller C element according to a fourteenth embodiment of the present invention. In the figure, 4 is a first power supply line, 5 is a second power supply line, 6 is a logic block, MAP1 is an AND pMOSFET, and MAN1 is an AND MP1,
MP2 is a single-input pMOSFET, MN1 and MN2 are single-input nMOSFETs,
A and B are input logic signals, and OUT is an output logic signal.
Thus, in the conventional circuit configuration, eight MOSFETs are used, but in the present invention, six MOSFETs can be used.

As described above, according to the present embodiment, the number of MOS transistors constituting the Muller C element can be reduced, and the area of the semiconductor integrated circuit can be reduced.

(Fifteenth Embodiment) FIG. 21 is a view for explaining a fifteenth embodiment of the present invention. FIG. 21 shows the current-voltage characteristics of the pn junction diode, with the horizontal axis representing the voltage across the pn junction diode and the vertical axis representing the current flowing. In the case of an nMOSFET, the body is formed of p-type silicon, the source and drain are formed of n-type silicon, and a pn junction diode is formed between the body and the source and between the body and the drain. When the voltage passes a certain voltage, a current suddenly flows. The voltage at which this current begins to flow rapidly is called the junction potential. By setting the logic amplitude to be equal to or lower than this junction potential, when a high level is applied to the body of the AND nMOSFET and OR nMOSFET, and when the AND pMOSFET and OR
When a low level is applied to the body of the pMOSFET, the current flowing between the source and the body and between the drain and the body can be reduced, and there is an advantage that power consumption can be reduced.

As described above, according to the present embodiment, the number of MOS transistors constituting the logic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be further reduced. .

(Sixteenth Embodiment) The logic amplitude of at least the logic signal of the body of the logic signal applied to the gate and the body should be smaller than that of the pn between the drain and the body and between the source and the body.
It is set below the junction potential of the junction diode.

As a result, the malfunction of the logic block transmitting the logic signal is eliminated, and the effect of reducing the leak current of the logic circuit can be obtained.

[0130]

As described above, according to the first aspect, the number of MOS transistors constituting a logic circuit can be reduced, the area of a semiconductor integrated circuit can be reduced, and the delay time of each chip can be reduced. Can be reduced and the yield can be increased.

According to the second aspect of the present invention, the number of MOS transistors constituting a logic circuit can be reduced, the area of a semiconductor integrated circuit can be reduced, and higher integration without causing latch-up can be achieved. There is an advantage that you can.

Further, according to the third aspect, there are advantages that the number of MOS transistors constituting the logic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be reduced.

Further, according to the fourth invention, there are advantages that the number of MOS transistors constituting the dynamic circuit can be reduced, the area of the semiconductor integrated circuit can be reduced, and the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 shows an AND-type MOSFE according to the first embodiment of the present invention;
Diagram illustrating the effect of threshold voltage fluctuation on characteristics at T

FIG. 3 is a diagram showing a correlation between a threshold voltage of an nMOS transistor and a body-source voltage.

FIG. 4 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 5 shows an AND nMOSFET according to a third embodiment of the present invention;
(A) AND-type nMOSFET circuit diagram (b) Diagram showing AND-type nMOSFET threshold voltage and body-source voltage characteristics (c) AND-type nMOSFET with drain at high level and source at low level Diagram showing operating characteristics

FIG. 6 shows an AND pMOSFET according to a fourth embodiment of the present invention.
(A) AND-type pMOSFET circuit diagram (b) Diagram showing AND-type pMOSFET threshold voltage and body-source voltage characteristics (c) AND-type pMOSFET with drain at high level and source at low level Diagram showing operating characteristics

FIG. 7 shows an OR-type nMOSFET according to a fifth embodiment of the present invention.
(A) OR-type nMOSFET circuit diagram (b) Diagram showing OR-type nMOSFET threshold voltage and body-source voltage characteristics (c) OR-type nMOSFET when drain is at high level and source is at low level Diagram showing operating characteristics

FIG. 8 shows an OR-type pMOSFET according to a sixth embodiment of the present invention.
(A) OR-type pMOSFET circuit diagram (b) Diagram showing OR-type pMOSFET threshold voltage and body-source voltage characteristics (c) OR-type pMOSFET with drain at high level and source at low level Diagram showing operating characteristics

FIG. 9 is a circuit diagram of a two-input AND circuit according to a seventh embodiment of the present invention. (A) A two-input AND circuit using an AND-type nMOSFET. (B) A two-input AND circuit using an AND-type nMOSFET and an OR-type pMOSFET. Figure

FIG. 10 is a diagram showing a simulation waveform of a two-input AND circuit using an AND nMOSFET.

11A and 11B illustrate a difference between a bulk MOS transistor and an SOI MOS transistor. (A) Cross-sectional view of a bulk MOS transistor. (B) Cross-sectional view of an SOI MOS transistor.

FIG. 12 is a diagram of a dynamic circuit according to a ninth embodiment of the present invention.

FIG. 13 is a view for explaining the operation of FIG. 12;

FIG. 14 is a diagram of a dynamic circuit according to a tenth embodiment of the present invention.

FIG. 15 is a diagram of a current blocking circuit according to an eleventh embodiment of the present invention.

16A and 16B are diagrams for explaining a tri-state inverter circuit. FIG. 16A is a symbol diagram of the tri-state inverter circuit. FIG. 16B is a diagram showing a truth table of the tri-state inverter circuit. Diagram

FIG. 17 is a diagram of a tri-state inverter circuit according to a twelfth embodiment of the present invention.

FIG. 18 is a diagram illustrating a flip-flop circuit according to a thirteenth embodiment of the present invention;

FIG. 19 is a diagram of a Muller C element according to a conventional configuration. (A) A diagram showing a truth table of a Muller C element. (B) A circuit configuration diagram of a conventional Muller C element.

FIG. 20 is a diagram of a Muller C element according to a fourteenth embodiment of the present invention.

FIG. 21 is a diagram showing current-voltage characteristics of diode characteristics.

FIG. 22 is a diagram of a conventional body terminal handling method in an n-channel MOS transistor. (A) A configuration diagram in which the body is fixed to the ground potential. (B) A configuration diagram in which a potential is supplied to the body from a bias circuit. (D) Structural diagram connecting body and gate (e) Structural diagram connecting body to gate via MOS transistor

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N-channel type MOS transistor 2 Ground line 3 Bias generating circuit 4 First power supply line 5 Second power supply line 6 Logic block 7 MOS transistor 8 Logic signal 9 Element isolation layer 10 Gate region 11 Source region 12 Drain region 13 Body region Reference Signs List 14 channel region 15 buried oxide film region 16 substrate region 17 precharge circuit 18 nMOS circuit block 19 output node 20 input logic signal 21 precharge circuit constituted by DT-MOS 22 tristate inverter of eleventh embodiment of the present invention Circuit 23 Inverter circuit 25 Variable power supply 26 Third power supply line 27 Power supply circuit 28 Threshold voltage detection circuit 29 Circuit for blocking current flow 30 Current blocking circuit composed of DT-MOS G Gate terminal B Body terminal D Drain terminal S Source Terminal VGS Gate-source voltage VBS Body-source Inter-voltage VTH Threshold voltage Ids Current flowing between drain and source MP Single-input pMOSFET MN Single-input nMOSFET MAN AND-type nMOSFET MON OR-type nMOSFET MOP OR-type pMOSFET PR Precharge signal DS Current blocking signal Ain Input logic signal Bin input Logic signal of OUT output Logic signal of IN input SEL selection signal of tri-state inverter circuit / Inversion signal of selection signal of SEL tri-state inverter circuit Din D flip-flop data input signal CLK D flip-flop clock signal / CLK D flip-flop inverted clock signal QD flip-flop output signal

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (reference) H03K 19/00 F term (reference) 5F038 AZ10 BB08 BG06 BG09 BH18 BH19 CD02 CD04 CD09 CD15 DF01 DF08 DF14 DT12 EZ06 EZ10 EZ20 5F048 AA01 AB03 AC00 AC01 AC03 BA01 BA16 BB00 BB14 BE09 5J056 AA03 BB17 BB57 CC03 CC19 DD13 DD18 DD28 EE04 FF09 HH00 KK01 KK02

Claims (16)

[Claims] A first power supply line for supplying a first potential;
A second supplying a second potential higher than the first potential;
, A third power supply line for supplying a third potential, and a p-channel type MOS transistor and / or an n-channel type MOS transistor. And a power supply circuit for converting the third potential to the second potential. A MOS transistor is provided in the logic block. A semiconductor integrated circuit comprising at least one MOS transistor that inputs a logic signal to each of the gate and the body independently and outputs a logic signal according to a combination of the input logic signals. 2. A circuit for detecting a threshold voltage of a MOS transistor in a chip on the same chip as the logic block, wherein the value of the second potential is varied according to the detected value of the threshold voltage. The semiconductor integrated circuit according to claim 1, wherein: 3. A MOS transistor included in the logic block, wherein when the low-level signal is applied to the body, a threshold voltage is positive and a difference between the second potential and the first potential ( An n-channel MOS transistor (hereinafter referred to as an AND-type nMOSFE) having a threshold voltage that is positive when the high-level signal is applied to the body and becomes equal to or less than the logical amplitude when the high-level signal is applied to the body.
3. The semiconductor integrated circuit according to claim 1, further comprising: 4. A MOS transistor included in the logic block, wherein when the high-level signal is applied to the body, a threshold voltage is negative and an absolute value thereof is greater than or equal to the logic amplitude. A p-channel MOS transistor (hereinafter referred to as an AND-type pMOSFET) having a negative threshold voltage when the low-level signal is applied and an absolute value of which is equal to or less than the logical amplitude is included. Item 3. The semiconductor integrated circuit according to item 1 or 2. 5. The MOS transistor included in the logic block, wherein when the low-level signal is applied to the body, a threshold voltage is positive and equal to or less than the logic amplitude, and the high-level signal is applied to the body. 3. The semiconductor integrated circuit according to claim 1, further comprising an n-channel MOS transistor (hereinafter referred to as an OR-type nMOSFET) whose threshold voltage becomes negative when a signal is applied. 6. The MOS transistor included in the logic block, wherein, when the high-level signal is applied to the body, a threshold voltage is negative and an absolute value thereof is equal to or less than the logic amplitude. 3. The semiconductor integrated circuit according to claim 1, further comprising a p-channel MOS transistor (hereinafter referred to as an OR-type pMOSFET) whose threshold voltage becomes positive when the low-level signal is applied. 7. A MOS transistor included in the logic block, wherein a body is not connected, connected to a first power supply line, connected to a source, connected to a second power supply line, or connected to a gate, and the threshold voltage is positive. And an n-channel type smaller than the logic amplitude
One or more MOSFETs (hereinafter single-input nMOSFET) and / or body not connected or connected to the first power line or connected to the source or connected to the second power line or connected to the gate and the threshold voltage is One or more p-channel MOSFETs (hereinafter, single-input pMOSFETs) that are negative and whose absolute value is smaller than the logic amplitude and / or the AND-type nMOSFET and the AND-type pMOSFE
3. The semiconductor integrated circuit according to claim 1, wherein at least one of T, the OR-type nMOSFET, and the OR-type pMOSFET is included. 8. The semiconductor device according to claim 1, wherein the MOS transistor is formed on a thin silicon layer formed on an insulator.
8. The semiconductor integrated circuit according to any one of items 1 to 7. 9. A first power supply line for supplying a first potential,
A second supplying a second potential higher than the first potential;
Power line and the p-channel type MO on the thin silicon layer formed on the insulator.
A logic signal comprising an S transistor and / or an n-channel MOS transistor, wherein the first logic signal is a low level signal and the second logic signal is a high level signal;
An nMOS circuit block including at least one n-channel MOS transistor that inputs a logic signal independently to a gate and a body of a MOS transistor and outputs a logic signal according to a combination of input logic signals; a power supply terminal, an output terminal, and a signal A precharge circuit comprising at least one terminal, wherein the precharge circuit connects the power terminal to the second power line, connects the output terminal to an output node, A precharge signal is connected to the signal terminal, and when the precharge signal is a signal for turning on the precharge circuit, the potential of the output node is charged to the second potential; Has a function of blocking the flow of current while the switch is on, and has one end connected to the output node and the other The semiconductor integrated circuit which comprises a first at least one configuration consisting of nMOS circuit block connected to the power supply line. 10. The p-channel MOS transistor, wherein both a gate and a body are connected to the precharge signal, a source is connected to the second power supply line, and a drain is connected to the output terminal. 10. The semiconductor integrated circuit according to claim 9, comprising a transistor. 11. An n-channel MOS transistor having both a gate and a body connected to the precharge signal, a drain connected to the nMOS circuit block, and a source connected to a first power supply line, 11. The semiconductor integrated circuit according to claim 9, further comprising a function of blocking a current flow in the nMOS circuit block while the charge circuit is on. 12. A first power supply line for supplying a first potential, a second power supply line for supplying a second potential higher than the first potential, and a thin film formed on an insulator. P-channel type MO on silicon layer
A logic signal comprising an S transistor and / or an n-channel MOS transistor, wherein the first logic signal is a low level signal and the second logic signal is a high level signal;
Connect a source to the first power supply line in a logic block including at least one MOS transistor that inputs a logic signal independently to a gate and a body of a MOS transistor and outputs a logic signal according to a combination of input logic signals. The AND nMOSFET having a drain connected to an output terminal, one of a gate and a body connected to an input terminal, and the other connected to a selection signal terminal.
The AND having a source connected to the second power supply line, a drain connected to the output terminal, one of a gate and a body connected to the input terminal, and the other connected to an inverted signal terminal of the selection signal. A semiconductor integrated circuit including a tri-state inverter circuit including a p-type MOSFET. 13. A first power supply line for supplying a first potential, a second power supply line for supplying a second potential higher than the first potential, and a thin film formed on an insulator. P-channel type MO on silicon layer
A logic signal comprising an S transistor and / or an n-channel MOS transistor, wherein the first logic signal is a low level signal and the second logic signal is a high level signal;
The tri-state inverter circuit according to claim 11, wherein the logic block includes at least one MOS transistor that inputs a logic signal independently to a gate and a body of the MOS transistor and outputs a logic signal according to a combination of the input logic signals. A semiconductor integrated circuit comprising a flip-flop circuit including: 14. A first power supply line for supplying a first potential, a second power supply line for supplying a second potential higher than the first potential, and a thin film formed on an insulator. P-channel type MO on silicon layer
A logic signal comprising an S transistor and / or an n-channel MOS transistor, wherein the first logic signal is a low level signal and the second logic signal is a high level signal;
A logic signal is input independently to the gate and body of the MOS transistor, and a source is connected to the second power supply line in a logic block including at least one MOS transistor that outputs a logic signal according to a combination of input logic signals. The AND type p having a drain connected to an output terminal, one of a gate and a body connected to a first input terminal, and the other connected to a second input terminal.
A MOSFET and a source are connected to the first power supply line, a drain is connected to the output terminal, one of a gate and a body is connected to the first input terminal, and the other is connected to the second input terminal. A semiconductor integrated circuit, comprising: the above-mentioned AND-type nMOSFET and a Muller C element comprising a latch circuit connected to an output terminal. 15. A first power supply line for supplying a first potential, a second power supply line for supplying a second potential higher than the first potential, and a second power supply line for supplying a third potential. 3. A power supply circuit comprising three power supply lines, wherein the power supply circuit converts the third potential to the second potential.
14. The semiconductor integrated circuit according to any one of 1, 12, and 13. 16. The logic amplitude of at least the logic signal of the body of the logic signal applied to the gate and the body is set to be equal to or less than the junction potential of the pn junction diode between the drain and the body and between the source and the body. Claim 1
15. The semiconductor integrated circuit according to items 14 to 14.