JP2002118446A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a minimum power source voltage of a current switch type D-FF to 1 V or less without sacrificing a rapidity and to commonly use the power source voltage for a radio section and a base band section of a low voltage operation. SOLUTION: A semiconductor integrated circuit comprises various type elements formed on an SOI substrate to constitute a current switching type D-FF. The integrated circuit further comprises a MOS transistor M1 connected at its drain to a node M and at its source to a node E1, input at its gate with a signal D, and input at its body with a clock CK; a MOS transistor M2 connected at its drain to a node MN and at its source to a node E1, input at its gate with a complementary signal DN of the signal D, and input at its body with a clock CK; a resistance element R1 connected between a power source end VDD and the node M; a resistance element R2 connected between the end VDD and the node MN; and a constant-current source I1 connected between the node E1 and a ground terminal VSS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current switch type (CML) type semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit with a reduced power supply.

[0002]

2. Description of the Related Art In recent years, with the spread of portable information devices such as portable telephones, demands for semiconductor chips with low power consumption have been increasing. 2. Description of the Related Art A portable information device includes a wireless unit that handles analog signals for communication and a baseband unit that converts analog signals into digital signals and performs signal processing, and uses a plurality of semiconductor chips.

[0003] The baseband section is mainly composed of logic gates. The power consumption P _BB of the logic gate is P _BB = C · V _DD ² ·
It is represented by f. Here, C is the MO that constitutes the logic gate.
The sum of the parasitic capacitance, the intrinsic capacitance, and the wiring capacitance of the S transistor, V _DD is the power supply voltage, and f is the operating frequency. Assuming that the operating frequency f is constant, the capacity C
Or the power supply voltage V _DD may be reduced. In order to reduce C, it is effective to reduce the number of MOS transistors forming the logic gate or to reduce the gate width of the transistor. Further, since power consumption is proportional to the square of the power supply voltage V _DD , lowering the power supply voltage is more effective for reducing power consumption.

At present, a power supply voltage of a digital circuit such as a baseband section is around 3 V. From the above viewpoint, a circuit operating at a lower power supply voltage is desired, and a circuit operating at 1 V or less has been proposed. (See, for example,
-55652).

[0005] On the other hand, the radio section is mainly composed of an analog circuit which always flows a substantially constant current, and its power consumption P _RF is P P
_RF = I · V _DD Here, I is a current flowing in the circuit. In order to suppress power consumption, the current I may be reduced or the power supply voltage V _DD may be reduced.
The current value is determined not only by the operation speed of the circuit but also by noise characteristics and distortion characteristics, so that the current I cannot be reduced more than necessary. Therefore, it is necessary to lower the power supply voltage in order to reduce the power consumption of the radio unit.

At present, the power supply voltage of the radio section is about 3 V, which is almost the same as that of the baseband section. If the power supply voltages of the radio unit and the baseband unit are different, for example, a single power supply such as a battery requires a voltage conversion circuit, resulting in an increase in power consumption and an increase in cost due to conversion loss. Therefore, for an analog circuit for reducing power consumption and cost, a circuit operating at 1 V or less is desired similarly to a digital circuit.

FIG. 18 shows a conventional configuration of a basic circuit (D-type flip-flop, hereinafter referred to as D-FF) used to generate a stable frequency in the radio section. 1 is a master stage, 2 is a slave stage, 3 is a level shift stage, R
101 to R108 are resistors, and Q101 to Q118 are bipolar transistors. CK and CKN are complementary clock signals, D and DN are complementary input signals, and M and M
N is an output node of the master stage 1 (complementary output signal),
S and SN are output nodes of the slave stage 2 (complementary output signals), Y and YN are level-shifted complementary output signals, _VCC is a power supply voltage, and _VEE is a ground voltage.

The master stage 1 has a constant current circuit composed of Q113 and R105, the slave stage 2 has a constant current circuit composed of Q114 and R106, and the level shift stage 3 has Q117 and R10.
7, Q118 and R108, each having a constant voltage V _BB applied to the base of the bipolar transistor to flow a constant current I.

Next, the operation of this circuit will be described with reference to a timing chart. FIG. 19 shows operation waveforms of the clock CK, the input signal D, the node M, the node S, and the output Y. In the master stage 1, when the clock CK rises, the resistors R101 and R102 and the transistors Q101 and Q10
2 operates, and the transistors Q103,
The input signal D is taken in because the latch circuit consisting of Q104 becomes inactive. When the clock CK falls,
Since the differential circuit becomes inactive and the latch circuit operates,
The captured signal is latched.

Next, in the slave stage 2, when the clock CK falls, the resistors R103 and R104 and the transistor Q
Since the differential circuit including the transistors 105 and Q106 operates and the latch circuit including the transistors Q107 and Q108 does not operate, the output of the master stage 1 (logic of the node M) is captured. When the clock CK rises, the differential circuit becomes inactive and the latch circuit operates, so that the fetched signal is latched. In the level shift stage 3, an output signal Y in which the output of the slave stage 2 (logic of the node S) is lowered by the voltage between the base and the emitter of the bipolar transistor.
Get.

As described above, since the input signal is taken into the master stage 1 at the rising edge of the clock and sent to the slave stage 2 at the falling edge of the clock, the D-FF outputs the same logic as the input signal with one cycle delay. Note that the power supply voltage V _CC
Is 2.5 V, the ground voltage _VEE is 0 V, and the output amplitudes of the master stage 1 and the slave stage 2 are 0.4 V. As shown in FIG. .7V, the input signal D and the output M of the master stage are between 2.1V and 2.5V.

Next, consider the minimum power supply voltage for operating such a D-FF. The master stage 1 and the slave stage 2 have a cascade connection of three transistor stages and two resistor stages. In order for the transistor not to perform a saturation operation, the collector-emitter voltage needs to be at least about 0.5 V. The operating amplitude is at least 0.3 V considering the noise margin.
Therefore, the voltage across the load resistor is 0.3 V. _{Assuming that the} voltage between both ends of the resistance of the constant current source is 0.1 V, the minimum power supply voltage V _CCmin (V) is V _CCmin = 0.3 + 3 × 0.5 + 0.1 = 1.9.

[0013]

As described above, the conventional D-
In the FF, since the master stage and the slave stage have a cascade connection configuration of three bipolar transistors and two stages of resistors, the minimum power supply voltage is about 1.9 V.
Furthermore, considering a margin of about 10% due to the variation in voltage fluctuation, it has been difficult to reduce the power supply voltage to 2.1 V or less. As a result, there is a problem that it is difficult to share the power supply voltage with the baseband unit operating at 1 V or less. In addition, if the power supply voltages of the radio unit and the baseband unit are different, for example, in the case of a single power supply such as a battery, a voltage conversion circuit is required, which causes an increase in power consumption and an increase in cost due to conversion loss. there were.

The present invention has been made in consideration of the above circumstances, and has as its object to reduce the minimum power supply voltage without sacrificing high-speed operation, and to reduce the minimum power supply voltage (for example, 1 V or less). An object of the present invention is to provide a current switch type semiconductor integrated circuit typified by an operating D-FF.

[0015]

(Structure) The gist of the present invention is that a MOS transistor formed on an SOI (Silicon On Insulator) substrate or the like, a resistance element, and a constant current source constitute a flip-flop, and the MOS transistor By applying signals not only to the gate terminal but also to the body terminal,
An object is to enable operation at a low voltage (for example, 1 V or less) power supply voltage.

That is, in the present invention, the first signal is connected to the first node, the source is connected to the second node, the first signal is input to the gate, and the second signal is input to the body. A MOS transistor having a drain connected to the third node, a source connected to the second node, a third signal input to the gate, and a fourth signal input to the body; , A constant current source connected between the second node and a ground terminal.

Here, preferred embodiments of the present invention include the following. (1) The semiconductor layer on the insulating film is used as an element formation substrate, and each transistor is formed on this substrate. (2) The semiconductor layer on the insulating layer is made of single crystal silicon.

(3) The first signal and the third signal are complementary signals, and the second signal and the fourth signal are the same signal. (4) The second signal and the fourth signal are complementary signals, and the first signal and the third signal are the same signal. (5) The first signal and the third signal are complementary signals, and the second signal and the fourth signal are complementary signals.

(6) The first and third signals are input signals,
The second and fourth signals are clock signals. (7) A D-FF, T-FF, or multiplier is configured as a semiconductor integrated circuit.

Further, the present invention is a semiconductor integrated circuit using a semiconductor layer on an insulating film as an element formation substrate, wherein a drain is connected to a first node, a source is connected to a second node, and a gate is connected to a gate. The first signal is input and the second
, A drain is connected to a third node, a source is connected to the second node, and a gate is provided with a third signal which is a complementary signal of the first signal. A second MOS transistor for inputting the second signal to the body, a first resistive element connected between the first node and a power supply terminal,
A second resistance element connected between the second node and the power supply terminal, and a first constant current source connected between the second node and a ground terminal. Features.

Here, preferred embodiments of the present invention include the following. (1) The drain is connected to the first node and the source is
A third MOS transistor having a gate connected to the third node, a fourth signal which is a complementary signal of the second signal input to the body, and a drain connected to the third MOS transistor.
And a fourth MOS transistor having a source connected to the second node, a gate connected to the first node, and a fourth signal input to the body.

(2) the drain is connected to the fourth node,
A fifth MOS transistor having a gate connected to the first node, a source connected to the fifth node, a drain connected to the sixth node, a gate connected to the third node, and a source connected to the fifth node; MO connected to node 5
An S transistor; and a second constant current source connected between the fifth node and the ground terminal.

(3) The above configuration is used as a master circuit, and the same configuration as the master circuit is used, and the first signal is used instead of the first signal.
And a slave circuit for inputting an output signal appearing at the third node and inputting an output signal appearing at the third node instead of the third signal.

(Operation) According to the present invention, by forming a MOS transistor on an SOI substrate or the like, the body region of the transistor is separated for each transistor. By applying a signal to the body terminal together with the gate, the driving capability of the transistor can be independently controlled by the two signals. As a result, the number of cascade-connected elements constituting the flip-flop can be reduced, thereby enabling low-voltage operation.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 4 is a circuit configuration diagram illustrating a D-FF according to the embodiment.
This D-FF has a two-stage configuration of a master stage 1 and a slave stage 2.

In the master stage 1, R1 is a resistance element connected between the power supply terminal of the voltage V _DD and the node M (first node), and R2 is a resistance element connected between the power supply terminal of the voltage V _DD and the node MN (third node).
, A drain connected to the node M, an input signal D (first signal) input to the gate, and a source connected to the node E1 (second node).
, An nMOS transistor (first MOS transistor) to which a clock CK (second signal) is input to the body, a drain of M2 connected to the node MN, and a gate of a complementary signal DN (third signal) of the input signal D to the gate. Signal)
The source is connected to the node E1, and the clock CK is applied to the body.
Are input nMOS transistors (second MOS transistors).

Further, M3 is an nMOS transistor having a drain connected to the node M, a gate connected to the node MN, a source connected to the node E1, and a complementary clock CKN (fourth signal) of the clock CK input to the body. (Third MOS transistor) M4 has a drain connected to the node MN, a gate connected to the node M, a source connected to the node E1, and a body to which the clock CKN is input (a fourth MOS transistor). , I1 is a constant current source connected between the ground terminal of the node E1 and the voltage V _SS.

Further, in the slave stage 2, R3 is the voltage V
A resistance element connected between the power supply terminal of _DD and the node S;
4 is a resistance element connected between the power supply terminal of the voltage V _DD and the node SN, M5 is a drain connected to the node S, a gate connected to the node M, a source connected to the node E2, and a clock connected to the body. An nMOS transistor to which CKN is input, M6 is an nMOS transistor whose drain is connected to the node SN, whose gate is connected to the node MN, whose source is connected to the node E2, and whose body receives the clock CKN.

M7 has a drain connected to the node S, a gate connected to the node SN, a source connected to the node E2, and a clock CK input to the body.
The OS transistor M8 has a drain connected to the node SN, a gate connected to the node S, and a source connected to the node E.
2 connected to the clock CK and input to the body
The S transistor, I2, is a constant current source connected between the node E2 and the ground voltage V _SS .

Here, M1 to M8 have a body region of MOS.
It is formed using an SOI substrate or the like separated for each transistor.

FIG. 2 is a block diagram showing the D-FF. In this block diagram, D, CK, and S on only one side of the complementary signal are shown. Next, this DF
The circuit operation of F will be described with reference to a timing chart.

FIG. 3 shows operation waveforms of the clock CK, the input signal D, the node M, and the output signal of the node S. In the master stage 1, the clock CK is input to the bodies of the MOS transistors M1 and M2,
Since the clock CKN is input to the bodies of the MOS transistors M3 and M4, the driving capability of the MOS transistors M1 and M2 is
4 larger than that of 4. Conversely, when the clock CK is at the low level, the driving capabilities of the MOS transistors M1 and M2 are smaller than those of the MOS transistors M3 and M4.

Since a constant current always flows in the master stage 1 by the constant current source I1, when the clock CK rises, a differential circuit including the resistance elements R1 and R2 and the MOS transistors M1 and M2 operates, and the MOS transistors M3 and M2 operate.
4 is deactivated, and the input signal D is taken into the master stage 1. When the clock CK falls, the differential circuit becomes inactive, the latch circuit operates, and the fetched signal is latched.

Similarly, when the clock CK falls, the differential circuit including the resistance elements R3, R4 and the MOS transistors M5, M6 operates, and the MOS transistors M7, M8
, And the information of the node M is taken into the slave stage 2. When the clock CK rises, the differential circuit becomes inactive, the latch circuit operates, and the fetched signal is latched. Thus, the same operation as that of the conventional circuit can be performed.

Assuming that the power supply voltage V _DD is 0.8 V, the ground voltage V _SS is 0 V, and the output amplitudes of the master stage 1 and the slave stage 2 are 0.4 V, as shown in FIG.
K, input signal D, output M of master stage 1, slave stage 2
Are in the range of 0.4V to 0.8V. Therefore, when the output of this D-FF is input to the input D of another D-FF or the clock CK, it is not necessary to perform level conversion using a level shift circuit. Low power consumption can be achieved.

Next, specific examples of the resistance elements R1 to R4 are shown in FIG.
Shown in FIG. 4A shows an example in which a diffusion layer resistance R or a polysilicon resistance R is used as a resistance element. The diffusion layer resistance formed on the SOI substrate has a smaller parasitic capacitance with respect to the substrate than the diffusion layer resistance formed on the bulk substrate, so that high-speed operation is hardly hindered. FIG. 4 (b) shows n as a resistance element.
This is an example using a MOS transistor M9. A voltage V _GN is applied to the gate, and a desired resistance value can be obtained by appropriately selecting the voltage, the gate length, and the gate width. Further, the MOS transistor M
9 may be kept on, the body may be connected to the gate or the source, or an appropriate voltage may be applied to the body to obtain a desired resistance characteristic. In this case, M
The OS transistor M9 is desirably formed on an SOI substrate.

FIG. 4C shows an example in which a pMOS transistor M10 is used as a resistance element. Voltage V at the gate
_GP is added, and a desired resistance value can be obtained by appropriately selecting the voltage, the gate length, and the gate width. Further, the gate may be connected to the drain to keep the MOS transistor M10 on at all times, or the body may be connected to the gate or the source, or an appropriate voltage may be applied to the body to obtain a desired resistance characteristic. good. In this case, it is desirable that the MOS transistor M10 be formed on an SOI substrate.

Next, a specific example of the constant current sources I1 and I2 is shown in FIG.
Shown in FIG. 5A shows an example in which an nMOS transistor M11 is used as a constant current source. The gate voltage V _G as MOS transistor M11 is saturation operation is applied. Alternatively, a desired constant current characteristic may be obtained by connecting the body to the gate or the source or applying an appropriate voltage to the body. In this case, the MOS transistor M
11 is desirably formed on an SOI substrate. FIG. 5 (b)
Is an example using an nMOS transistor M12 and a resistor R5 as a constant current source. A voltage VG that causes the MOS transistor M12 to perform a saturation operation is applied to the gate. Alternatively, a desired constant current characteristic may be obtained by connecting the body to the gate or the source or applying an appropriate voltage to the body. In this case, it is desirable that the MOS transistor be formed on an SOI substrate.

FIG. 5C shows a bipolar current source as a constant current source.
This is an example using the transistor Q1. Tran on the base
A voltage V at which the transistor Q1 is activated._BIs added
You. FIG. 5D shows a bipolar transistor as a constant current source.
This is an example using a star Q2 and a resistor R6. In this example,
A voltage V such that the transistor Q2 is activated.
_BIs added.

Next, an example of a T-FF using a D-FF will be described. FIG. 6 is a block diagram in which the output S of the D-FF is connected to the inverted input DN. In this block diagram, the complementary signal shows DN, CK, and S on only one side.

FIG. 7 shows a specific circuit configuration of the above block diagram. The other configuration is exactly the same as that of FIG. 1 except that the output S is connected to the input DN and the output SN is connected to the input D with respect to the D-FF. The T-FF performs a frequency dividing operation to reduce the frequency of the clock CK to 1/2. Next, this frequency dividing operation will be described with reference to a timing chart.

FIG. 8 shows operation waveforms of the clock CK, the node M, and the output node S. In the master stage 1, when the clock CK rises, the resistance elements R1, R2,
The differential circuit including the MOS transistors M1 and M2 operates, and the latch circuit including the MOS transistors M3 and M4 does not operate. At this time, assuming that the output S is at a high level, the node M goes to a low level. When the clock CK falls, the differential circuit becomes inactive and the latch circuit operates, so that the node M remains at the low level.

In the slave stage 2, when the clock CK falls, the differential circuit including the resistance elements R3 and R4 and the MOS transistors M5 and M6 operates, and the latch circuit including the MOS transistors M7 and M8 becomes inactive. .
At this time, since the node M is at the high level, the output S of the differential circuit is at the low level. When the clock CK rises, the differential circuit becomes inactive and the latch circuit operates, so that the output S remains at the low level. Therefore, each time the clock CK falls, the state of the output S changes, and an output S having a frequency half the frequency of the clock CK is obtained.

The D-FF or T-FF described above comprises a master stage 1 and a slave stage 2, and an output signal is output from the slave stage 2. Now, considering a case where a plurality of D-FFs or T-FFs are cascaded, this output signal may be a clock signal of the next stage. For example,
When two T-FFs are cascaded to form a 1/4 frequency divider, the output of the first T-FF becomes the clock signal of the second T-FF. Since the clock signal CK is input to the body of the MOS transistor, there is a concern that the input impedance is low and the signal level is reduced. Therefore, in order to prevent this, the output signal of the slave stage 2 is amplified by a buffer having a high input impedance.

FIG. 9 shows a D-FF using a source-coupled logic circuit as a buffer. 1 is a master stage, 2 is a slave stage, and 4 is a buffer stage. The master stage 1 and the slave stage 2 are the same as those in FIG.

In the buffer stage 4, R7 is the power supply voltage V
R8 is a resistance element connected between the power supply voltage V _DD and the node Z, and M8 is a resistance element connected between the _DD and the node ZN.
Reference numeral 13 denotes an nM having a drain connected to the node ZN, a gate connected to the node S, and a source connected to the node E3.
OS transistor, M14 has a drain connected to the node Z, a gate connected to the node SN, a source nMOS transistor connected to the node E3, I3 is a constant current which is connected between the ground voltage V _SS and node E3 Source.

The specific examples of the resistance elements R7 and R8 are the same as in FIG. 4, and the specific examples of the constant current source I3 are the same as in FIG. This D-FF performs the same operation as that of FIG.
Even when the input impedance of the next stage is low, the signal level does not decrease. Also, the T-FF can be configured by connecting the outputs S and SN of the slave stage 2 to the inputs DN and D, respectively, as in FIG.

Next, consider the minimum power supply voltage for operating the D-FF or T-FF. FIG. 4 as a resistance element
Considering the case where the resistor R in FIG. 5A and the MOS transistor M11 in FIG. 5A are used as the constant current source, both the master stage 1 and the slave stage 2 have two MOS transistors and a resistor 1.
Cascade connection of stages. The drain-source voltage at which the MOS transistor M11 operates should be at least 0.3
_Assuming that V is V and the operating amplitude is at least 0.3 V in consideration of noise margin, the minimum power supply voltage V _CCmin (V) is V _CCmin = 0.3 + 2 × 0.3 = 0.9.

As described above, the D-FF or T
The -FF can reduce the minimum operating voltage to 1 V or less even in consideration of a margin of 10% due to variation in voltage fluctuation, and can achieve low power consumption of a wireless unit in a portable information device. Further, the operation speed is the master stage 1 or the slave stage 2
The high-speed operation is not hindered even if the low-voltage operation is performed.

The reason why the minimum power supply voltage can be reduced in this embodiment is as follows. That is, in the present embodiment, MOS transistors are formed on an SOI substrate, and a clock signal is applied to the body region of each MOS transistor to control its driving capability, thereby reducing the number of elements from the power supply terminal to the ground terminal. Can be reduced. this is,
In contrast to the conventional circuit shown in FIG.
This corresponds to eliminating MOS transistors corresponding to 9, 110, 111, and 112. In other words, the number of cascade stages from the power supply terminal to the ground terminal can be reduced by one step, whereby the minimum power supply voltage can be reduced.

(Second Embodiment) FIG. 10 is a circuit diagram showing a D-FF according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment has basically the same configuration as the circuit of FIG. 1, but the signals applied to the gate and the body are
The circuit is reversed. That is, the signal D,
Clocks CK and CKN are input instead of DN, and signals D and DN are input to the body side instead of clocks CK and CKN.

In the slave stage 1, M21 is an nMOS transistor whose drain is connected to the node M, whose gate receives the clock CK, whose source is connected to the node E21, and whose body receives the input signal D. MN, an nMOS transistor having a gate connected to the clock CK, a source connected to the node E21, a body connected to the input signal DN, and a drain M23 connected to the node M and a gate connected to the clock CKN.
, An nMOS transistor having a source connected to the node E21 and a body connected to the node MN,
Is an nMOS transistor whose drain is connected to the node MN, whose gate receives the clock CKN, whose source is connected to the node E21, and whose body is connected to the node M.

In the slave stage 2, M25 is an nMOS transistor having a drain connected to the node S, a gate to which the clock CKN is input, a source connected to the node E22, and a body connected to the node M, and M26 having a drain connected. Connected to node SN, clock CK at gate
An NMOS transistor M2 having an input N, a source connected to the node E22, and a body connected to the node MN;
Reference numeral 7 denotes an nMOS transistor having a drain connected to the node S, a clock CK input to the gate, a source connected to the node E22, and a body connected to the node SN;
28 has a drain connected to the node SN, a clock CK input to the gate, a source connected to the node E22,
The body is an nMOS transistor connected to the node S.

Note that M21 to M28 are formed using an SOI substrate or the like in which a body region is separated for each transistor.

Next, the operation of the D-FF will be described. In the master stage 1, the MOS transistors M21, M2
2, the clock CK is input to the gate of the MOS transistor M23 and the clock CKN is input to the gates of the MOS transistors M23 and M24. Therefore, when the clock CK is at the high level, the driving capability of the MOS transistors M21 and M22 is It will be bigger than that. Conversely, when the clock CK is at the low level, the MOS transistor M2
1 and M22 are driven by MOS transistors M23 and M23.
24 is smaller than that.

Since a constant current always flows in the master stage 1 by the constant current source I1, when the clock CK rises, the resistance elements R1 and R2 and the MOS transistors M21 and M2
2 operates, and the MOS transistor M2
3 and M24 are deactivated, and the input signal D is taken into the master stage 1. When the clock CK falls, the differential circuit becomes inactive, the latch circuit operates, and the fetched signal is latched.

Similarly, when the clock CK falls, the resistance elements R3, R4 and the MOS transistors M25, M26
Operates, and the MOS transistor M2
7 and M28 become inactive, and the information of the node M is taken into the slave stage 2. Clock CK
Rises, the differential circuit becomes inactive, the latch circuit operates, and the fetched signal is latched. In this manner, the same operation as in the first embodiment can be performed.
Further, the point that the outputs S and SN of the slave stage 2 are connected to the inputs DN and D, respectively, to form a T-FF is also the same as in the first embodiment.

Also in this embodiment, a buffer may be added to prevent the signal level from lowering even when the input impedance of the next stage is low. FIG. 11 shows a D using the same source-coupled logic circuit as in FIG.
-FF. In the case of forming a T-FF, if the outputs Z and ZN of the buffer stage are connected to the inputs DN and D, respectively, the output signal level of the slave stage 2 can be prevented from lowering.

In FIG. 10 or FIG. 11, since the output of the master stage 1 is input to the body of the MOS transistor of the slave stage 2, there is a concern that the signal level of the master stage 1 will decrease. Therefore, in order to prevent this, the output signal of the master stage 1 may be amplified by a buffer having a high input impedance and input to the slave stage.

FIG. 12 shows an example of such a D-FF. 1 is a master stage, 2 is a slave stage, 4 is a buffer stage for preventing a decrease in output of the slave stage, and 5 is a buffer stage for preventing a decrease in output of the master stage. The master stage 1, the slave stage 2, and the buffer stage 4 are the same as those in FIG. Buffer stage 5 is buffer stage 4
In this case, a source-coupled logic circuit is used.

In the buffer stage 5, R9 is the power supply voltage V
Resistance element connected between _DD and node XN, R10 is resistance element connected between the power supply voltage V _DD and the node X,
M29 has a drain connected to the node XN, a gate connected to the node M, and a source connected to the node E4.
MOS transistors, M30 has a drain connected to the node X, its gate connected to node MN, a source nMOS transistor connected to the node E4, I4 constant current connected between the node E4 and the ground voltage V _SS Source. The specific examples of the resistance elements R9 and R10 are the same as in FIG. 4, and the specific examples of the constant current source I4 are the same as in FIG.

In this D-FF, the same operation as in FIG. 1 is performed, and the output signal levels of the master stage 1 and the slave stage 2 do not decrease. The outputs Z and ZN of the buffer stage 4
Are connected to the inputs DN and D, respectively, to form a T-FF as in FIG.

(Third Embodiment) FIG. 13 is a block diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention. This circuit includes an OR circuit to which signals D1 and D2 are input, and a D-FF to which an output of the OR circuit is input. In this block diagram, only one side of the complementary signal is shown.

FIG. 14 is a diagram showing a specific circuit configuration of the block diagram shown in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is different from the circuit of FIG.
That is, two MOS transistors are used instead of the MOS transistor M1 of the master stage 1. M15 is an nMOS transistor having a drain connected to the node M, an input signal D1 input to the gate, a source connected to the node E1, a clock CK input to the body, and M16 a drain connected to the node MN and an input to the gate. Signal D2
Are input, the source is connected to the node E1, and the clock CK is input to the body.

Note that M2 to M8, M15, and M16 are formed using an SOI substrate or the like in which a body region is separated for each transistor. Further, it is desirable that the input signal DN is set to a constant potential between the high level and the low level of the input signal D1 or D2.

Next, the operation of this circuit will be described. FIG.
Shows operation waveforms of the clock CK, the inputs D1, D2, and DN, the node M, and the output node S. In the master stage 1, the clock CK is input to the bodies of the MOS transistors M15, M16, and M2, and the MOS transistors M3, M3
Since the clock CKN is input to the body of M4, when the clock CK is at the high level, the MOS transistor M1
5, M16 and M2 have MOS transistors M
3, larger than that of M4. Conversely, clock CK
Is low level, the MOS transistors M15, M1
6 and M2 have smaller driving capabilities than those of the MOS transistors M3 and M4.

Since a constant current always flows through the master stage 1 by the constant current source I1, when the clock CK rises, the resistance elements R1 and R2 and the MOS transistors M15 and M1
The differential circuit composed of MOS transistors M3 and M2 operates, and the latch circuit composed of MOS transistors M3 and M4 is deactivated. When both of the input signals D1 and D2 are at a low level, the node M is at a high level. When at least one of D1 and D2 is at a high level, the node M is at a low level. Therefore, the logical sum of the input signals D1 and D2 is taken into the master stage 1.
When the clock CK falls, the differential circuit becomes inactive, the latch circuit operates, and the fetched signal is latched.

Similarly, when the clock CK falls, a differential circuit including the resistance elements R3 and R4 and the MOS transistors M5 and M6 operates, and the MOS transistors M7 and M8 operate.
, And the information of the node M is taken into the slave stage 2. When the clock CK rises, the differential circuit becomes inactive, the latch circuit operates, and the fetched signal is latched. Also in this case, the logic operation shown in FIG. 13 can be realized with an operation voltage of 1 V or less.

(Fourth Embodiment) FIG. 16 is a circuit diagram showing a multiplier according to a fourth embodiment of the present invention.
The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

M31 has a drain connected to the node O,
An nMOS transistor in which the signal S1 is input to the gate, the source is connected to the node E1, the signal S2 is input to the body, and the drain of M32 is connected to the node BO, the signal S3 is input to the gate, and the source is connected to the node E1. And
This is an nMOS transistor to which the signal S4 is input to the body. Note that M31 to M32 are formed using an SOI substrate or the like in which a body region is separated for each transistor.

Next, the operation of this circuit will be described. MOS
The drain current flowing through the transistor 31 is modulated by the signal S1 input to the gate and the signal S2 input to the body, and the output O has a multiplication component S1 · S2 of these signals.
Output. Similarly, the drain current flowing through the MOS transistor 32 is modulated by the signal S3 input to the gate and the signal S4 input to the body, and the output BO outputs multiplication components S3 and S4 of these signals. Assuming that signal S3 is the complement of signal S1 and signal S4 is the complement of signal S2, output BO is the complement of output O.

These output signals are amplified and output by the current switch type circuit configuration. Also, by providing a difference between the DC bias voltages of the signal S2 and the signal S4, the MO
It is also possible to correct for variations in threshold voltages of the S transistor M31 and the MOS transistor M32.

FIG. 17 is a circuit diagram of another multiplier performing the same operation as that of FIG. M33 is an nMOS having a drain connected to the node O, a gate receiving the signal S1, a source connected to the node E1, and a body receiving the signal S2.
The transistor M34 is an nMOS transistor having a drain connected to the node BO, a gate receiving the signal S3, a source connected to the node E1, and a body receiving the signal S2, and M35 having a drain connected to the node O and a gate connected to the node O. An nMOS transistor to which the signal S3 is input, the source is connected to the node E1, the signal S4 is input to the body, and the drain of the M36 is connected to the node BO, the signal S1 is input to the gate, and the source is connected to the node E1,
This is an nMOS transistor to which the signal S4 is input to the body.

Note that M33 to M36 are formed using an SOI substrate or the like in which a body region is separated for each transistor.

Here, assuming that the signal S3 is a complementary signal of the signal S1 and the signal S4 is a complementary signal of the signal S2, the output BO is a complementary signal output of the output O. Also in this circuit, a multiplied component of the input signals S1 and S3 is amplified and output to the outputs O and BO.

(Modification) The present invention is not limited to the above embodiments. In the first and third embodiments, the example in which the clock signal is input to the body is shown, and in the second embodiment, the example in which the clock signal is input to the gate is shown. However, these can be appropriately combined. For example, a MOS transistor forming a differential circuit may input a clock signal to a body, and a MOS transistor forming a latch circuit may input a clock signal to a gate. The present invention is also effective when a transistor inputs a clock signal to a gate and a MOS transistor forming a latch circuit inputs a clock signal to a body.

In the embodiment, the SOI substrate is used. However, a substrate in which a semiconductor layer other than silicon is formed on an insulating film can be used. In addition, various modifications can be made without departing from the scope of the present invention.

[0081]

As described in detail above, according to the present invention, the minimum power supply voltage can be reduced without sacrificing high speed.
A current switch type semiconductor integrated circuit represented by a D-FF operating at a lower voltage (for example, 1 V or lower) can be realized. Therefore, the power supply voltage can be shared between the radio unit and the baseband unit operating at a low voltage, and a voltage conversion circuit is not required or its load is reduced. Further, the power consumption of the prescaler and the mixer using the same can be reduced, and the power consumption of the portable information device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a D-FF according to a first embodiment.

FIG. 2 is a block diagram of a D-FF in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the D-FF in FIG. 1;

FIG. 4 is a view showing a specific example of a resistance element used in the D-FF of FIG. 1;

FIG. 5 is a diagram showing a specific example of a constant current source used in the D-FF of FIG.

FIG. 6 is a block diagram showing a T-FF according to the first embodiment.

FIG. 7 is a diagram showing a specific circuit configuration of the T-FF in FIG. 6;

FIG. 8 is a timing chart for explaining the operation of the T-FF in FIG. 7;

FIG. 9 is a circuit diagram showing another example of the D-FF according to the first embodiment.

FIG. 10 is a circuit diagram illustrating a D-FF according to a second embodiment.

FIG. 11 is a circuit configuration diagram showing another example of a D-FF according to the second embodiment.

FIG. 12 is a circuit diagram showing still another example of a D-FF according to the second embodiment.

FIG. 13 shows a DF with an OR gate according to the third embodiment.
The block diagram which shows F.

FIG. 14 is a diagram showing a specific circuit configuration of the D-FF of FIG.

FIG. 15 is a timing chart for explaining the operation of the D-FF in FIG. 14;

FIG. 16 is a circuit configuration diagram showing a multiplier according to a fourth embodiment.

FIG. 17 is a circuit diagram showing another example of the multiplier according to the fourth embodiment.

FIG. 18 is a circuit diagram showing a conventional D-FF.

FIG. 19 is a timing chart for explaining the operation of the D-FF in FIG. 18;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Master stage 2 ... Slave stage 3 ... Level shift stage 4, 5 ... Buffer M1-M16, M21-M36 ... MOS transistor R1-R8 ... Resistance element I1-I4 ... Constant current source R, R102-R108 ... Resistance Q1 Q2, Q101 to Q118 ... Bipolar transistors

Claims (9)

[Claims] A first MOS transistor having a drain connected to a first node, a source connected to a second node, a gate receiving a first signal, and a body receiving a second signal; A drain connected to the third node and a source connected to the second node;
A second MOS transistor connected to a third node, a third signal input to the gate, and a fourth signal input to the body; and a constant current source connected between the second node and a ground terminal. A semiconductor integrated circuit, comprising: 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor layer on the insulating film is used as an element forming substrate, and the transistors are formed on the substrate. 3. The semiconductor integrated circuit according to claim 1, wherein the first signal and the third signal are complementary signals, and the second signal and the fourth signal are the same signal. 4. The semiconductor integrated circuit according to claim 1, wherein the second signal and the fourth signal are complementary signals, and the first signal and the third signal are the same signal. 5. The semiconductor integrated circuit according to claim 1, wherein the first signal and the third signal are complementary signals, and the second signal and the fourth signal are complementary signals. 6. A semiconductor integrated circuit using a semiconductor layer on an insulating film as an element forming substrate, wherein a drain is connected to a first node, a source is connected to a second node, and a gate is connected to the first node. A first MOS transistor to which a signal is input and a second signal is input to the body; a drain connected to a third node; and a source connected to the second node.
A second MOS transistor having a gate to which a third signal which is a complementary signal of the first signal is input, and a body to which the second signal is input; A first resistance element connected between the third node and a power supply terminal; and a second resistance element connected between the third node and the power supply terminal.
And a first constant current source connected between the second node and a ground terminal. 7. A semiconductor integrated circuit using a semiconductor layer on an insulating film as an element formation substrate, wherein a drain is connected to a first node, a source is connected to a second node, and a gate is connected to the first node. A first MOS transistor to which a signal is input and a second signal is input to the body; a drain connected to a third node; and a source connected to the second node.
A second MOS transistor having a gate to which a third signal which is a complementary signal of the first signal is input, and a body to which the second signal is input; and a drain connected to the first node. A third MOS transistor having a source connected to the second node, a gate connected to the third node, and a fourth signal which is a complementary signal of the second signal input to the body. And a drain connected to the third node, a source connected to the second node, a gate connected to the first node, and a fourth signal input to the body.
An OS transistor, a first resistance element connected between the first node and a power supply terminal, and a second resistance element connected between the third node and the power supply terminal
And a first constant current source connected between the second node and a ground terminal. 8. A fifth MOS transistor having a drain connected to a fourth node, a gate connected to the first node, a source connected to a fifth node, and a drain connected to a sixth node. Connected and the gate is the third
A sixth MOS transistor having a source connected to the fifth node, and a second constant current source connected between the fifth node and a ground terminal. 8. The semiconductor integrated circuit according to claim 6, wherein: 9. A master circuit according to claim 6 or 7, wherein an output signal appearing at said first node is input in place of said first signal and said third circuit is input in said third circuit. And a slave circuit for inputting an output signal appearing at the third node in place of the above signal.