JP2002112203A - Interpolation signal generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interpolation signal generating device that suppresses a tilt edge of an image pattern from being fluctuated on an image even when applying in-field interpolation to a video signal with the image pattern in a tilt direction. SOLUTION: A block signal generating circuit 17 extracts a pixel pair in point symmetry relation around a position of an interpolated pixel and a correlation detection circuit 22 detects the correlation of pixel information of each pixel pair and decides interpolated pixel information on the basis of a pixel pair having the high correlation to generate an interpolation signal. The correlation detection circuit 22 detects the correlation of the pixel pair on the basis of pixel information in an area including pixels around each pixel of the pixel pair and pixel information of an area including pixels around the interpolated pixel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interpolation signal generator applied to a progressive scan converter for converting an interlaced television signal into a progressive scan signal, and more particularly, to suppressing deterioration of the image quality of a moving image portion. The present invention relates to a circuit for generating an interpolated signal capable of performing an interpolation.

[0002]

2. Description of the Related Art In converting an interlaced television signal into a progressive scanning television signal, if the video is a still image, the two field signals constituting one frame are directly scanned by each other. Fit in between,
By performing so-called inter-field interpolation, it is possible to convert to a progressive scanning method without any problem. However, if the video is a moving image, performing inter-field interpolation may make two vertical lines appear, In some cases, distortion such as saw-toothing may occur, and the image quality may be significantly impaired. Therefore, in a moving image portion, an interpolation signal is generated based on video information of adjacent scanning lines in the same field, and so-called intra-field interpolation is performed in which the interpolation signal is inserted between the scanning lines.

That is, as shown in FIG. 9, a video signal 8 supplied to an input terminal 81 is used as a progressive scan converter.
2, a still image interpolation signal generation device 84, a moving image interpolation signal generation device 85, and a mixer that mixes the still image interpolation signal and the motion image interpolation signal based on the detection output of the motion detection circuit 83. 86, a selector 87 that operates to fit the output of the mixer 86 between the corresponding scanning lines of the input video signal 82, and a double-speed conversion circuit 88 that doubles the horizontal scanning line frequency of the output video signal of the selector 87. It has.

The motion detection circuit 83 has a frame memory, compares video signals between frames, recognizes a non-coincidence portion as a moving image portion, and outputs a detection signal.

[0005] The still image interpolation signal generator 84 has a field memory and outputs the video signal one field before as it is as an interpolation signal.

The moving picture interpolation signal generator 85 has a memory for storing a video signal for one horizontal scanning period (1H), and this memory is used as a delay line to store the current video signal and 1H.
An interpolation signal is generated and output based on a signal obtained by adding the previous video signal.

[0007] Such an interlace-sequential scanning conversion device is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-179890.

FIG. 10 is a specific block diagram of the motion picture interpolation signal generating device 86. The 1H memory 92 functions as a delay line for delaying the video signal 82 supplied to the input terminal 91 by 1H, and the video signals 82 and 1H. An adder 93 for adding the output of the memory 92;
2 and an amplifier 94 for outputting.

That is, in the circuit shown in FIG. 9, the average of the adjacent 1H video signals, that is, the average of the pixel information in the vertical direction of the screen, is obtained, and the gain is halved and output as an interpolation signal.

This output signal is to be interpolated between the original scanning lines that produced the interpolation signal, and is present at the same position from the scanning start point on each of two adjacent scanning lines a and b. Assuming pixels to be Ya and Yb, the luminance Ym of the interpolated pixel is Ym = (Ya + Yb) / 2.

FIG. 11 schematically shows the display state of the screen after the interpolation has been performed. On the scanning line a, up to four pixels from the beginning have high luminance and thereafter have low luminance, and on the scanning line b, the first two pixels have high luminance and thereafter have low luminance. In the scanning line X, pixels having different luminances in the vertical direction of the screen are averaged.
That is, compared to the state before the interpolation, the averaged pixels are advanced in the vertical upward direction on the screen, and the degree of play of the boundary of the picture formed by these pixels is emphasized.

As described above, in the conventional progressive scan converter,
Interpolation without problems is possible with still images, but the circuit that creates the in-field interpolation signal corresponding to the moving image portion is not necessarily adapted to all pictures, and especially at the borders of pictures in the tilt direction. There was a situation where the rattling was emphasized and satisfactory progressive scan conversion could not be performed.

[0013]

The conventional interpolation signal generating apparatus merely outputs the interpolation signal of the moving image portion by averaging the video signal between adjacent scanning lines in the vertical direction, and outputs the interpolation signal. The interpolated screen has a problem that, depending on the picture, the backlash is emphasized at the boundary portion thereof, making the screen difficult to see.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and detects a correlation between pixel information of a pair of pixels having a point-symmetric positional relationship with respect to a pixel interpolation position. It is an object of the present invention to provide an interpolation signal generation device that can output an interpolation signal with less noticeable play by obtaining an interpolation signal based on the interpolation signal.

[0015]

SUMMARY OF THE INVENTION An interpolation signal generating apparatus according to the present invention generates an interpolation signal for interpolating between scanning lines of a television signal in which each scanning line is composed of a plurality of pixels each having pixel information. In the interpolation signal generating device, extracting means for extracting a plurality of pixel combinations having a point-symmetric relationship within a predetermined range of an adjacent scanning line in which the interpolation signal is to be interpolated, with the pixel position of the interpolation signal as a center. Finding the difference between the respective pixel information of each extracted pixel pair, detecting means for detecting the correlation of each pixel pair from the difference value, based on the correlation determined by the detecting means,
Generating means for determining interpolation pixel information and generating an interpolation signal.

According to this, the correlation of the pixel information of the pixel pair having a point-symmetrical positional relationship with respect to the position where the pixel is to be interpolated is detected, and the pixel pair having the highest correlation is specified. Since the interpolation signal is generated based on the specified pixel information, the screen display after the interpolation can be prevented from rattling even in the shape having the boundary in the oblique direction, and the image quality can be improved.

Further, the present invention provides an interpolation signal generating apparatus for generating an interpolation signal for interpolating between scanning lines of a television signal in which each scanning line is composed of a plurality of pixels. Extracting means for extracting a combination of two pixels having a point-symmetrical relationship between adjacent scanning lines about which the interpolation signal is to be interpolated, with the pixel position at the center,
Based on each pixel of the extracted pixel pair, the first and second regions including a plurality of pixels including the pixels existing around this pixel are specified, and each pixel information in each region is determined. Addition means for performing cumulative addition, detection means for obtaining a difference between the cumulative addition values in the first and second regions, and detecting the correlation of each pixel pair from the difference value, based on a detection result of the detection means Generating means for determining interpolation pixel information and generating an interpolation signal.

According to this, the pixel information of a predetermined area which is point-symmetric with respect to the interpolation pixel position, that is, the correlation is detected in units of picture information, and the interpolation pixel information is specified, so that more accurate pixel information is obtained. Interpolation becomes possible.

Further, according to the present invention, in an interpolation signal generating apparatus for generating an interpolation signal for interpolating between the scanning lines of a television signal in which each scanning line is composed of a plurality of pixels, a pixel position of the interpolation signal is determined. With respect to the center, there is a point symmetrical relationship between adjacent scanning lines for interpolating the interpolation signal.
Extracting means for extracting a combination of pixels; first and second pixels each including a plurality of pixels including pixels present around the extracted pixel pair with respect to each pixel of the extracted pixel pair
Adding means for specifying a region of the scanning line, specifying a third region composed of a plurality of pixels of the scanning line adjacent to each other around the interpolation pixel position, and accumulating each pixel information in each region. , The sum of the first area and the third
Detecting means for detecting the correlation of each pixel pair based on the difference between the added values of the areas, the added value of the second area, and the difference of the third area; Generating means for specifying interpolation pixel information and generating an interpolation signal.

According to this, the pixel information of the area which is point-symmetric with respect to the interpolation pixel position, that is, the correlation is detected in the unit of picture information in consideration of the pixel information of the predetermined area around the interpolation pixel position, and interpolation is performed. Since pixel information is determined, more accurate interpolation can be performed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an interpolation signal generating apparatus according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an interpolation signal generating apparatus according to the present invention.

In FIG. 1, a first 1H memory 13 capable of storing 1H of pixel information is connected to an input terminal 12 to which an input video signal 11 is supplied.
The output of the H memory is a second output having the same configuration as that of the first 1H memory.
And a block signal generation circuit 17 that specifies a block of pixels and outputs a block output signal for each block. Similarly, the output of the second 1H memory 14 is supplied to the third 1H memory 15 and the block signal generation circuit 17, and the output of the third 1H memory 15 is supplied to the fourth 1H memory 16 and the block signal generation circuit 17 Is supplied to

The output of the second 1H memory 14 is supplied to a first register 18a of a first register group 18 composed of eight registers 18a to 18h connected in series.

The output of the third 1H memory 15 is sent to the first register 19a of the second register group 19 composed of eight registers 19a to 19h connected in series similarly to the first register group. It is connected.

The registers 18a to 18h and 19a to 19h of the register groups 18 and 19 operate to accumulate and sequentially shift the pixel information of the adjacent scanning lines, respectively. Each output is supplied to the first selector 20 and the register 1
The outputs 9b to 19h are supplied to the second selector 21.

The correlation detection circuit 22 outputs the block output signals B1b to B7 output from the block signal generation circuit 17.
b, C7b... Based on C1b and Xb, a correlation between pixel pairs, which will be described later, is detected, and the detection result is supplied to first and second selectors 20 and 21.
Pixel information items having correlation with each other are selected from 19 and output to the adder 22.

The adder 22 adds the input pixel information to 1
The amplifier 23 amplifies the signal with a gain of / 2, and the amplifier 23 outputs an interpolation signal.

The specific example of the interpolation signal generating apparatus of the present invention is configured as described above. The operation of the apparatus will be described with reference to FIGS.

In FIG. 1, a video signal 11 supplied to an input terminal 12 is continuously transmitted to first to fourth 1H memories 13.
To 16 sequentially. These 1H memories 13-1
FIG. 2 schematically shows a part of the pixel information of the video signal accumulated in 6.

That is, the first scanning line A of the video signal is composed of pixels A0, A1, A2, A3, A4, A5, A6, A7,
A8 are sequentially stored in the fourth 1H memory 16, and the second scanning line B is B0, B1, B2, B3, B4, B
5, 1H memory 1 having B5, B6, B7 and B8 in this order.
5 and the third scan line C is C8, C7, C6,
C5, C4, C3, C2, C1, C0
, And the fourth scanning line D is
8, D7, D6, D5, D4, D3, D2, D1, D0
, And stored in the first 1H memory 13.

The video signals 11 stored in the second 1H memory 14 and the third 1H memory 15 are read and sequentially stored in the first and second register groups 18 and 19.

On the other hand, the first to fourth 1H memories 13 to 16
Are read out and supplied to the block signal generating circuit 17.

As shown in FIG. 2, when trying to interpolate between the B4 pixel of the scanning line B and the C4 pixel of the scanning line C with the interpolation pixel x, the block signal generation circuit 17 firstly sets the vertical direction of the interpolation pixel x. (2n-1) pixels A1 to A2 in the horizontal direction from the pixels existing on the upper and lower scanning lines B and C in the horizontal direction around the pixels B4 and C4 corresponding to the interpolation pixels.
7, a first area 201 indicated by a dotted line in a diagram composed of pixels B7 to B1 (n = 4 in this case) is specified.

The block signal generation circuit 17 further includes seven pairs of pixels B1-C1, B2-C2, and B1-C1, B2-C2,
3-C3, B4-C4, B5-C5, B6-C6, B7
−C7 is extracted, and a second area 202 and a third area 203, each of which is composed of three pixels in the horizontal direction and three scanning lines in the vertical direction, are specified with the pixel of each pixel pair as the center. I do.

FIG. 2 shows an example of a pair of the pixel B5 and the pixel C5, and the pixels A4, A5, A6 and the pixels B4, B
Region 2 composed of pixels 5, B6 and pixels C4, C3, C2
02, pixels B2, B3, B4 and pixels C6, C5, C4
And an area 203 including the pixels D6, D5, and D4.

As can be easily understood from FIG.
Reference numerals 02 and 203 denote pixels 1 in the vertical, horizontal, and oblique directions, respectively, with the extracted pixel pair as the center.
And at least a part of the picture is constituted by these pixels.

The block signal generation circuit 17 further adds, to each pixel information of the areas 202 and 203 specified in this way,
A filtering process is performed by multiplying the pixels of each pixel pair by a predetermined coefficient. That is, as shown in FIG. 3, the pixel information of the pixel B5 of the pixel pair located at the center of the region is 1/4.
, And each pixel information of pixels A5 and C3 adjacent in the vertical direction and pixels B5 and B6 adjacent in the horizontal direction is respectively divided by 1 /
Multiplied by a coefficient of 8 to obtain pixels A4, A6, C4, C
2 pixel information is multiplied by 1/16 coefficient. By this processing, the high frequency components in the horizontal and vertical directions are suppressed for each region, and the low frequency components are extracted.

Next, the block signal generation circuit 17 cumulatively adds all the pixel information multiplied by the coefficients in the regions 202 and 203, respectively. The region identification, the filtering process, and the addition process are performed for each pixel of the pixel pair having a point-symmetric positional relationship with the interpolation pixel position x, and block signals B1b... B7b and C7 are provided for each pixel of each pixel pair.
b ... Output as C1b. That is, seven outputs corresponding to one pixel of each pixel pair are block signals B1b.
7b, and seven outputs corresponding to the other pixel of each pixel pair are block signals C7b... C1b.

For example, a region 202 centered on the pixel B5
B5b = (A4 / 16) + (A5 / 8) + (A6 / 1
6) + (B4 / 8) + (B5 / 4) + (B6 / 8) +
(C4 / 16) + (C3 / 8) + (C2 / 16).

Similarly, an area 203 centered on the pixel C5
Of the block signal C5b is expressed as follows: C5b = (B2 / 16) + (B3 / 8) + (B4 / 1
6) + (C6 / 8) + (C5 / 4) + (C4 / 8) +
(D6 / 16) + (D5 / 8) + (D4 / 16).

The correlation detection circuit 22 calculates the difference between the block signals output from the block signal output circuit 17 for each pixel pair, and recognizes the pixel pair having the smallest difference as the pixel pair having the highest correlation. Then, a detection signal for selecting the pixel information is supplied to the first and second selectors 20 and 21.

Each register 18a of the first register group 18
To 18h, the pixel information of the scanning line read from the third 1H memory 15 is sequentially transferred, and the pixel at the position corresponding to the interpolation pixel position (pixel B4 in FIG.
8e, and pixel information of pixels (pixels B1 to B3 and pixels B5 to B7 in FIG. 2) located before and after the interpolation pixel position are stored in registers 18b to 18d and 18g to 18h before and after the pixel. As the interpolation pixel position moves, the pixel information of the registers 18a to 18h also shifts.

Further, the pixel information of the scanning line read from the second 1H memory 14 is sequentially transferred to each of the registers 19a to 19h of the second register group 19, and a pixel (pixel) corresponding to the interpolation pixel position is transferred. In FIG. 2, the pixel C4) is the register 1
9e, and pixel information of pixels (pixels C7 to C5 and pixels C3 to C1 in FIG. 2) located before and after the interpolation pixel position are stored in registers 19b to 19d and 19g to 19h before and after that. As the interpolation pixel position moves, the pixel information of the registers 19a to 19h also shifts.

The pixel pair having the highest correlation with the interpolated pixel position x shown in FIG. 2 is the pixel pair B5 on the second scanning line B,
The pixel C5 of the third scanning line C, and the correlation detection circuit 22
Outputs a detection signal to the first selector 20 so as to select the output of the register 18f in which the pixel B5 is stored as a result of the processing, and selects the output of the register 19d in which the information of the pixel C5 is stored. As in the second selector 2
1 to output a detection signal.

Accordingly, in the adder 22, the pixel information of the pixels B5 and C5 are added, and the pixel information whose gain has been reduced to 増 幅 器 by the amplifier 23 is output as interpolation pixel information. That is, in this case, a pixel having black dot pixel information at the interpolation pixel position x is interpolated.

By performing the above-described processing for each interpolated pixel position, the amplifier 23 outputs an interpolated signal as a set of interpolated pixel information.

For example, in the case of the pixel arrangement shown in FIG. 2, the interpolated scanning line X interpolated between the second and third scanning lines B and C is, as shown in FIG. Pixel pair B3
−C7, the pixel information of the interpolation pixel X3 is determined based on the pixel pair B4-C6, and the pixel information of the interpolation pixel X4 is determined based on the pixel pair B5-C5 as described above. , X6, respectively,
It is determined based on the pixel pairs B6-C4, B7-C3.

As is clear from FIG. 4, the boundary between white circles and black circles is present diagonally as pixel information, and it is possible to suppress the backlash of the inclined portion of the screen.

As described above, according to the first embodiment of the present invention, a pixel pair having point symmetry around an interpolation pixel position is extracted, and a pixel pair having the highest correlation among these pixel pairs is determined. Since the interpolated pixel information is determined based on the pixel pair, it is possible to perform a smooth display by suppressing the backlash of the outer shape of the shape inclined on the screen. Further, since the correlation of the pixel information of the pixel pair is detected as a part of the picture including a plurality of pixels adjacent to the pixel pair, the detection accuracy of the correlation is improved.

Next, a description will be given of a second embodiment of the interpolation signal generating apparatus according to the present invention.

In the second embodiment, the block signal output circuit 17 is composed of six pixels B3, B4, B5 and C5, C4, C3 adjacent to the interpolated pixel x shown in FIG. As shown in FIG. 5, an area 204 is specified, and each pixel information of the area 204 is multiplied by a coefficient according to the distance from the interpolated pixel x, and then added to output a block signal Xb. Have been. The coefficient multiplied by each pixel is 1/4 in the vertical direction of the interpolation pixel x and 1/8 in the oblique direction.

That is, when the position of the interpolated pixel is x in FIG. 2, the block signal Xb is as follows: Xb = (B3 / 8) + (B4 / 4) + (B5 / 8) +
(C5 / 8) + (C4 / 4) + (C3 / 8).

In this embodiment, the correlation detection circuit 22
Are the second and third regions 202 and 203 centered on the pixels of each pixel pair supplied from the block signal output circuit 17.
Block signal B1 obtained by cumulatively adding the respective pixel information of
.. B7b and C7b and C7b and the difference B1s... B7s and C7s.
C1s, and then add the differences to obtain additional outputs AD1... AD7.

That is, when processing the block signal B5b of the area 202 centered on the pixel B5 and the block signal C5b of the area 203 centered on the pixel C5 in FIG. 2, B5s = B5b-Xb C5s = C5b-Xb AD5 = | B5s | + | C5s |

The above processing is performed for each pixel pair.
The addition outputs AD1 to AD7 are obtained for each of the seven pixel pairs existing in the first area 201 in FIG. Further, an offset value L that increases as the pixel pair moves away from the interpolated pixel x is added to the addition outputs AD1 to AD7.

In the case of AD5, AD5 = | B5s |
+ | C5s | + L.

The correlation detection circuit 22 outputs each of the addition outputs AD1 to AD1.
AD7 is compared to identify the pixel pair corresponding to the smallest addition output, and supply the selectors 20 and 21 with a detection signal for selecting the register output of the first and second register groups in which they are stored. I do.

In this embodiment, the first
As in the first embodiment, the display of the inclined boundary portion can be performed without backlash.Moreover, by detecting the correlation of the pixel pair, by taking into account the pixel information around the interpolation pixel position, It is possible to further improve the detection accuracy of the correlation.

FIG. 6 is a circuit diagram showing a specific circuit configuration of a circuit for specifying each region and collecting pixel information of each pixel in the block signal generation circuit 17 of the block diagram of FIG.

The pixel information collecting circuit in the block signal generating circuit 17 includes an input terminal 51 to which pixel information constituting the first scanning line A of FIG. An input terminal 52 to which pixel information constituting the second scanning line B of FIG. 2 read from the 1H memory 15 is supplied, and a third scanning line C of FIG. And an input terminal 54 to which pixel information constituting the fourth scanning line D of FIG. 2 read from the first 1H memory 13 is supplied. . Each of the input terminals 51 to 54 has nine registers 51a.
52i, 53a... 53i, 54a... 54i.

In the registers 51e, 52e, 53e and 54e located at the center of each of the register groups, pixel information of the position corresponding to the interpolation pixel position in each scanning line is accumulated, and the interpolation pixel position moves. The pixel information is sequentially shifted accordingly.

Each register 51a ... 51i, 52a ... 52
53i, 54a... 54i are collectively output to an adder, which will be described later, as outputs via an amplifier that multiplies the surrounding pixel information by a predetermined coefficient shown in FIG. 3 for each pixel pair. Sent.

For example, assuming that the pixel information of B1 shown in FIG. 2 is stored in the register 52b, its own pixel information is output as an output 52b5 via a 1/4 amplifier, and the register 51a which is the pixel information of the pixel A0 is output. Information is 1/1
The signal is output as a 52b1 signal through the
If the information of the register 51b storing one pixel information is 1
Is output as 52b2 via a / 8 amplifier, and
The information of the register 51c in which the pixel information of
It is output as 52b3 via a / 16 amplifier.

Similarly, the register 52a (pixel B0)
Of the register 52c (pixel B2) is output as 1/8 of the pixel information of the register 52c (pixel B2).
Output as 52b6 via the amplifier
The pixel information of a is output as 52b7 via (1/16 amplifier), the information of register 52b is output as 52b8 output via 1/8 amplifier, and the information of pixel 52c is output as 52b9 via 1/16 amplifier. These are collectively output to an adder to perform cumulative addition.

FIG. 7 shows a block signal generation circuit.
The pixel information collected by the pixel information collection circuit is
It is a block diagram which shows the adder which adds for every 2,203,204.

In FIG. 7, the second region 2 in FIG.
Adders 55a to 55g for cumulatively adding all the pieces of pixel information in the pixel information 02 are provided.
, The output of the register storing each pixel information is supplied via an amplifier which multiplies the coefficient shown in FIG.

The adder 55a performs the cumulative addition of the area 202 centered on the pixel B1 in FIG.
And the adders 55b to 55g each output a pixel B
Region 2 centered on 2, B3, B4, B5, B6, B7
02 block outputs B2b to B7b
Is output.

Further, adders 56a to 56c for accumulatively adding all the pieces of pixel information in the third area 203 in FIG.
An adder 56a is provided with an output of a register storing each pixel information via an amplifier which multiplies the coefficient shown in FIG.

The adder 56a performs a cumulative addition of the third area 203 centering on the pixel C7 in FIG. 2 to output a block output C7b, and the adders 56b to 56g respectively output the pixels C6, C5, C4 and C4. A block output C6 which is a cumulative addition output of the third area 203 centered on C3, C2 and C1.
b to C1b are output.

Further, the block output signal generation circuit 1
7 includes an adder 57 for cumulatively adding all the pieces of pixel information in the fourth area 204 centered on the interpolation pixel position shown in FIG. 2 and outputting it as a block output Xb. The pixel information at the position corresponding to the interpolation pixel is stored in the adder 57, and the output of the register and the outputs of the registers before and after the register are supplied via an amplifier which multiplies the coefficient shown in FIG. The cumulative addition is performed and output as a block output Xb.

FIG. 8 is a specific circuit diagram of the correlation detection circuit 22 shown in FIG. 1, and has a configuration corresponding to the second embodiment.

The first block difference calculation circuit 71 has one input terminal for receiving the block signals B1b, B2b, B3b, B4b, B5b, B6 from the block signal generation circuit 17.
b, B7b are supplied to the second block difference calculating circuit 7
2, the block signals C7b, C6b, C5b, C4b, C3 from the block signal generation circuit 17 are connected to one input terminal.
b, C2b and C1b are supplied.

The first and second block difference calculation circuits 7
1 and 72, respectively.
b are supplied, and their differences are calculated by the respective block difference calculation circuits 71 and 72, and the calculation result is converted to an absolute value conversion circuit 73.
Is supplied to the block difference combination circuit 74, and the difference value corresponding to the region centering on each pixel of the pixel pair is combined and output. The output of the block difference synthesizing circuit 74 is multiplied by an offset coefficient by an offset adding circuit 75 and then supplied to a minimum value detecting circuit 76, where the pixel pair having the smallest value is the pixel pair having the highest correlation. Is recognized.

In the case of the first embodiment of the present invention, for example, block signals B1b, B2b, B3b, B4b, B5b, B6b, B
7b and block signals C7b, C6b, C5b, C4
b, C3b, C2b, and C1b, and the difference is further converted into an absolute value by an absolute value conversion circuit 73, and the difference is directly used or an offset coefficient adding circuit 7
5 to the minimum value detecting circuit 76, where the pixel pair having the smallest value can be recognized as the pixel pair having the highest correlation.

Furthermore, although the embodiment of the present invention has been described as being realized by a hardware configuration such as a 1H memory, a register, an amplifier, an adder, a subtractor, etc., the present invention is not necessarily limited to a hardware configuration. Needless to say, the configuration can be realized by software processing. As described above, according to the interpolation signal generation device of the present invention, a point-symmetric pixel pair is extracted for a pixel position to be interpolated, and the correlation of the pixel information of the pixel pair is detected. Since a pixel pair having high correlation is specified and an interpolation signal is generated based on the pixel information of the specified pixel pair, even a shape having a sloping boundary can be smoothly displayed without any backlash. Things.

[0077]

As described above, according to the present invention,
Generates an interpolation signal by detecting the correlation of the pixel information of a pixel pair that is point-symmetric with respect to the pixel position to be interpolated, determining the interpolation pixel information based on the pixel information of the pixel pair having a high correlation. As a result, it is possible to perform interpolation without deteriorating image quality, including display of an inclined portion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an interpolation signal generation device according to the present invention.

FIG. 2 is a configuration diagram for explaining the operation of the circuit shown in FIG. 1;

FIG. 3 is a configuration diagram for explaining the operation of the circuit shown in FIG. 1;

FIG. 4 is a configuration diagram for explaining the operation of the circuit shown in FIG. 1;

FIG. 5 is a configuration diagram for explaining the operation of the circuit shown in FIG. 1;

FIG. 6 is a circuit diagram showing a specific example of a main part of the circuit shown in FIG. 1;

FIG. 7 is a circuit diagram showing a specific example of a main part of the circuit shown in FIG. 1;

FIG. 8 is a circuit diagram showing a specific example of another main part of the circuit shown in FIG. 1;

FIG. 9 is a block diagram showing a progressive scan conversion device.

FIG. 10 is a circuit diagram showing a conventional interpolation signal generation device.

FIG. 11 is a configuration diagram for explaining the operation of the circuit in FIG. 9;

[Explanation of symbols]

13, 14, 15, 16 1H memory 17 Block signal generating circuit 18, 19 Register group 20, 21 Selector 22 Adder 23 Amplifier 51a to 51i, 52a to 52i, 53a to 53i, 5
4a to 54i: Registers 55a to 55g, 56a to 56g, 57: Adders 71, 72: Block difference operation circuit 73: Absolute value conversion circuit 74: Block difference synthesis circuit 75: Offset addition circuit 76: Minimum value detection circuit

Claims (10)

[Claims] 1. An interpolation signal generating apparatus for generating an interpolation signal for interpolating between scanning lines of a television signal in which each scanning line includes a plurality of pixels each having pixel information, wherein a pixel position of the interpolation signal is determined. Extracting means for extracting a plurality of combinations of pixels having a point-symmetric relationship within a predetermined range of an adjacent scanning line in which the interpolation signal is to be interpolated; and extracting the pixel information of each of the extracted pixel pairs. A detection unit that calculates a difference and detects the correlation of each pixel pair from the difference value, based on the correlation determined by the detection unit, a generation unit that determines interpolation pixel information and generates an interpolation signal, An interpolated signal generation device comprising: 2. The image processing apparatus according to claim 1, wherein the extraction unit has a point-symmetrical relationship within a predetermined range of an adjacent scanning line in which the interpolation signal is to be interpolated with the pixel position of the interpolation signal as a center.
Extracting all combinations of pixels, wherein the detecting means obtains a difference between respective pixel information of the extracted pixel pairs, and determines a pixel pair having the highest correlation of each pixel pair from the difference value. The interpolation signal generation device according to claim 1, wherein 3. An interpolation signal generating apparatus for generating an interpolation signal for interpolating between scanning lines of a television signal in which each scanning line is composed of a plurality of pixels, wherein said interpolation signal generating device is configured to center on a pixel position of said interpolation signal. Extracting means for extracting a combination of two pixels having a symmetrical point relationship between adjacent scanning lines for which an interpolation signal is to be interpolated; and an extracting means which is located around this pixel with respect to each pixel of the extracted pixel pair. An adding unit that specifies first and second regions each including a plurality of pixels including pixels, and adds and accumulates pixel information in each of the regions; and an accumulative addition value in the first and second regions. Detecting means for obtaining a difference and detecting the correlation of each pixel pair from the difference value; and generating means for determining interpolation pixel information and generating an interpolation signal based on a detection result of the detection means. Characterized by Interpolation signal generator. 4. An interpolation signal generation device for generating an interpolation signal for interpolating between scanning lines of a television signal in which each scanning line is composed of a plurality of pixels, wherein the interpolation signal generation device is configured to center on a pixel position of the interpolation signal. Extracting means for extracting a combination of two pixels having a point-symmetrical relationship between adjacent scanning lines for which an interpolation signal is to be interpolated; and pixels existing around this pixel with reference to each pixel of the extracted pixel pair While identifying the first and second regions composed of a plurality of pixels including, and identifying the third region composed of a plurality of pixels of the scanning line adjacent to the interpolation pixel position as a center, Adding means for cumulatively adding each pixel information in the area; a difference between an added value of the first area and an added value of the third area; a difference between an added value of the second area and the third area. Each image based on Detecting means for detecting a correlation of pairs, based on said detection result of the detecting means, the interpolation signal generating apparatus characterized by comprising a generating means for generating an interpolation signal by specifying the interpolation pixel information. 5. The detecting means determines that a pixel pair detected as having a minimum difference serving as a reference for the correlation detection is a pixel pair having the highest correlation, and based on this pixel pair, The interpolation signal generation device according to claim 3, wherein a detection output is output to the generation unit such that an interpolation signal is generated. 6. The method according to claim 1, wherein each of the first and second regions includes a pixel serving as a center and pixels adjacent to the pixel in vertical, horizontal, and oblique directions. The interpolation signal generation device according to claim 3. 7. The interpolation signal generation method according to claim 4, wherein the third area is constituted by pixels adjacent to the interpolation pixel position in a vertical direction, a horizontal direction, and an oblique direction. apparatus. 8. A method according to claim 1, wherein pixel information of a plurality of pixels constituting said first and second regions is multiplied by predetermined coefficients having different values according to a distance from a center pixel. The interpolation signal generation device according to claim 6. 9. The method according to claim 7, wherein a plurality of pieces of pixel information forming the third area are multiplied by predetermined coefficients having different values according to a distance from the interpolation pixel. An interpolation signal generation device according to claim 1. 10. The detection circuit according to claim 1, wherein the detection circuit considers an offset amount according to a distance from the interpolation pixel position when detecting the correlation between the pixel pairs.
The interpolation signal generation device according to any one of items 3 and 4.