JP2002111006A - Voltage generation circuit, timepiece and electronic device including the same - Google Patents

Abstract

[PROBLEMS] To provide a voltage generation circuit for supplying an operation voltage almost to an operation lower limit voltage to an oscillation circuit that performs oscillation output to a device having an SOI structure having a hysteresis effect, and a timepiece and an electronic device including the same. provide. A constant voltage generating circuit for supplying an operating voltage to an oscillation circuit for supplying an oscillation output to a digital circuit including a frequency dividing circuit for performing a logical operation. The monitoring circuit 116 monitors the clock signal 138 output from the control circuit 140 and generates a control signal 140 according to the monitoring result. The constant voltage generation circuit 102 changes the constant voltage value supplied to the oscillation circuit 104 so as to gradually approach the circuit operation stop voltage V _STO in response to the control signal 140.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to SOI (Silicon).
The present invention relates to a voltage generation circuit including a field effect transistor having an On Insulator structure, a timepiece including the same, and an electronic device.

[0002]

2. Description of the Related Art Recent advances in integration technology and communication technology have led to the advancement of portability of various electronic devices such as mobile phones and information terminals, and semiconductor integrated circuits and ICs incorporated therein. (Semiconductor devices) are required to further reduce power consumption.

For example, in the case of watches (watches), those that do not use a primary battery in consideration of the environment have increased. Some are used as power supplies for built-in control ICs. In recent years, a device that mechanically moves a hand by a mainspring and, at the same time, generates power for a crystal oscillator and a built-in control IC to guarantee an accurate time on a quartz clock time has been put into practical use. In this case, the upper limits of the operating voltage and operating current allowed for the built-in control IC are, for example, 0.5 volt ([V]) and 50 nanoamperes ([nA]), respectively.

Generally, the above-mentioned control IC is a metal-oxide semiconductor (hereinafter referred to as MO).
Abbreviated as S. ) It is composed of a transistor. In order to reduce the power consumption of the control IC, a built-in MOS
Although it goes without saying that the parasitic capacitance of the transistor is reduced, since the power consumption is proportional to the square of the operating voltage (power supply voltage),
It is most effective to lower the operating voltage.

A device having an SOI (Silicon On Insulator) structure has a feature that a junction capacitance can be reduced and an operation voltage can be reduced by a low threshold voltage. It is attracting attention as a technology for realizing various required circuits.

In the case of an IC for a watch, a crystal oscillation circuit to which an external crystal oscillator is connected, and a circuit for dividing the oscillation output and controlling the timing, are provided by a MOS field effect transistor (SOI) having a SOI structure. FE
Abbreviated as T. ) Enables extremely low current consumption operation and low constant voltage operation.

However, if the voltage supplied to the oscillation circuit is low, the oscillation operation itself takes time. On the other hand, when the voltage supplied to the oscillation circuit is high, the oscillation starts earlier, but the power consumed for the oscillation operation itself increases more and more.

Therefore, normally, a high voltage is applied to the voltage supplied to the oscillation circuit when the power is turned on, oscillation starts to some extent, and when the oscillation output is detected, the voltage supplied to the oscillation circuit is defined as an operation lower limit voltage. Circuit operation stop voltage. As a result, it is possible to achieve both rapid start of oscillation and low power consumption.

In the case of a device having an SOI structure, by using a circuit constituted by a floating body type device in which a body portion is in a floating state,
Since the threshold value changes due to the floating effect of the substrate, which is the effect of the carriers accumulated in the body portion, operation at a low voltage becomes possible and power consumption can be further reduced.

However, when the supply voltage is rapidly changed for a floating body type device, it takes a long time to discharge the carriers accumulated in the body portion, and the D discharge time increases.
A hysteresis effect exists in the C characteristic.

Therefore, the watch I as described above
In C, when the oscillation output from the oscillation circuit is supplied to a circuit constituted by a device having a floating body type SOI structure, it is determined that the start of oscillation is detected through the circuit, and the voltage suddenly changes from a high voltage to a low voltage. When you switch,
Due to the hysteresis effect, the circuit may stop operating at the operating voltage at which the circuit originally operates. For this reason, it is difficult to set the low constant voltage value to be switched to just below the operation lower limit voltage, and the increase in power consumption has to be accepted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above technical problems, and an object of the present invention is to provide an oscillation circuit for oscillating and outputting an SOI structure device having a hysteresis effect. It is an object of the present invention to provide a voltage generating circuit capable of supplying an operating voltage just below the lower limit voltage, a timepiece including the same, and an electronic device.

[0013]

In order to solve the above problems, the present invention provides a first power supply line for supplying a first potential and a second power supply line for supplying a second potential lower than the first potential. And at least a part of a transistor as a component is a partially depleted type in which a body region and a source region are electrically connected to each other. A constant voltage generating circuit including a field effect transistor having an SOI structure; and a third for supplying a constant voltage generated by the constant voltage generating circuit with reference to one of the first and second potentials. A power line and the first
And a monitoring circuit electrically connected to the third power supply line, wherein at least a part of the transistor as a component is a monitoring circuit including a field-effect transistor having a partially depleted SOI structure in which a body region is in an electrically floating state; Including
The constant voltage generating circuit generates the constant voltage having a value corresponding to a given control signal, and the monitoring circuit uses a partially depleted SOI structure field effect transistor in which a body region is in an electrically floating state. The oscillation output of the oscillation circuit is monitored through a given operation circuit configured, and the control signal is generated as a result of the monitoring.

Here, the constant voltage generation circuit generates a constant voltage by using a potential difference between the first and second potentials supplied to the first and second power supply lines as an operating voltage. At least a part of the transistor constituting such a constant voltage generation circuit is formed of a partially depleted SOI field effect transistor in which a body region and a source region are electrically connected, and the entire circuit is formed. It is desirable to be constituted by such a source-tie type partially depleted SOI field effect transistor.

The operating circuit is at least partially operated at a constant voltage generated by the constant voltage generating circuit with reference to one of the first and second potentials, preferably at an extremely low voltage. Is composed of a partially-depleted SOI field-effect transistor in which the body region is electrically floating, and the entire circuit is formed by such a floating-body partially-depleted SOI field-effect transistor. It is desirable to be configured.

That is, according to the present invention, the constant voltage generating circuit connected to the first and second power supply lines to which a high voltage is likely to be applied includes a partially depleted body region and a source region. It is constituted by a field effect transistor having an SOI structure which is electrically connected, and a constant voltage generated by a constant voltage generation circuit is supplied to an operation circuit by first and third power supply lines. The constant voltage generation circuit
If an ultra-low constant voltage can be generated, a semiconductor integrated circuit capable of an ultra-low power consumption operation can be provided by configuring the operation circuit with a field effect transistor having an SOI structure with a body region in a floating state.

A digital circuit that performs a logical operation is suitable as the operation circuit. In general, when most parts of a semiconductor integrated circuit are digital circuit parts that perform a logical operation, as described above, by adopting a floating body type SOI structure field effect transistor capable of an ultra-low constant voltage operation, an effect can be obtained. Thus, ultra-low power consumption can be achieved.

According to the present invention, an oscillation output is monitored via an operating circuit such as a frequency dividing circuit constituted by a MOSFET of a floating body type SOI structure operating at a lower voltage than that having a hysteresis effect, and the monitoring thereof is performed. Based on the result, the constant voltage value generated by the constant voltage generating means can be changed step by step, so that the operating voltage does not suddenly change, and the MOS constituting the operating circuit is not changed.
It is possible to set a low constant voltage value that finally causes the oscillation circuit to operate just before the circuit operation stop voltage V _STO depending on the threshold value of the FET. Therefore, it is possible to achieve both rapid start of oscillation of the oscillation circuit and ultra-low power consumption.

Further, according to the present invention, the monitoring circuit monitors a lapse of time from the power-on, and gradually approaches the constant voltage value to a given first voltage value according to the lapse of time. It is characterized in that the control signal is generated in such a manner as to generate the control signal.

Thus, the constant voltage is changed stepwise so as to approach the first voltage value when a given oscillation condition is satisfied, without depending on the manufacturing conditions, so that it is difficult to control the threshold value. Circuit operation stop voltage V _STO
A very low voltage value can be supplied to the oscillation circuit, and power consumption can be reduced and oscillation can be started quickly.

Further, according to the present invention, the monitoring circuit counts pulses of the oscillation output of the oscillation circuit, and gradually brings the value of the constant voltage closer to a given first voltage value based on the count result. The control signal is generated such that the control signal is generated.

In this way, when the time for the stepwise change is known at the time of design, the monitoring circuit for monitoring the oscillation output gradually sets the constant voltage every time a given time elapses after the power is turned on. , The configuration can be simplified, and the circuit can be simplified and the cost can be reduced.

Further, according to the present invention, in the constant voltage generating circuit, one end is electrically connected to the second power supply line, and one end is electrically connected to the first power supply line. A connected second constant current source, a body region electrically connected to a source region electrically connected to the first power supply line, and a gate electrode and a drain region connected to the first constant current source. A first P-channel field-effect transistor having an SOI structure electrically connected to the other end; one electrically connected to a gate electrode of the first P-channel field-effect transistor; A differential pair comparator circuit electrically connected to the other end of the constant current source, a body region electrically connected to the source region, and a gate electrode and a drain region connected to the other end of the second constant current source. One or more electrically connected SOI structures 1 N-channel field effect transistor and a differential output of a gate electrode of the differential output of the differential pair comparator circuit which is electrically connected to the gate electrode of the first P-channel field effect transistor. A second power supply line, the body region and the source region being electrically connected to the second power supply line, and the drain region being electrically connected to a third power supply line for supplying the constant voltage.
A channel type field effect transistor, a drain region is electrically connected to a source region of each of the first N-channel type field effect transistors, a body region is electrically connected to each of the source regions, and a gate electrode is connected to the source region. And a second N-channel field effect transistor having one or more SOI structures, the source region being electrically connected to the third power supply line. .

Further, according to the present invention, in the constant voltage generating circuit, one end is electrically connected to the second power supply line, and one end is electrically connected to the first power supply line. A connected second constant current source, one or more SOIs having a body region electrically connected to the source region, and a gate electrode and a drain electrically connected to the other end of the first constant current source; A first P-channel field effect transistor having a structure, each body region is electrically connected to a source region electrically connected to the first power supply line, and each drain region is connected to the first P-type field effect transistor; One or more SOs connected to the source region of each channel-type field effect transistor and supplied with the given control signal to each gate electrode
A second P-channel field effect transistor having an I structure;
A differential pair comparator circuit, one of which is electrically connected to a gate electrode of the first P-channel field effect transistor and the other of which is electrically connected to the other end of the second constant current source; Are connected to the source region, the gate electrode and the drain region are electrically connected to the other end of the second constant current source, and the source region is electrically connected to the third power supply line for supplying the constant voltage. A first N-channel field-effect transistor having an SOI structure and a gate electrode connected to the gate electrode of the first P-channel field-effect transistor of the differential output of the differential pair comparator circuit; And a body region and a source region are electrically connected to the second power supply line, and a drain region is a source of the first N-channel field effect transistor. Second N which are electrically connected to the region
And a channel-type field-effect transistor.

As described above, a constant voltage generation circuit capable of changing a constant voltage value to be supplied stepwise can be constituted by a body-tie type MOSFET having an SOI structure, thereby simplifying the circuit and generating the constant voltage. Accurate control of a low constant voltage value becomes possible.

Further, according to the present invention, in the constant voltage generating circuit, one end is electrically connected to the second power supply line, and one end is electrically connected to the first power supply line. A connected second constant current source, a body region electrically connected to a source electrically connected to the first power supply line, and a gate electrode and a drain region other than the first constant current source. A first P-channel field-effect transistor having an SOI structure electrically connected to one end thereof; one being electrically connected to a gate electrode of the first P-channel field-effect transistor; A differential pair comparator circuit electrically connected to the other end of the constant current source; a body region electrically connected to the source region; and a gate electrode and a drain region electrically connected to the other end of the second constant current source. And the source region supplies the constant voltage. And a first N-channel field effect transistor having one or more SOI structures electrically connected to the third power supply line for supplying the constant current value of the first constant current source. By changing the value, the value of the constant voltage is made to gradually approach a given first voltage value.

According to the present invention, the constant current value of the second constant current source is changed so that the value of the constant voltage gradually approaches a given first voltage value. It is characterized by being.

As described above, a constant-voltage generator capable of changing a constant voltage value to be supplied in a stepwise manner by changing the constant current value generated by the constant current source while being configured as a body-tie type MOSFET having an SOI structure. Since the circuit can be configured, it is possible to simplify the circuit and accurately control the generated low constant voltage value.

Further, the invention is characterized in that the oscillation circuit is a crystal oscillator.

According to the present invention, since the constant voltage supplied to the crystal oscillator for obtaining the oscillation output of the crystal oscillator is changed stepwise, a stable oscillation output independent of the operating voltage and frequency can be obtained. , More quickly and with low power consumption.

According to the present invention, there is provided a timepiece including any one of the above-described voltage generating circuits.

Thus, it is possible to provide a timepiece capable of performing the above-described rapid oscillation start and ultra-low power consumption operation.

According to the present invention, there is provided an electronic apparatus including any one of the above-described voltage generating circuits.

Thus, it is possible to provide an electronic device which can extend the life of the battery by the above-described rapid start of oscillation and ultra-low power consumption operation.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

1. Watch IC The voltage generation circuit of this embodiment is a MOSFE having an SOI structure.
T is included in the watch IC. The watch IC monitors the movement of the hands of the clock body and controls the timing of the frequency-divided signal of the oscillation output of the oscillation circuit so that the clock is supplied to the clock body at an appropriate timing according to the monitoring result. The voltage generation circuit according to the present embodiment controls the operation voltage supplied to the oscillation circuit.

1.1 Configuration FIG. 1 shows an example of the configuration of a watch IC composed of a MOSFET having an SOI structure including the voltage generation circuit of the present embodiment.

The watch IC includes an analog circuit unit 100 that requires a linear operation and a digital circuit unit 110 that performs a logical operation.

The analog circuit section 100 includes a constant voltage generation circuit (Voltage Regulator) 102 and an oscillation circuit (Oscillato).
r) 104, and a detection circuit (Detector) 106.

The digital circuit section 110 includes a frequency dividing circuit (Di
vider) 112, a control circuit (Controller) 114, and a monitoring circuit 116.

The analog circuit section 100 includes a first power supply line V
_DD and the second power supply line V _SS are connected.

Constant voltage generation circuit 1 of analog circuit section 100
02, the first power supply line V_DDAnd the second power line V_SSIs connected
Have been. This constant voltage generation circuit 102 is connected to a first power supply
Line V _DDAnd the second power line V_SSOperate the potential difference between
Source) voltage as the first power supply line V_DDWith reference to the potential of
Able to generate a given low constant voltage
You. This low constant voltage is applied to the first power supply line V_DDAnd power line 120
Thus, the power is supplied to each part of the circuit.

The oscillation circuit 104 and the detection circuit 106
The power supply line V _DD and the power supply line 120 are connected, and the potential difference between the two power supply lines operates as an operation (power supply) voltage.

The frequency dividing circuit 112 of the digital circuit 110,
The control circuit 114 and the monitoring circuit 116 are connected to the first power supply line V _DD
And the power supply line 120, and operates using the potential difference between the two power supply lines as an operation (power supply) voltage.

In such a watch IC, assuming that the first power supply line V _DD is at the ground level, the constant voltage generation circuit 102 receives an external signal from the outside of the IC via the second power supply line V _SS. A voltage is supplied.

1.1.1 Analog Circuit Unit The analog circuit unit 100 according to the present embodiment includes a second power supply line V
Constant voltage generation circuit 1 to which external power supply voltage is supplied via _SS
02 and a part of the MOSFET of the detection circuit 106 which receives a signal from an external circuit to which the ultra-low constant voltage is not supplied by the constant voltage generation circuit 102, respectively, is provided with a body-tie type partially depleted (hereinafter referred to as PD). (It is abbreviated.) Type MOSFET of SOI structure is adopted.
This makes it possible to suppress the substrate floating effect in the body region and obtain the same level of analog characteristics as the bulk type.

Further, in this embodiment, the oscillation inverters of the oscillation circuit 104 are also body-tie PD type S
It is configured by a MOSFET having an OI structure. This is because, especially in the case of an oscillation circuit, analog characteristics having no frequency dependency or voltage dependency are required. In other words, the oscillation circuit 104 employs a body-type PD-type SOI structure MOSFET and operates at an extremely low constant voltage, whereby low power consumption operation and quick start of oscillation can be achieved.

Further, in the detection circuit 106, except for the interface portion of the external signal to which the ultra-low constant voltage is not supplied by the constant voltage generation circuit 102, a floating body type is used, thereby further reducing the power consumption operation. Can be planned.

Such an analog circuit 100 further supplies a constant current and operates at a constant current, thereby suppressing the operating current and reducing the operating current of the MOSFET by 1n.
It is operated in a sub-threshold region of about A. This ensures low current consumption operation and constant voltage operation.

In particular, the oscillating inverter of the oscillating circuit 104 has a P-channel type and an N-channel type SOI structure MOI.
By selectively doping impurities into the SFET and controlling the SFET to be lower than the threshold of other MOSFETs in the analog circuit section 100, a low-constant voltage operation of the oscillation circuit 104 can be ensured.

1.1.2 Digital Circuit Unit The digital circuit unit 110 is a logic circuit that performs a logical operation, and usually has the largest number of elements and occupies most of the circuits in a watch IC.

In the present embodiment, the digital circuit section 110 such as the frequency dividing circuit 112, the control circuit 114, and the monitoring circuit 116 is constituted by a floating body type MOSFET of PD SOI structure.

By adopting the floating body type, it is possible to realize a MOSFET having a minimum size according to design rules, and to ideally reduce the junction capacitance.

Also, a floating body type PD type S
By adopting the MOSFET having the OI structure, the threshold value in the actual operation (AC operation) can be further reduced from the threshold value in the DC operation by using the substrate floating effect of the body region positively. Low-voltage driving of the digital circuit unit 110 occupying a large part of the IC for use can be realized. Thereby, ultra-low power consumption can be effectively achieved. Therefore, the digital circuit 110 is provided with a floating body type P by the constant voltage generation circuit 102.
An ultra-low constant voltage necessary for positively utilizing the above-mentioned substrate floating effect in a D-type SOI MOSFET is supplied.

1.2 Outline of Circuit The constant voltage generation circuit 102 generates a given low constant voltage and supplies it to each part of the circuit.

The oscillation circuit 104 has an external 32 KH
An oscillation output of 32 KHz is taken out from the crystal unit 130 of z and supplied to the digital circuit unit 110.

In the digital circuit section 110, the frequency dividing circuit 1
The frequency of the oscillation output from the oscillation circuit 104 is sequentially divided by 12 to generate a frequency-divided signal of, for example, 0.1 Hz.

On the other hand, the detection circuit 106 detects various notification signals which are input from the operation state notification signal terminal 134 and indicate the operation state of the clock (not shown), and the detection result signal 13
6 is output to the control circuit 114 of the digital circuit 110.

The control circuit 114 controls the frequency dividing circuit 11 according to the result indicated by the detection result signal 136 from the detection circuit 106.
2 controls the output timing and the like of the frequency-divided signal 132 output from the control signal 2. Thus, for example, the detection circuit 106 monitors the movement of the hands of the clock body (not shown) based on various notification signals from the operation state notification signal terminal 134, and the control circuit 11
4 generates and supplies a clock signal 138 with accurate timing, and can control the hand movement of a clock body (not shown).

The monitoring circuit 116 monitors the clock signal 138 controlled and output by the control circuit 114 to detect whether or not a given oscillation condition is satisfied from the frequency of the oscillation output and the like. Is supplied to the constant voltage generation circuit 102.

The control signal 140 has a predetermined time from the lapse of time from when the oscillation output of the clock signal 138 satisfies a given oscillation condition or the result of counting the pulses of the clock signal 138 after power-on. The constant voltage value supplied to the power supply line 120 by the constant voltage generating circuit 102 is generated so as to be controlled so as to approach a target voltage value defined as a circuit operation stop voltage.

The constant voltage generation circuit 102 outputs the control signal 1
40 to generate a constant voltage value indicated by the power line 12.
Supply 0.

That is, the voltage generating circuit of the present embodiment monitors the clock signal output from the control circuit 114 by the monitoring circuit 116 and controls the constant voltage generating circuit 102 in accordance with the monitoring result. The supplied constant voltage value can be controlled.

1.3 Voltage Generating Circuit of the Present Embodiment The voltage generating circuit of the present embodiment includes a monitoring circuit 116 that generates a control signal 140 based on a monitoring result of a clock signal whose output is controlled by the control circuit 114, Control signal 14
And a constant voltage generating circuit 102 for generating a constant voltage value corresponding to 0.

FIG. 2 shows a constant voltage generating circuit 10 according to this embodiment.
2 shows an example of a main part of the second configuration.

The P-channel and N-channel MOSFETs of the PD SOI structure included in the constant voltage generation circuit 102 of this embodiment are all of a body tie type, and the body region is connected to the source region.

The constant voltage generating circuit 102 includes a differential pair comparator circuit 200.

This differential pair comparator circuit 200
Constant current source 202, P-channel type MOSFET 204, 2
06, N-channel MOSFETs 208 and 21 on the load side
Contains 0.

The differential pair comparator circuit 200 has a constant current source 20 having one end grounded (connected to the first power supply line V _DD ).
P-channel type MOSFETs 204 and 206
Source terminals are connected.

P-channel MOSFETs 204 and 206
Are connected to the load side N-channel type MO, respectively.
It is connected to the drain terminals of the SFETs 208 and 210.

Load-side N-channel MOSFET 20
Gate terminals 8 and 210 are connected to each other, and a gate terminal and a drain terminal of the N-channel MOSFET 210 are connected. Thereby, a mirror circuit is configured on the load side.

The P-channel MOSFET 212
The source terminal is grounded (first power line V _DDConnected to
The port terminal and the drain terminal are connected. This game
The gate terminal and the drain terminal are connected to the node P. No
The node P is a gate terminal of the P-channel MOSFET 204.
And a second power supply line V at one end._SSConstant current source 2 connected to
14 is connected to the other end.

Further, the other end of the constant current source 216 whose one end is grounded (connected to the first power supply line V _DD ) is connected to the node P ′. The node P ′ has a P-channel type MOSF
ET206 gate terminal and multiple N-channel MOS
The drain terminals of the FETs 218 ₁ , 218 ₂ , 218 ₃ ,... Are connected.

N-channel MOSFETs 218 ₁ , 21
8 _2, 218 _3, gate terminal and the drain terminal of the ... are connected to each other, each of the source terminal, N-channel type MOSFET224 ₁ control signal from the monitoring circuit 108 to the gate electrode is connected, 224 ₂ , 22
4 _3, and is connected to the respective drain terminals of ....

The N-channel MOSFET 22
4 _1, 224 _2, 224 _3, the source terminal of ... is connected to the node Q. This node Q has an output terminal 220 for outputting an ultra-low constant voltage value with reference to a ground level (the potential level of the first power supply line), and an N-channel MOSF.
The drain terminal of ET222 is connected.

The gate terminal of the N-channel MOSFET 222 is connected to the drain terminal of the P-channel MOSFET 204 and the drain terminal of the N-channel MOSFET 208. The source terminal of the N-channel type MOSFET222 is connected to the second power supply line V _SS.

FIG. 3 shows an example of the configuration of the monitoring circuit 116 of this embodiment.

The P included in the monitoring circuit 116 of this embodiment
MO of channel type and N channel type PD type SOI structure
The SFETs are all floating body type,
The power supply line _V.sub.DD and the power supply line 120 to which a low constant voltage is supplied by the constant voltage generation circuit 102 operate as an operating voltage.

The monitoring circuit 116 of this embodiment includes a monitor circuit 250, a timer circuit 252, and a decoder circuit 254.

The monitor circuit 250 monitors the clock signal 138 controlled and output by the control circuit 114, and can detect whether or not a given oscillation condition is satisfied. For example, the clock signal 138
When the oscillation condition is set to be equal to or higher than a certain frequency, the monitor circuit 250 monitors the clock signal 138 and outputs the oscillation condition detection signal 26 indicating whether or not the oscillation condition is satisfied.
0 is output to the timer circuit 252.

The timer circuit 252 outputs the clock signal 13 based on the oscillation condition detection signal 260 from the monitor circuit 250.
8 satisfies the given oscillation conditions,
A timeout signal 262 is output to the decoder circuit 254 every time the N-th times T _{1 to} T _N elapse.

The decoder circuit 254 decodes the time-out signal 262 and generates a control signal 140 consisting of a plurality of bits corresponding to the time lapse indicated by the time-out signal 262.

The control signal 140 thus generated
Is an N-channel type MO shown in FIG. 2 for each corresponding bit.
Are supplied to the respective gate electrodes of the SFETs 224 ₁ , 224 ₂ , 224 ₃ ,.

FIGS. 4A and 4B show an example of a control result of the constant voltage value generated by the constant voltage generating circuit 102 controlled by the control signal 140. FIG.

Here, the vertical axis represents the constant voltage value | V _IN | supplied to the operating circuit composed of the MOSFET of the floating body type PD SOI structure as the operating voltage by the constant voltage generating circuit 102, and | V _IN | Is the time since power-on.

The lower limit voltage at which the operation circuit operates is defined as
Circuit operation stop voltage specified by V _STOAnd This time
Road operation stop voltage V_STOIs the MOSF that constitutes the operation circuit
Depends on the ET threshold.

Further, when a power supply is turned on, a given high voltage value supplied in order to make the oscillation of the oscillation circuit
₁ , V for ultimately low power consumption operation
A constant voltage _{value STO} is barely set to V _2.

Conventionally, as shown in FIG. 4A, when a high constant voltage value V ₁ is supplied in order to make the oscillation start as soon as possible when the power is turned on, after a predetermined time elapses,
It has been switched to a low constant voltage value V _2.

However, as described above, the floating body type SOI device has a threshold value that changes due to the substrate floating effect, which is the effect of the carriers accumulated in the body portion. Although power consumption can be reduced, when the operating voltage is rapidly switched due to the hysteresis effect of the body portion in which the carriers are accumulated, the circuit may stop operating at the operating voltage at which the circuit originally operates.

This means that the low constant voltage value V ₂ cannot be set just before the circuit stop voltage value V _STO , resulting in the difference between the low constant voltage value V ₂ and the circuit stop voltage value V _STO. Since V _M must be increased, the operation is performed at a higher voltage although the operation is originally performed at a slightly lower voltage, so that the power consumption is correspondingly increased.

On the other hand, in the present embodiment, FIG.
, The constant voltage value supplied to the floating body type SOI device gradually approaches the circuit stop voltage value V _STO at given times T ₁ , T ₂ ,..., T _N. As a result, the influence of the hysteresis effect due to the rapid voltage change as described above can be eliminated. Thus, barely circuit stop voltage V _STO, it is possible to set a low constant voltage value V _2, it is possible to reduce the difference V _M 'of the low constant voltage value V ₂ and the circuit stops the voltage value V _STO As a result, it is possible to achieve both the quick start of oscillation and the reduction in power consumption as compared with the related art.

As described above, the constant voltage generating circuit 102 according to the present embodiment capable of switching the constant voltage value stepwise.
Is set such that the potential of the node P, which is the potential of the drain terminal of the P-channel MOSFET 212, flows through the constant current supplied by the constant current source 214. The potential of this node P is determined by the differential pair comparator circuit 2 described above.
P-channel MOSFET which is one input terminal of 00
The signal is input to the gate terminal 204.

In the comparator circuit 200 of the differential pair, the P-channel MOSFETs 204 and 206 operate so that the operating current is defined by the mirror circuit on the load side.

The N-channel type MOSFET 222 is an output control transistor. N-channel type MOSFET
, 218 ₁ , 218 ₂ , 218 ₃ ,... Are bias generating MOSFETs that generate a given bias between the drain and the source by flowing a current between the drain and the source. N-channel type MOSFETs 224 ₁ , 224 ₂ ,
224 _3, ... it is turned on the current flowing between the drain and the source, a switch to turn off.

An output control N-channel MOSFET 222 and an N-channel MOSFET 21 are connected to a node P ′.
8 ₁ , 218 ₂ , 218 ₃ ,..., And the potential at this node P ′ is a P-channel MOSFE which is the other input terminal of the differential pair comparator.
Negative feedback is provided to the gate terminal of T206. With this configuration, the nodes P and P ′ are controlled to the same potential by the operations of the differential pair P-channel MOSFETs 204 and 206 and the output control N-channel MOSFET 222.

By doing so, the output terminal 2
Constant voltage V _Q supplied from 20, as a ground-level reference potential (first potential level of power supply line), and the potential difference V _P generated in the P-channel type MOSFET 212, the node P
'And the potential difference between the node Q and the potential difference.

Here, each bit of the control signal 140 generated by the monitor circuit 116 is an N-channel type MOSF.
ET224 ₁ , 224 ₂ , 224 ₃ ,...

Thus, between the node P 'and the node Q
Of the N-channel MOSFET connected to the
Width) / L (gate length) can be changed.
N-channel type M connected between node P 'and node Q
OSFET218₁218_Two218_Three, ..., N
Channel type MOSFET 224₁224_Two224_Three,
.. Arbitrarily cut off by the node P ′
Of the MOSFET connected between the
Can be changed. That is, the output terminal 220
Constant voltage V supplied from_QIs the ground level (the first power supply
Line potential level) as a reference potential, a P-channel MO
Potential difference V generated in SFET 212_PAnd the node P '
Developed into N-channel MOSFET connected to node Q
Generated voltage V _NIs output.

MOSFETs 218 ₁ , 218 ₂ , 21
8 ₃ ,... Are formed so as to be different from each other, and one or a plurality of connections are selected to control a bias value between the node P ′ and the node Q. Is also good.

As described above, by changing the N-channel MOSFET to be cut off or connected by the control signal 140, the constant voltage value can be changed stepwise.

Incidentally, since the circuit operation stop voltage V _STO depends on the threshold value of the MOSFET constituting the circuit to which the low voltage is supplied, the constant voltage generating circuit 102 in this embodiment adjusts the constant current value. Thus, the sum of the value of Vds (drain-source voltage) of the P-channel MOSFET 212 connected in saturation and the value of Vds of the N-channel MOSFET 218 connected in saturation is output as a constant voltage.

Therefore, the power supplied from the output terminal 220 is
Constant voltage V_QAre P-channel MOSFET 212, N
The threshold V of each channel type MOSFET 218_thN,
｜ V_{t hP}The value depends on the sum of |.

As a result, the temperature gradient between the low constant voltage generated by the constant voltage generating circuit 102 and the circuit operation stop voltage V _STO of the circuit to which the low constant voltage is supplied becomes equal,
By constantly supplying a constant voltage slightly higher than the circuit operation stop voltage V _STO without setting uselessly high constant voltage in the temperature range where operation is to be guaranteed, power consumption can be effectively reduced. it can.

2. 2. Another Example of Configuration 2.1 Another Example of Configuration of Constant Voltage Generating Circuit The voltage generating circuit according to the present embodiment includes a Tr connected to one of the differential pair of comparator circuits as shown in FIG.
(Transistor) N-channel type MOSF with different sizes
Although it has been described that the constant voltage value supplied to the oscillation circuit is changed stepwise by selecting the ET stepwise, the present invention is not limited to this.

FIG. 5 shows another example of a main part of the configuration of the constant voltage generating circuit of the present embodiment.

P-channel type and N-channel type PD-type SOI MOSFETs included in this constant voltage generating circuit
Also, like the constant voltage generating circuit 102 shown in FIG. 2, all are of a body tie type, and the body region is connected to the source region.

This constant voltage generation circuit 280 has basically the same configuration as constant voltage generation circuit 102 shown in FIG.

[0108] However constant voltage generating circuit 280, N-channel type MOSFET218 ₁ during the constant voltage generating circuit 102 shown in FIG. 2 is a node P'and node Q, 218 _2, 21
8 ₃ ,... 224 ₁ , 224 ₂ , 224 ₃ ,.
Only 8 are connected. Further, the constant voltage generation circuit 280
Is, P-channel type between the constant voltage generation circuit 102 shown in FIG. 2 is a first power supply line V _DD and the node P MOSFET 21
2 is connected, the constant voltage generating circuit 280 connects the P-channel type MO between the first power supply line V _DD and the node P.
The SFETs 212 ₁ , 212 ₂ , 282 ₁ , and 282 ₂ are connected.

P-channel MOSFETs 212 ₁ , 21
2 _second source terminal respectively, P-channel source terminal connected to the first power supply line V _DD MOSFET 28
2 _1, 282 ₂ are connected to respective drain terminals. Each bit of the control signal 140 generated by the monitoring circuit 116 is connected to the gate electrodes of the P-channel MOSFETs 282 ₁ and 282 ₂ .

P-channel MOSFETs 212 ₁ , 21
₂ 2, 212 _3, MOSFET for ... bias generator
Then, a given bias is generated between the drain and the source by flowing a current between the drain and the source. P-channel type _{MOSFET282 1, 282 2, 282 3} , ··
Is a switch for turning on and off the current flowing between the drain and the source.

At the node P ', a potential controlled by the output control N-channel MOSFET 222 and the N-channel MOSFET 218 is generated. The potential at the node P' is the other input terminal of the differential pair comparator. Is negatively fed back to the gate terminal of the P-channel MOSFET 206. With this configuration, a differential pair P-channel MOSFET
204, 206 and N-channel MOSFET for output control
By the operation of 222, the nodes P and P 'are controlled to the same potential.

Here, the number of P-channel MOSFETs connected between the node P and the first power supply line V _DD is two, but three or more P-channel MOSFETs may be similarly connected.

With this configuration, it is possible to change W (gate width) / L (gate length) of the P-channel MOSFET connected between the first power supply line V _DD and the node P. Therefore, a P-channel MOSFET 212 ₁ connected between the first power supply line V _DD and the node P,
212 ₂ is connected to P-channel MOSFETs 282 ₁ , 282
₂ and the first power supply line V
The Tr size of the MOSFET connected between the _DD and the node P can be changed. That is, the output terminal 22
The constant voltage VQ supplied from the first power supply line _VQ is set to a ground level (the potential level of the first power supply line) as a reference potential.
And the potential difference between the DD and the node P, the sum of the voltage V _N generated in the N-channel MOSFET connected to the node P'and the node Q is output.

The MOSFETs 212 ₁ and 212 ₂ may be formed with different W / Ls, and one or a plurality of the connections may be selected to control the bias value of the node P.

As described above, by changing the P-channel MOSFET to be cut off or connected by the control signal 140, the constant voltage value can be changed stepwise.

Further, the constant voltage generation circuit constituting the voltage generation circuit according to the present embodiment is composed of an N connected to one of the differential pair comparator circuits as shown in FIGS.
The present invention is not limited to the method in which the constant voltage value supplied to the oscillation circuit is changed stepwise by changing the Tr size of the channel type MOSFET and the P-channel type MOSFET stepwise.

In addition, the first power supply line VDD and the node P
Are provided only with the P-channel MOSFET 212 without connecting a plurality of P-channel MOSFETs, and an N-channel MOSFET is also provided between the node P ′ and the node Q.
N-channel MOSFET without connecting multiple SFETs
218 is provided, for example, by changing the constant current value of the constant current source 214 that supplies the bias current of the P-channel MOSFET connected between the first power supply line VDD and the node P in a stepwise manner. a constant voltage value V _Q output from the terminal 220 may be changed stepwise.

The output from the output terminal 220 can also be changed by changing the constant current value of the constant current source 216 for supplying the bias current of the N-channel MOSFET connected between the node P 'and the node Q stepwise. The constant voltage value V _Q can be changed stepwise.

For example, the constant current value can be easily changed by providing a plurality of constant current sources that generate different constant current values from each other and selectively switching the constant current value by a control signal.

2.2 Another Example of Configuration of Monitoring Circuit The voltage generating circuit according to the present embodiment has a MOS transistor in a stepwise manner when the oscillation output of the oscillation circuit satisfies a given oscillation condition.
Although the description has been made assuming that the constant voltage value supplied to the oscillation circuit is changed stepwise by changing the Tr size of the FET stepwise, the invention is not limited to this.

FIG. 6 shows another example of the configuration of the monitoring circuit of this embodiment.

P-channel type and N-channel type MOSFETs of PD SOI structure included in monitoring circuit 290
Are of a floating body type, and operate using a potential difference between a first power supply line V _DD and a power supply line 120 to which a low constant voltage is supplied by a constant voltage generation circuit 102 as an operation voltage.

The monitoring circuit 290 includes a counter circuit 292,
Decoder circuit 294 is included.

The counter circuit 292 counts pulses of the clock signal 138 controlled and output by the control circuit 114. When the count reaches a given count, a count-up signal 29 corresponding to the count is sent.
6 to the decoder circuit 294.

For example, when the clock signal 138 reaches the first count number C ₁ , a corresponding count-up signal is output to the decoder circuit 294, and the clock signal 138 further outputs the second count number C 1. When the count reaches ₂ , a count-up signal corresponding to the count is output to the decoder circuit 294.

The decoder circuit 294 decodes the count-up signal 296 and generates a control signal 140 consisting of a plurality of bits corresponding to the count number indicated thereby.

The control signal 140 thus generated
Is an N-channel type MO shown in FIG. 2 for each corresponding bit.
SFETs 224 ₁ , 224 ₂ , 224 ₃ ,... Or P-channel MOSFETs 282 ₁ , 282 ₂ shown in FIG.
Are supplied to the respective gate electrodes.

When the threshold value of each MOSFET can be controlled with high accuracy and the oscillation start time can be predicted to some extent, the oscillation output is not monitored at all, and the oscillation output is not monitored at all and a step-by-step operation is performed every given time after power-on. The control signal 140 may be generated so as to change the constant voltage value.

3. Semiconductor Device The voltage generation circuit of the present embodiment as described above is mounted on a silicon chip or the like to form a semiconductor device.
An unprecedented ultra-low power consumption operation can be performed. However, in a broad sense, the semiconductor integrated circuit of the present embodiment is included in a semiconductor device.

FIG. 7 shows an example of the configuration of a semiconductor device incorporating the voltage generating circuit of the present embodiment.

The power supply / clock generation circuit 31 including the voltage generation circuit of the present embodiment is
0, a CPU 312, a RAM 314, a DMA 316, a timer circuit 318, a silicon chip on which a serial interface circuit 320 and the like are mounted, and a plurality of external terminals. CPU 312, RAM 314, DMA
The 316, the timer circuit 318, and the serial interface circuit 320 are connected to each other by a bus 322.

Each circuit in the silicon chip is inputted from outside the semiconductor device through these various external terminals, and an operation signal of the circuit is outputted outside the semiconductor device through these various external terminals.

In the silicon chip mounted on the semiconductor device 300 of this embodiment, a part of the power supply / clock generation circuit 310 is constituted by a MOSFET body tie having a PD type SOI structure, and the other CPU 312 and RAM
At least a part of the 314, the DMA 316, the timer circuit 318, and the serial interface circuit 320 includes a circuit composed of a floating body type PD type SOI MOSFET.

Power supply / clock generation circuit 310 includes a constant voltage generation circuit 330 and a clock signal generation circuit 332,
The constant voltage generation circuit 330 includes first and second power supply lines 338 and 340 connected to the first and second power supply lines via power supply terminals 334 and 336, and the clock signal generation circuit 332 includes a first power supply line 338. Constant voltage supply wiring 34 to which the constant voltage generated by the constant voltage generating circuit 330 is supplied.
2 respectively.

The clock signal generation circuit 332 is connected to the crystal oscillator 34 via the crystal oscillator connection terminals 344 and 346.
8 is externally divided to divide an oscillation signal of a given frequency,
The monitoring circuit shown in FIG. 3 or FIG. 6 is provided to output the clock signal 350, monitor the clock signal 350, and generate the control signal 35 generated based on the monitoring result.
2 is output to the constant voltage generation circuit 330.

The constant voltage generation circuit 330 outputs the control signal 3
52, the constant voltage value is gradually changed to the circuit operation stop voltage V
_It is changed so as to approach _STO, and is supplied to an oscillation circuit portion for extracting the oscillation output of the crystal unit 348 at least in the clock signal generation circuit 332.

A circuit constituted by a MOSFET having a floating body type PD type SOI structure has a first power supply line 338 connected to a low constant voltage supply wiring 342, and a clock signal 350 generated by a clock signal generation circuit 332. Is supplied.

As described above, the floating circuit type PD is provided in the logic circuit portion which occupies most of the circuit as described above.
In addition to adopting a MOSFET of the type SOI structure, a low constant voltage for reducing the influence of the substrate floating effect is supplied to these logic circuit portions. Further, as described above, the constant voltage generating circuit 330 for generating the low constant voltage and the clock signal generating circuit for obtaining the oscillation output are composed of the PD type SO.
It is configured as a body tie type MOSFET of I structure. Thus, it is possible to provide a semiconductor device which can operate at an extremely low power consumption without manufacturing cost.

Also, a floating body type SOI having a hysteresis effect in the frequency dividing circuit portion of the clock signal 350 and the like.
Even if the device is adopted, the circuit operation stop voltage V
It is possible to approach _STO , and it is possible to achieve faster oscillation start and ultra-low power consumption.

Since the frequency dividing circuit portion of the oscillation output of the clock signal generating circuit 332 performs a logical operation, a further reduction in power consumption can be achieved by employing a floating body type PD SOI structure MOSFET. it can.

4. Electronic Apparatus By applying the above-described semiconductor integrated circuit and semiconductor device to an electronic apparatus, power consumption of the electronic apparatus can be reduced. This is applicable not only to the watch of the present embodiment but also to various portable information terminal devices.

FIGS. 8A and 8B show an example of a block diagram of the electronic apparatus of the present embodiment.

As shown in FIG. 8A, the electronic device 400 includes a power supply / clock generation circuit 410 for generating an ultra-low constant voltage and a clock signal corresponding thereto, and uses the ultra-low constant voltage as an operating voltage. An operation circuit 420 that performs a given operation according to a clock signal.

The power supply / clock generation circuit 410 includes a constant voltage generation circuit 412 and a clock signal generation circuit 414.

The constant voltage generation circuit generates an ultra-low constant voltage from the potential difference between the first power supply line V _DD and the second power supply line V _SS, and is constituted by a body-tie type MOSFET having a PD type SOI structure. Have been.

The clock signal generation circuit 414 operates using the potential difference between the first power supply line V _DD and the ultra-low constant voltage generated by the constant voltage generation circuit 412 as the operation voltage, and operates the externally mounted crystal oscillator. An oscillation output 416 is taken out and divided to generate a clock signal 418. It is preferable that the portion for extracting the oscillation output of the clock signal generation circuit 414 is constituted by a body-tie type MOSFET having a PD-type SOI structure, and the dividing portion of the floating body type is constituted by a MOSFET having a PD-type SOI structure.

The clock signal generation circuit 414 includes the monitoring circuit shown in FIG. 3 or FIG. 6, monitors the clock signal 418, and outputs the control signal 419 generated based on the monitoring result to the constant voltage generation circuit 412. To be output.

The constant voltage generation circuit 412 outputs the control signal
19, the constant voltage value is gradually changed to the circuit operation stop voltage V.
_It is changed so as to approach _STO, and is supplied to at least an oscillation circuit portion for extracting the oscillation output of the crystal oscillator 416 in the clock signal generation circuit 414.

The operation circuit 420 outputs the clock signal 41
8 to perform a given logical operation, and
The MOSFET is configured as a floating body type MOSFET.

As shown in FIG. 8B, the operation circuit 420
Includes a CPU (or a semiconductor integrated circuit (semiconductor device) of the present embodiment) 422, an input unit 424, a memory 426, an image generation unit 428, a sound output unit 430, and a communication unit 432.

It is desirable that each part performing these logical operations is constituted by a MOSFET having a floating body type PD type SOI structure.

Here, the input section 424 is for inputting various data. The CPU (or the semiconductor integrated circuit (semiconductor device) of this embodiment) 422 performs various processes based on the data input through the input unit 424. The memory 426 serves as a work area for the CPU (or the semiconductor integrated circuit (semiconductor device) of the present embodiment) 420 or the like. The image output unit 428 outputs various images (characters, icons, graphics, and the like) displayed by the electronic device.
It can be realized by hardware such as a CD and a CRT. The sound output unit 430 is for outputting various sounds (voices, game sounds, and the like) output from the electronic device 400, and its function can be realized by hardware such as a speaker.

FIG. 9A shows an example of an external view of a mobile phone 950 which is one of the electronic devices. This mobile phone 950
Includes a dial button 952 functioning as an input unit, an LCD 954 functioning as an image output unit to display a telephone number, a name, an icon, and the like, and a speaker 956 functioning as a sound output unit and outputting sound.

FIG. 9B shows an example of an external view of a portable game apparatus 960 which is one of the electronic devices. The portable game device 960 includes an operation button 9 functioning as an input unit.
62, an arrow key 964, an LCD 966 that functions as an image output unit and displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sounds.

[0155] FIG. 9C shows an example of an external view of a personal computer 970 which is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that functions as an image output unit and displays characters, numbers, graphics, and the like, and a sound output unit 976.

By incorporating the semiconductor integrated circuit of the present embodiment or the semiconductor device provided with the same into the electronic equipment shown in FIGS. 9A to 9C, ultra-low power consumption of the electronic equipment can be achieved. it can.

The electronic apparatus to which the present embodiment can be applied includes a portable information terminal, a pager, an electronic desk calculator, and a touch panel in addition to those shown in FIGS. 9A, 9B, and 9C. Various electronic devices such as a device, a projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, and a printer can be considered.

Note that the present invention is not limited to the present embodiment.
Various modifications can be made within the scope of the present invention.

Although the monitoring circuit in the present embodiment has been described as being constituted by a MOSFET having a floating body type PD type SOI structure in the digital circuit section 110, the present invention is not limited to this. The monitoring circuit may be configured by a body-tie type MOSFET having a PD-type SOI structure in the analog circuit section 100.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an example of a configuration of a watch IC configured by a MOSFET having an SOI structure including a voltage generation circuit according to an embodiment.

FIG. 2 is a configuration diagram illustrating an example of a main configuration of a constant voltage generation circuit according to the embodiment;

FIG. 3 is a block diagram illustrating an example of a configuration of a monitoring circuit according to the present embodiment.

FIGS. 4A and 4B are explanatory diagrams showing an example of a control result of a constant voltage value generated by a constant voltage generation circuit controlled by a control signal.

FIG. 5 is a configuration diagram illustrating another example of a main part of the configuration of the constant voltage generation circuit according to the embodiment;

FIG. 6 is a block diagram illustrating another example of the configuration of the monitoring circuit according to the embodiment;

FIG. 7 is a block diagram illustrating an example of a configuration of a semiconductor device having a built-in voltage generation circuit according to the embodiment;

FIGS. 8A and 8B are block diagrams of an example of the electronic apparatus of the embodiment.

FIGS. 9A, 9B, and 9C are examples of external views of various electronic devices.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 analog circuit section 102 constant voltage generation circuit 104 oscillation circuit 106 detection circuit 110 digital circuit section 112 frequency divider circuit 114 control circuit 116, 290 monitoring circuit 120 power supply line 130 crystal oscillator 132 divided signal 134 operation state notification signal terminal 136 detection Result signal 138 Clock signal 140 Control signal 200 Differential pair comparator circuit 202, 214, 216 Constant current source 204, 206, 212, 212 ₁ , 212 ₂ , 28
2 ₁ , 282 ₂ P-channel MOSFETs 208, 210, 218 _{1 to} 218 ₃ , 222, 224 ₁
~ 224 ₃ N-channel type MOSFET 220 Output terminal 250 Monitor circuit 252 Timer circuit 254,294 Decoder circuit 260 Oscillation condition detection signal 262 Timeout signal 292 Counter circuit 296 Count up signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/08 331 H01L 29/78 626B F term (Reference) 2F002 AA07 AB06 AC01 AD08 AE01 BA02 BA04 CB02 EA01 EA05 EB01 EB11 EC05 GA04 GA06 5F038 AV06 BB04 BG02 BG06 CD06 DF01 EZ06 EZ20 5F048 AB03 AB08 AC04 BA16 BE09 5F110 AA15 BB03 BB04 GG60 5H420 NA17 NB02 NB25 NC02 NE26

Claims (10)

[Claims] A first power supply line for supplying a first potential; a second power supply line for supplying a second potential lower than the first potential; and the first and second power lines. And at least a part of the transistor as a component is a partially depleted S in which the body region and the source region are electrically connected.
A constant voltage generating circuit including a field effect transistor having an OI structure; and a third voltage supply circuit configured to supply a constant voltage generated by the constant voltage generating circuit with reference to one of the first and second potentials. A power supply line, and at least a part of a transistor as a component electrically connected to the first and third power supply lines, wherein a partially depleted S having a body region in an electrically floating state is provided.
A monitoring circuit comprising a field effect transistor having an OI structure;
Wherein the constant voltage generation circuit generates the constant voltage having a value corresponding to a given control signal; and the monitoring circuit includes a partially depleted SOI structure electric field in which a body region is in an electrically floating state. A voltage generation circuit for monitoring an oscillation output of an oscillation circuit via a given operation circuit constituted by an effect transistor and generating the control signal as a result of the monitoring. 2. The monitoring circuit according to claim 1, wherein the monitoring circuit monitors a lapse of time since the power-on, and gradually changes the value of the constant voltage to a given first voltage value according to the lapse of time. A voltage generation circuit for generating the control signal so as to approach the voltage generation circuit. 3. The first voltage value according to claim 1, wherein the monitoring circuit counts pulses of the oscillation output of the oscillation circuit, and the value of the constant voltage is given stepwise based on the count result. A voltage generating circuit for generating the control signal so as to approach the voltage. 4. The constant voltage generation circuit according to claim 1, wherein one end of the constant voltage generation circuit is electrically connected to the second power supply line, and one end of the first constant current source is the first constant current source. A second constant current source electrically connected to the power supply line, a body region electrically connected to the source region electrically connected to the first power supply line, and a gate electrode and a drain region connected to the first and second power supply lines. A first P-channel field effect transistor having an SOI structure electrically connected to the other end of the first constant current source; and one of the first P-channel field effect transistors is electrically connected to a gate electrode of the first P-channel field effect transistor A differential pair comparator circuit electrically connected to the other end of the second constant current source; a body region electrically connected to the source region; and a gate electrode and a drain region connected to the second constant current source. Electrically connected to the other end of the constant current source A first N-channel field-effect transistor having one or more SOI structures; and a gate electrode electrically connected to a gate electrode of the first P-channel field-effect transistor among differential outputs of the differential pair comparator circuit. Connected, the body region and the source region are electrically connected to the second power supply line, and the drain region is electrically connected to the third power supply line for supplying the constant voltage. A connected second N-channel field effect transistor, a drain region electrically connected to the source region of each of the first N-channel field effect transistors, and a body region electrically connected to each of the source regions. The given control signal is supplied to the gate electrode, and the source region is electrically connected to the third power supply line. Voltage generating circuit which comprises a Yaneru type field effect transistor. 5. The constant voltage generation circuit according to claim 1, wherein one end of the constant voltage generation circuit is electrically connected to the second power supply line, and one end of the first constant current source is connected to the first power supply line. A second constant current source electrically connected to the power supply line of the first transistor, a body region electrically connected to the source region, and a gate electrode and a drain electrically connected to the other end of the first constant current source. One or a plurality of SOI-structured first P-channel field effect transistors, each body region being electrically connected to a source region electrically connected to the first power supply line, and a drain A second P-channel field effect transistor of one or more SOI structures, wherein a region is connected to the source region of each of the first P-channel field-effect transistors and the given control signal is supplied to each gate electrode; Transi A differential pair comparator circuit, one of which is electrically connected to a gate electrode of the first P-channel field effect transistor and the other is electrically connected to the other end of the second constant current source. A body region connected to the source region, a gate electrode and a drain region electrically connected to the other end of the second constant current source, and the third power source for supplying the constant voltage to the source region. Of the SOI structure electrically connected to the line
An N-channel field effect transistor having a gate electrode electrically connected to a differential output of the differential output of the differential pair comparator circuit connected to the gate electrode of the first P-channel field effect transistor; A second N-channel type in which a body region and a source region are electrically connected to the second power supply line, and a drain region is electrically connected to a source region of the first N-channel type field effect transistor A voltage generation circuit, comprising: a field-effect transistor; 6. The constant voltage generation circuit according to claim 1, wherein one end of the constant voltage generation circuit is electrically connected to the second power supply line, and one end of the first constant current source is connected to the first power supply line. A second constant current source electrically connected to the first power supply line, a body region electrically connected to the source electrically connected to the first power supply line, and a gate electrode and a drain region connected to the second power supply line. SO electrically connected to the other end of the constant current source 1
A first P-channel field-effect transistor having an I structure, one of which is electrically connected to a gate electrode of the first P-channel field-effect transistor, and the other of which is electrically connected to the other end of the second constant current source. A differential pair comparator circuit that is electrically connected, a body region is electrically connected to a source region, a gate electrode and a drain region are electrically connected to the other end of the second constant current source, And a first N-channel field-effect transistor having an SOI structure electrically connected to the third power supply line for supplying the constant voltage. Wherein the constant current value is changed so that the value of the constant voltage gradually approaches a given first voltage value. 7. The method according to claim 6, wherein the constant current value of the second constant current source is changed so that the value of the constant voltage gradually approaches a given first voltage value. A voltage generating circuit characterized in that: 8. The voltage generation circuit according to claim 1, wherein the oscillation circuit is a crystal oscillator. 9. A timepiece comprising the voltage generation circuit according to claim 1. Description: 10. An electronic apparatus comprising the voltage generation circuit according to claim 1.