JP2002110982A - Field effect transistor - Google Patents

Abstract

(57) Abstract: Provided is a technique for reducing the conduction resistance of a field effect transistor. In a field effect transistor according to the present invention, a first base region is formed on a surface of a drain layer in which a plurality of holes are formed, and a second base region is formed on an inner bottom surface of the hole. ing. When a voltage equal to or higher than the threshold voltage is applied to the gate electrode film 22 in a state where a voltage is applied between each of the source regions 43 and 44 and the drain layer 12, an inversion layer is formed in each of the base regions 29 and 28 and a conductive layer is formed. State.
At this time, a depletion layer spreads outside each of the base regions 29 and 28. However, as compared with the conventional case where each base region is arranged on the same plane, the distance between the base regions 29 and 28 is increased by the depth of the hole. As it becomes larger, the depletion layer does not connect as in the past,
A gap is created between each depletion layer. Since the current flows through this gap, the conduction resistance is lower than in the conventional case where no current flows unless the current passes through the high-resistance depletion layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a field effect transistor having a high withstand voltage and a low resistance.

[0002]

2. Description of the Related Art Hitherto, a field effect transistor which allows a current to flow in a thickness direction of a substrate has been used as a power control element. Referring to FIG. 34, reference numeral 105 denotes an example of a conventional field effect transistor, which is a silicon single crystal substrate 11
One. On the surface of single crystal substrate 111, drain layer 112 formed by epitaxial growth is arranged.

An N-type impurity is heavily doped in a silicon single crystal substrate 111, and a drain electrode film 148 is formed on the back surface thereof. In the drain layer 112, an N-type impurity is doped at a low concentration, and a p-type base region 154 is formed near the surface. In the base region 154, an N-type impurity is further diffused from the surface to form a source region 161.

[0004] Reference numeral 110 denotes a channel region located between the edge of the source region 161 and the edge of the base region 154. Above the channel region 110, a gate insulating film 126 and a gate electrode film 127 are arranged in this order. An interlayer insulating film 141 is formed on the surface and side surfaces of the gate electrode film 127, and a source electrode film 144 is disposed on the surface.

The above-described base region 154 is arranged in the form of an island in the vicinity of the surface of the drain region 112. One base region 154 and the source region 161 and the channel region 110 arranged in the base region 154 are arranged. And 1
Cells 101 are formed. FIG. 35 is a plan view showing the surface of the drain region 112, and a plurality of rectangular cells 101 are arranged in a matrix.

When the field effect transistor 105 is used, the source electrode film 144 is set to the ground potential, a positive voltage is applied to the drain electrode film 148, and the gate electrode film 127
When a gate voltage (positive voltage) equal to or higher than the threshold voltage is applied to the p-type channel region 110, an N-type inversion layer is formed on the surface of the p-type channel region 110, and the source region 161 and the conductive region 111 are connected by the inversion layer. Transistor 10
5 conducts.

When a voltage lower than the threshold voltage (eg, ground potential) is applied to the gate electrode film 127 in this state, the inversion layer disappears, and the field effect transistor 105 is shut off. Regarding such a field effect transistor 105,
When a large number of cells 101 as described above are arranged, the cell 1
In order to reduce the area occupied by 01, it is conceivable to reduce the interval between the cells 101. FIG. 36 shows a cell 101
4 shows an internal state of the field-effect transistor 105 in which a gap between the field-effect transistors 105 is small in a conductive state.

[0008] The field effect transistor 105 having the above configuration
In the example, the cells 101 are all arranged on the surface of the drain region 112 and are arranged on the same plane. For this reason,
If the distance between the cells 101 is small, each cell
The depletion layers extending from 1 are connected to each other as shown by reference numeral 198 in FIG. In the conductive state, the carrier is denoted by reference numeral 1 in FIG.
As shown at 67, the current flows from the source region 161 to the drain region and then reaches the silicon substrate 111. At this time, since the depletion layers 198 are connected to each other, the carrier 1
67 indicates that the silicon substrate 1 must pass through the depletion layer 198.
I can't reach 11. For this reason, there has been a problem that the conduction resistance increases.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and has as its object to provide a field-effect transistor having a high withstand voltage and a low resistance.

[0010]

According to a first aspect of the present invention, there is provided a field effect transistor comprising a first conductive type high resistance layer having a plurality of holes formed in a surface thereof. A first base region of a second conductivity type disposed on a surface of the high resistance layer; a first source region of a first conductivity type disposed on a surface of the first base region; A first region located at least on an inner side surface of the hole while being in contact with the first source region.
Channel region, at least a first gate insulating film disposed on the surface of the first channel region, a first gate electrode film disposed on the surface of the first gate insulating film, A second layer disposed on the high resistance layer on the inner bottom surface;
A second base region of a conductivity type, a second source region of a first conductivity type disposed on a surface of the second base region, and a part of the second base region; A second channel region located between an outer edge portion of the base region and an outer edge portion of the second source region, a second gate insulating film disposed at least on the surface of the second channel region, A second gate electrode film disposed on the surface of the second gate insulating film. The invention according to claim 2 is the field-effect transistor according to claim 1, wherein the first source region is arranged such that an outer edge thereof is located inside an outer edge of the first base region, The first channel region is configured to be located on a surface of the first base region between an outer edge of the first base region and an outer edge of the first source region. The invention according to claim 3 is the field-effect transistor according to any one of claims 1 and 2, wherein the first gate insulating film and the second gate insulating film are connected to each other, and And the second gate electrode film are connected to each other.
According to a fourth aspect of the present invention, there is provided the field-effect transistor according to any one of the first to third aspects, wherein the first or second source region is replaced with a first or second source region.
A conductive impurity diffusion region is formed on the surface of the first or second base region. According to a fifth aspect of the present invention, there is provided the field-effect transistor according to any one of the first to fourth aspects, wherein a second conductivity type semiconductor layer is provided on a back surface of the high resistance layer. Features.

In a conventional field effect transistor, a plurality of cells are arranged on the same surface, so that the base region is also arranged on the same plane. In the field-effect transistor having such a configuration, the depletion layer expands to the outside of the base region in the conductive state. Therefore, in the field-effect transistor having the conventional structure, when the space between adjacent cells is reduced, the space between the base regions is reduced. The depletion layers extending outside the base region during conduction are more likely to contact each other.

However, in the field-effect transistor of the present invention, a plurality of holes are formed, and the surface of the high-resistance layer in a region where there is no hole and the surface of the high-resistance layer exposed at the bottom of the hole are formed.
The first and second base regions and the first and second source regions constituting the respective cells are arranged, and the first and second base regions adjacent to each other are arranged even when the interval between the cells is the same as in the related art. The spacing between the regions increases by approximately the depth of the hole.

For this reason, even if the cells are arranged at a smaller interval than in the prior art, the interval between the first and second base regions can be maintained at the same level or higher than the conventional level. The depletion layers extending from the first and second base regions do not contact each other, and a gap is formed between the depletion layers.

Therefore, in the conductive state, carriers can flow from the source region to the high-resistance layer through the gaps between the depletion layers, so that the carriers have to pass through the high-resistance depletion layer. , The conduction resistance becomes lower.

In the field effect transistor of the present invention, the first and second gate insulating films may be connected to each other, and the first and second gate electrode films may be connected to each other.

Further, in the field effect transistor of the present invention, an IGBT (Insulated gate bipolar transistor) having a semiconductor layer of the second conductivity type provided on the back surface of the high resistance layer.
The structure of r) may be adopted.

Further, in the IGBT structure, a first conductivity type impurity diffusion region is formed on the surface of the first or second base region, and a thyristor cell forming a pn junction therebetween is provided; , The thyristor cell has an EST (Emitt) structure that is not electrically connected to the source region.
(er switched thyristor) structure.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A field effect transistor according to the present invention will be described with reference to the drawings. Referring to FIG. 1, reference numeral 1 denotes a field-effect transistor according to an example of the present invention. This field effect transistor 1 has an n ⁺ type silicon substrate 11. On the surface of the silicon substrate 11, a high resistance layer 12 made of an n-type impurity is formed by epitaxial growth.

On the surface of the high resistance layer 12, a plurality of rectangular holes are formed at predetermined intervals. Here, the length of one side of the hole is 8 μm, and the depth of the hole is 2 μm. A first surface and a second surface are provided on the surface of the high resistance layer 12 and the bottom surface of the hole, respectively.
Cells 51 and 52 are formed.

The first cell 51 has a first base region 29 formed on the surface of the high resistance layer 12 and having a p-type impurity diffused. The outer edge portion of the first base region 29 reaches the inner side surface of the hole. In a central region on the surface of the first base region 29, a first source contact region 38 in which a high concentration p ⁺ -type impurity is diffused is arranged. At the outer edge of the surface of the first base region 29,
A first source region 43 in which an n-type impurity is diffused is arranged. This first source region 43 is arranged in contact with first source contact region 38. A portion of the first base region 29 near the inner side surface of the hole serves as a first channel region 99.

On the other hand, the second cell 52 is disposed on the surface of the high resistance layer 12 located at the bottom of the hole, and has a second base region 28 in which p-type impurities are diffused. The second base region 28 has its outer edge located on the inner bottom surface of the hole, and is arranged so as to fit inside the outer periphery of the inner bottom surface of the hole. Here, the outer edge of the second base region 28 is located 0.5 μm inside the outer periphery of the hole.

On the surface of the second base region 28, there is arranged a second source contact region 39 in which a high concentration of p ⁺ -type impurity is diffused in the central region. At the outer edge of the second source contact region 39, a second source region 44 formed by diffusing an n-type impurity is arranged.
The outer edge is located inside the outer edge of the second base region 28. On the surface of the second base region 28 located on the inner bottom surface of the hole, the region between the outer edge of the second base region 28 and the outer edge of the second source region 44 is:
The second channel region 98 is formed. The impurity concentration on the surface of the first base region 29 is adjusted to be lower than the impurity concentration on the surface of the second base region 28. As a result, the impurity concentration of the first and second channel regions 99 and 98 is adjusted. Are almost equal to each other.

The inner side surface of the hole is located on the inner bottom surface of the hole.
Up to a portion of the second source region 44
A gate insulating film made of In the figure, the holes
Gate insulating film located on the inner bottom surface of the first gate insulating film
Reference numeral 31 denotes the film₁Shown on the inside side of the hole
The gate insulating film is referred to as a second gate insulating film and denoted by reference numeral 31. _Two
Shown in This second gate insulating film 31_TwoFirst from the top of
The base oxide film 33 is arranged in the source region 43 of FIG.
You.

A gate electrode film 22 made of polysilicon is disposed on the surfaces of the first and second gate insulating films 31 ₁ and 31 ₂ and the underlying oxide film 33. Gate electrode film 22
The first and second source regions 43 and 44 are formed by the first and second gate insulating films 31 ₁ and 31 ₂ and the underlying oxide film 33.
It is insulated from the first and second base regions 29 and 28.

An interlayer insulating film 45 is arranged on the gate electrode film 22 so as to cover the gate electrode film 22. First and second source regions 43 and 44 and first and second
Source contact regions 38 and 39 and an interlayer insulating film 45
A source electrode film 46 made of Al is disposed on the surface of the substrate. The source electrode film 46 is in contact with the first and second source regions 43 and 44 and the first and second source contact regions 38 and 39 and is electrically connected thereto. It is in a state of being insulated from the electrode film 22.

On the entire back surface of the silicon substrate 11, a drain electrode film 47 made of a metal film that forms an ohmic junction with the silicon substrate 11 is disposed. The drain electrode film 47 is electrically connected to the high resistance layer 12 via the silicon substrate 11.

FIG. 37 is a plan view showing the surface of the high-resistance layer 12.
52 are arranged in a checkered pattern. The left side of FIG. 1 is a cross-sectional view taken along the line AA of FIG.

On the other hand, in the peripheral region of the silicon substrate 11,
Neither the first nor the second cell 51, 52 is formed. The peripheral area is indicated by reference numeral 53 in FIG. In the peripheral region 53, a p-well region 14 in which a p-type impurity is diffused is arranged on the surface of the high resistance layer 12, and a diffusion in which the p-type impurity is diffused in contact with the p-well region 14. A layer 30 is arranged. On the surface of the diffusion layer 30,
A high-concentration diffusion region 40 formed by diffusing high-concentration p ⁺ -type impurities is provided.

The surface of the high resistance layer 12 has a p-well region 1
4, a thick field oxide film 15 is arranged at a position overlapping with a part thereof. In contact with the side surface of the field oxide film 15, the entire region of the p-well region 14 and the diffusion layer 3
A thin field oxide film 16 is arranged so as to cover a part of region 0. Further, a silicon oxide film 19 is arranged so as to cover a part of the high concentration diffusion region 40 in contact with the side surface of the thin field oxide film 16.

On the silicon oxide film 19, the thin field oxide film 16 and the thick field oxide film 15, a conductor film 23 made of polysilicon is arranged from the p-well region 14 to the region where the high concentration diffusion region 40 is formed. I have. On the conductor film 23, an interlayer insulating film 45 is arranged so as to cover the conductor film 23, and on the interlayer insulating film 45, A
A gate electrode metal film 78 of l is disposed. An opening is provided in the interlayer insulating film 45, and the gate electrode metal film 78 is electrically connected to the conductor film 23 through this opening.

The conductor film 23 is electrically connected to the plurality of gate electrode films 22 at locations not shown,
In addition, since the conductor film 23 is electrically connected to the gate electrode metal film 78, it is configured such that when a voltage is applied to the gate electrode metal film 78, a voltage can be applied to all the gate electrode films 22. ing.

The steps of manufacturing the field effect transistor 1 will be described below with reference to FIGS. 3 (a) and 3 (b) to FIGS. 29 (a) and (b). FIGS. 3A to 29A are cross-sectional views showing a manufacturing process of a region (hereinafter, referred to as a cell region) in which the first and second cells 51 and 52 are formed. b)
29B are cross-sectional views illustrating a manufacturing process of the peripheral region 53.

First, n ⁺ having a resistivity of 3 × 10 ⁻³ Ω · cm
On the surface of the silicon substrate 11, an n ⁻ -type silicon single crystal having a thickness of 4 to 5 μm and a resistivity of 0.3 Ω · cm is epitaxially grown to form a high resistance layer 12 (FIGS. 3A and 3A).
(b)).

Next, a field oxide film 15 is formed to a thickness of 0.5 μm on the entire surface of the high-resistance layer 12 by performing a thermal oxidation process, and then the field oxide film 15 is patterned to form a field oxide film in the peripheral region. An opening 81 is formed in the oxide film 15 and the surface of the substrate in that state is irradiated with a p-type impurity. Since the p-type impurity cannot pass through the field oxide film 15, the p-type impurity is injected only into the high-resistance layer 12 in the region where the opening 81 is formed in the peripheral region, and the p-type implantation layer 13 is formed in this region. . This state is shown in FIGS. 4 (a) and 4 (b).

Next, when heat treatment is performed, the p-type impurity is diffused, and the p-well region 14 is formed immediately below the opening 81, as shown in FIGS. Next, a field oxide film 16 is formed to a thickness of 0.5 μm on the surface of the p-well region 14 by a thermal oxidation method (FIGS. 6A and 6B). Then, the already formed field oxide film 15 is thickened by thermal oxidation, and its thickness becomes 0.8 μm.

Next, the field oxide films 15 and 16 are patterned to leave the field oxide films 15 and 16 so as to overlap a part of the p-well region 14, and then a base oxide film 17 is formed by a thermal oxidation method. I do. At this time, in the peripheral region, the underlying oxide film 17 is hardly formed on the surfaces of the field oxide films 15 and 16, and the exposed high resistance layer 1 is exposed.
No. 2 is formed only on the surface.

Thereafter, the PSG film 1 is formed on the entire surface by the CVD method.
8 is formed. The state is shown in FIGS. 7 (a) and 7 (b). In the cell region, since the field oxide films 15 and 16 have been completely removed, FIG.
5 and 16 do not appear.

Next, a resist film 71 is formed on the entire surface and patterned to form openings at predetermined intervals in a plurality of cell regions. Then, using the resist film 71 as a mask, the base oxide film 17 and the PSG film are formed. 18 is etched to form openings 82 in the underlying oxide film 17 and the PSG film 18. FIGS. 8A and 8B show the state. Although a large number of openings 82 are formed in the cell region, FIG. 8A shows only one opening 82. Since the opening 82 is formed only in the cell region, the opening 82 does not appear in FIG.

Next, after removing the resist film 71, P
Using the SG film 18 and the base oxide film 17 as a mask, the high resistance layer 12 exposed from the opening 82 is etched to form a hole 83 in the high resistance layer 12. FIGS. 9A and 9B show the state.
Shown in

Next, a resist film (not shown) is formed on the surface of the cell region, and the PSG film 18 is etched using the resist film as a mask. Then, the PSG film 18 in the peripheral region where the resist film is not formed and the base oxide film 17 are selectively removed. The state is shown in FIGS. 10 (a) and 10 (b).

Next, a silicon oxide film 19 is deposited to a thickness of 0.05 μm by a thermal oxidation method. This silicon oxide film 19 functions as a gate oxide film by covering the inner bottom surface and side surfaces of the hole 83 in the cell region. Thereafter, a polysilicon layer 20 is formed on the surface of the silicon oxide film 19 by CVD.
Is deposited to a thickness of 0.5 μm. FIG. 11 shows the state.
(a) and (b) show.

Next, the polysilicon layer 2 is formed by the CVD method.
The PSG film 21 is deposited to a thickness of 1 μm on the surface of No. 0.
This state is shown in FIGS. 12 (a) and 12 (b). Next, the PSG film 21 is etched for a predetermined time. Then, the PSG film 21
Most of the PSG film is removed, and the PSG film 21 located on the side surface of the polysilicon layer 20 formed inside the hole remains. This state is shown in FIGS. 13 (a) and 13 (b).

Next, a resist film 72 is selectively formed on the surface of the polysilicon layer 20 formed on the p-well region 14 in the peripheral region (FIGS. 14A and 14B).
Using polysilicon 2 as a mask, polysilicon layer 20 is etched for a predetermined time.

Then, in the cell region, as shown in FIG. 15A, most of the polysilicon layer 20 is removed, and the polysilicon layer remains from the periphery of the inner bottom surface of the hole to a position below the inner side surface, In the center of the inner bottom surface of the hole is an opening 8
4 are formed. The remaining polysilicon layer is called a gate electrode film, and is indicated by reference numeral 22. On the other hand, in the peripheral region, the polysilicon layer remains only on p-well region 14. This polysilicon layer is called a conductor film, and is denoted by reference numeral 2 in FIG.
3 is shown. The conductor film 23 and the gate electrode film 22 are connected at a location (not shown).

Next, the substrate surface is irradiated with p-type impurities. Then, in the cell region, as shown in FIG.
The type impurity is formed in the opening 84 and the silicon oxide film 19 immediately therebelow.
Is implanted into the surface of the high-resistance layer 12 exposed at the center of the bottom of the hole, and a p-type implantation layer 26 is formed.

On the other hand, in the peripheral region, as shown in FIG.
6 cannot be transmitted through the conductive film 23, and is injected into the surface of the high-resistance layer 12 through the silicon oxide film 19, and a p-type injection layer 27 is formed at a position in contact with the p-well region 14.

Next, a resist (not shown) is formed in the peripheral area 53.
A film is formed, and using this as a mask, a silicon oxide film 19,
The PSG film 18 and the PSG film 21 are etched. Do
In the cell region where the resist film is not formed,
When the PSG film 18 and the PSG film 21 are completely removed,
Most of the silicon oxide film 19 is also removed,
Electrode film 22 and first body region 2 located on the side of electrode film 22
9 and the gate oxide
The silicon oxide film located below the pole film 22 remains.
As a result, an opening 85 is formed in the center region of the hole,
The surface of the anti-layer 12 is exposed. Of the remaining silicon oxide film
Of these, the silicon remaining on the side of the gate electrode film 22
The silicon oxide film is referred to as a first gate insulating film, and
Code 31 ₁And remained under the gate electrode film 22.
The silicon oxide film is referred to as a second gate insulating film and denoted by reference numeral 31.
_TwoShown in

Next, the surface is irradiated with a p-type impurity for a predetermined time. Then, the p-type impurity is applied to the high resistance layer 1 in the cell region.
2 to form a p-type implanted layer 25. At this time, the p-type implantation layer 26 formed at the bottom of the hole is subjected to the second p-type impurity implantation.
The concentration becomes higher than the surface concentration of the p-type injection layer 25 on the surface of the high resistance layer 12 (FIG. 18A).

Next, when heat treatment is performed, the p-type implanted layer 25,
The p-type impurities are diffused at 26 and 27 to form a first base region 29 on the surface of the high resistance layer 12 in the cell region, and a second base region on the surface of the high resistance layer 12 at the bottom of the hole. 28 are formed. At this time, the outer edge of the first base region 29 reaches the side surface of the hole, and the outer edge of the second base region 28 is located inside the outer periphery of the hole. On the other hand,
A diffusion layer 30 is formed on the surface of the high resistance layer 12 in the peripheral region. The state is shown in FIGS. 19 (a) and (b).

Next, the first base region 29 of the cell region
An underlying oxide film 33 is formed on the surface of the substrate by a thermal oxidation method (FIG. 20).
(a), (b)). Then, the first and second base regions 29,
28, and an opening 87 in the central region of the diffusion region 30,
A resist film 73 having 86 and 88 is formed.

When the surface of the resist film 73 is irradiated with a p-type impurity in this state, the p-type impurity is exposed to the openings 87, 86,
The surfaces of the first and second base regions 29 and 28 and the surface of the diffusion region 30 are respectively implanted through 88, and p-type implanted layers 36, 35 and 37 are formed on the respective surfaces.
(FIGS. 21A and 21B).

Next, when the resist film 73 is removed and heat-treated, the p-type impurities diffuse, and the p-type
First and second source contact regions 38 and 39 made of p-type high-concentration impurities are formed in the formation regions 6 and 35, respectively, and high-concentration diffusion regions 40 made of p-type high-concentration impurities are formed in the peripheral region. (FIGS. 22A and 22B).

Next, a resist film 74 covering the central regions of the first and second source contact regions 38 and 39 and the entire region of the diffusion layer 30 is formed.
Is used as a mask to implant an n-type impurity. Then, as shown in FIG. 23A, the n-type impurity becomes first base region 29.
To form an n-type implanted layer 41, and to the surface of the outer edge of the second source contact region 39 to form an n-type implanted layer. On the other hand, in the peripheral region, the resist film 74 covers the entire diffusion layer 30 as shown in FIG.
Therefore, no n-type impurity is implanted at all.

Next, when the resist film 74 is removed and a heat treatment is performed, the n-type impurities in the n-type implantation layers 41 and 42 are diffused, and the first and second regions are formed in the regions where the n-type implantation layers 41 and 42 are formed. Source regions 43 and 44 are formed as shown in FIG.
(b)). Next, an interlayer insulating film 45 made of PSG is formed to a thickness of 1 μm on the entire surface by the CVD method (FIG. 25A,
(b)).

Next, a resist film 7 is formed on the surface of the interlayer insulating film 45.
5 is formed. In the cell region, the resist film 75 includes a region where the first source region 43 and the first source contact region 38 are formed and a region where the second source region 44 and the second source region 43 are formed.
And a region where the source contact region 39 is formed, while the peripheral region has an opening in the diffusion layer 3.
0 and a part of the formation region of the conductor film 23 have openings respectively.

Using this resist film 75 as a mask,
The insulating film 45 is etched for a predetermined time. At this time
In the region, as shown in FIG.
31 ₁And the underlying oxide film 33 is etched to form an opening 8.
9 and 86 are respectively formed, and the first
Source region 43 and first source contact region 38
At the same time, the second source region is exposed through the opening 86.
44 and the second source contact region 39 are exposed.
You. On the other hand, in the peripheral area, as shown in FIG.
The surface of the diffusion layer 30 and the high concentration diffusion region 40 from the mouth 90
At the same time, a portion of the conductor film 23 is exposed through the opening 91.
Is exposed.

Next, after removing the resist film 75, a metal film 77 made of Al is formed on the entire surface by vapor deposition (FIGS. 27A and 27B). Next, a resist film 76 is formed on the entire surface, and an opening 92 is formed in a part of the resist film 76 in the peripheral region.
Is formed (FIGS. 28A and 28B).

Next, the metal film 77 is etched using the resist film 76 as a mask to remove the metal film 77 in the peripheral region at the position where the opening 92 is formed, and the first and second source regions 43 and 44 are electrically connected to each other. In addition to forming the source electrode film 46 that is electrically connected, the gate electrode metal film 78 that is electrically connected to the conductor film 23 in the peripheral region is formed. Thereafter, the resist film 76 is removed, a metal film for forming an ohmic junction with the silicon substrate 11 is deposited on the back surface of the silicon substrate 11, and the drain electrode film 47 is formed on the entire back surface of the silicon substrate 11.
Is formed (FIGS. 29A and 29B). Through the steps described above, the field effect transistor 1 shown in FIG. 1 is completed.

In the field effect transistor 1 described above, the source electrode film 46 is set at the ground potential and the drain electrode film 47
In a state where a positive voltage is applied to the gate electrode film 22 while a positive voltage is applied to the gate electrode film 22, the field effect transistor 1 is in a cut-off state. FIG. 2B shows the state of the field effect transistor 1 in the cutoff state. As described above, the impurity concentrations of the second channel region 98 and the first channel region 99 are substantially equal, and as a result, the threshold voltages are substantially equal in the first and second cells 51 and 52. Has become. Reference numeral 69 in FIG. 2B indicates a depletion layer in a cutoff state.
Connected to each other.

When a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode film 22 from the cutoff state, in the first cell 51, the p-type first channel region 99 and the first gate insulating film 31 ₁ An n-type inversion layer is formed at the interface between the drain region and the first source region 43 in the inversion layer, and a conductive state is established.

[0061] On the other hand, in the second cell 52, the inversion layer of n-type at the interface between the second channel region 98 of p-type and ₂ second gate insulating film 31 is formed, the drain region in the inversion layer And the second source region 44 are connected to be in a conductive state. The state is shown in FIG.

In this state, the first and second base regions 2
The depletion layer extends to the outside of 9, 28. Depletion layers extending from the first and second base regions 29 and 28 are indicated by reference numerals 65 and 66 in FIG. 2, respectively.

In the present embodiment, a plurality of holes are formed, and the resulting irregularities are formed by first and second planar type, respectively.
Since the cells 51 and 52 are formed, the first and second base regions 29 and 28 are respectively formed in the concave and convex portions formed by the holes, unlike the conventional case where all the cells are arranged on the same plane. And are not arranged on the same plane, and the outer edge of the second base region 28 is located 0.5 μm inside the outer periphery of the hole as described above.
The distance between the first and second base regions 29 and 28 adjacent to each other is increased substantially by the depth of the hole.
The depletion layers 65 and 66 extending from 9 and 28 do not contact each other, and a gap is created between the depletion layers 65 and 66.

Carriers flowing in the first and second cells 51 and 52 are indicated by reference numerals 68 and 67 in FIG. These carriers 68 and 67 flow to the silicon substrate 11 through the gaps between the depletion layers 65 and 66, so that the carriers pass through the high-resistance depletion layer, so that the conduction resistance is higher than in the conventional case. As a result, the conduction resistance decreases.

In the above-described embodiment, the first cell 51 has a structure in which the outer edge of the first source region 43 reaches the outer edge of the first base region 29.
The present invention is not limited to this. For example, as shown in a sectional view of FIG. 30, the outer edge of the first source region 54 does not reach the outer edge of the first base region 29. The field effect transistor 2 may have a structure having one cell 55. In this case, as shown in FIG. 30, the portion between the outer edge of the surface of the first base region 29 and the outer edge of the first source region 54 (reference numeral 96) is included in the first channel region. become.

Although the n-type silicon substrate 11 is used in the field-effect transistor 1 of FIG. 1, a p-type silicon substrate 97 is used instead of the n-type silicon substrate 11 as shown in FIG. Alternatively, the IGBT 3 having a structure in which the collector electrode 95 is arranged on the back surface of the silicon substrate 97 may be configured.

Further, as shown by reference numeral 4 in FIG. 32, in the IGBT 3 described above, the second source contact region and the second source contact region are formed in the second base region 28 formed at the bottom of the hole of the high resistance layer 12. No source region is provided, and an n-type impurity diffusion layer 57 is disposed on the surface of the second base region
Thyristor cell 56 in which a pn junction is formed between base region 28 and impurity diffusion layer 57, and EST having a structure in which thyristor cell 56 is not electrically connected to source electrode film 46. Is also good. Similarly, FIG.
As indicated by reference numeral 5 in FIG. 3, in the above IGBT 3,
An n-type impurity diffusion layer 59 is formed on the surface of the first base region 29 formed on the surface of the high resistance layer 12, and a thyristor cell 58 formed by the first base region 29 and the impurity diffusion layer 59 is formed. The EST may have a structure in which the thyristor cell 58 is not electrically connected to the source electrode film 46.

In the above embodiment, the first conductivity type is set to n.
Although the second conductivity type is a p-type, the present invention is not limited to this, and the first conductivity type may be a p-type and the second conductivity type may be an n-type.

The high-resistance layer 12 is formed by epitaxial growth on the silicon substrate 11.
The high-resistance layer 12 is formed of the high-resistance silicon wafer itself, and impurities of the same conductivity type as the high-resistance layer 12 are diffused from the back side of the high-resistance layer 12, so that the silicon substrate 11 has a lower resistance than the high-resistance layer 12. May be configured.

The first and second gate insulating films 31 ₁ and 31 ₂ are integrated, but the present invention is not limited to this, and the first and second gate insulating films 31 ₁ and 31 ₂ are not limited thereto. What is necessary is just to be arrange | positioned so that the area | regions 99 and 98 may be contacted, for example, it may be mutually divided. Similarly, the gate electrode film 22 includes first and second gate insulating films 31 ₁ and 3 ₁
1 ₂ but both are formed over the gate electrode film of the present invention is not limited thereto, for example, as a gate electrode film is divided into two parts, the gate electrode film of each of which is divided the first may be configured to be arranged on the second gate insulating film 31 _1, 31 ₂ of the surface.

[0071]

As described above, it is possible to obtain a field effect transistor having a small occupation area and a low conduction resistance.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a field-effect transistor according to one embodiment of the present invention.

2A is a cross-sectional view illustrating a conduction state of a field-effect transistor according to one embodiment of the present invention; FIG. 2B is a cross-sectional view illustrating a blocking state of a field-effect transistor according to one embodiment of the present invention;

FIG. 3A is a first cross-sectional view illustrating a manufacturing process of a cell region of the field-effect transistor of the present embodiment. FIG. 3B is a first cross-sectional view illustrating a manufacturing process of a peripheral region of the field-effect transistor of the present embodiment. 1 cross section

FIG. 4A is a second cross-sectional view illustrating a manufacturing process of a cell region of the field-effect transistor of the present embodiment. FIG. 4B is a second cross-sectional view illustrating a manufacturing process of a peripheral region of the field-effect transistor of the present embodiment. Sectional view of 2

FIG. 5A is a third cross-sectional view illustrating a manufacturing process of the cell region of the field-effect transistor according to the embodiment; and FIG. 5B is a third cross-sectional view illustrating the manufacturing process of the peripheral region of the field-effect transistor according to the embodiment. Sectional view of 3

FIG. 6A is a fourth cross-sectional view illustrating a manufacturing process of the cell region of the field-effect transistor of the present embodiment. FIG. 6B is a fourth cross-sectional view illustrating the manufacturing process of the peripheral region of the field-effect transistor of the present embodiment. Sectional view of 4

FIG. 7A is a fifth cross-sectional view illustrating a manufacturing process of the cell region of the field-effect transistor according to the embodiment; FIG. 7B is a fifth cross-sectional view illustrating the manufacturing process of the peripheral region of the field-effect transistor according to the embodiment; Sectional view of 5

FIG. 8A is a sixth cross-sectional view illustrating a manufacturing process of the cell region of the field-effect transistor of the present embodiment. FIG. 8B is a sixth cross-sectional view illustrating the manufacturing process of the peripheral region of the field-effect transistor of the present embodiment. Sectional view of 6

FIG. 9A is a seventh cross-sectional view illustrating a manufacturing process of the cell region of the field-effect transistor according to the embodiment. FIG. 9B is a seventh cross-sectional view illustrating the manufacturing process of the peripheral region of the field-effect transistor according to the embodiment. Sectional view of 7

FIG. 10A is an eighth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the embodiment; FIG. 10B is a sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment; Sectional view of 8

FIG. 11A is a ninth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the embodiment; FIG. 11B is a ninth cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment; Sectional view of 9

FIG. 12A is a tenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the embodiment; FIG. 12B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment; 10 cross section

13A is an eleventh cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the embodiment; FIG. 13B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment; Sectional view of 11

14A is a twelfth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the present embodiment. FIG. 14B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment. Sectional view of 12

FIG. 15A is a thirteenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the embodiment; FIG. 15B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment; Sectional view of 13

FIG. 16A is a fourteenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor of the present embodiment. FIG. 16B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor of the embodiment. 14 cross section

FIG. 17A is a fifteenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor of the present embodiment. FIG. 17B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor of the embodiment. Sectional view of 15

FIG. 18A is a sixteenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor of the present embodiment. FIG. 18B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor of the embodiment. Sectional view of 16

19A is a seventeenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor of the present embodiment. FIG. 19B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor of the embodiment. Sectional view of 17

FIG. 20A is an eighteenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the present embodiment. FIG. 20B is a sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment. Sectional view of 18

21A is a nineteenth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the embodiment; FIG. 21B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment; Sectional view of 19

FIG. 22A is a twentieth cross-sectional view illustrating a manufacturing step of the cell region of the field-effect transistor of the present embodiment. FIG. 22B is a cross-sectional view illustrating the manufacturing step of the peripheral region of the field-effect transistor of the present embodiment. Sectional view of 20

23A is a cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the embodiment; FIG. 23B is a cross-sectional view illustrating a step of manufacturing the peripheral region of the field-effect transistor according to the embodiment; Sectional view of 21

FIG. 24A is a 22nd cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor of the present embodiment. FIG. 24B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor of the embodiment. Sectional view of 22

FIG. 25A is a twenty-third cross-sectional view illustrating a manufacturing step of the cell region of the field-effect transistor of the present embodiment. FIG. 25B is a second cross-sectional view illustrating the manufacturing step of the peripheral region of the field-effect transistor of the present embodiment. Sectional view of 23

FIG. 26A is a twenty-fourth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor according to the present embodiment. FIG. 26B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor according to the embodiment. 24 cross section

FIG. 27A is a twenty-fifth cross-sectional view for explaining the manufacturing process of the cell region of the field-effect transistor of the present embodiment. FIG. 27B is a second sectional view for explaining the manufacturing process of the peripheral region of the field-effect transistor of the present embodiment. 25 cross section

28A is a twenty-sixth cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor of the present embodiment. FIG. 28B is a cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor of the present embodiment. Sectional view of 26

29A is a twenty-seventh cross-sectional view illustrating a step of manufacturing the cell region of the field-effect transistor of the present embodiment. FIG. 29B is a second cross-sectional view illustrating the step of manufacturing the peripheral region of the field-effect transistor of the present embodiment. Sectional view of 27

FIG. 30 is a cross-sectional view illustrating a field-effect transistor according to another embodiment of the present invention.

FIG. 31 is a sectional view illustrating a field-effect transistor having an IGBT structure according to another embodiment of the present invention.

FIG. 32 is a cross-sectional view illustrating a field-effect transistor having a first thyristor structure according to another embodiment of the present invention.

FIG. 33 is a cross-sectional view illustrating a field-effect transistor having a second thyristor structure according to another embodiment of the present invention.

FIG. 34 is a cross-sectional view illustrating a structure of a conventional field-effect transistor.

FIG. 35 is a plan view illustrating the structure of a conventional field-effect transistor.

FIG. 36 is a cross-sectional view illustrating a conduction state of a conventional field-effect transistor.

FIG. 37 is a plan view illustrating an arrangement state of first and second cells in the field-effect transistor according to one embodiment of the present invention;

[Explanation of symbols]

11 silicon substrate 12 high resistance layer 22
... Gate electrode film 28 ... Second base region 29
... First base region 31 ₁ ... First gate insulating film 31 ₂ ... Second gate insulating film 43.
Source region 44 of the second source region 46 Source electrode film
47: drain electrode film 98: second channel region 99: first channel region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 655 H01L 29/78 655G 21/336 658F

Claims (5)

[Claims] A first conductive type high-resistance layer having a plurality of holes formed in a surface thereof; a second conductive type first base region disposed on a surface of the high-resistance layer; A first source region of a first conductivity type disposed on a surface of the base region; and a part of the first base region, at least inside the hole in contact with the first source region. A first channel region located on a side surface, at least a first gate insulating film disposed on a surface of the first channel region, and a first gate electrode disposed on a surface of the first gate insulating film A second conductive type second base region disposed on the high resistance layer on the inner bottom surface of the hole; a first conductive type second source disposed on the surface of the second base region A region, a portion of the second base region and outside the second base region A second channel region located between a portion and an outer edge portion of the second source region; a second gate insulating film disposed at least on a surface of the second channel region; and the second gate And a second gate electrode film disposed on the surface of the insulating film. 2. The first source region is arranged such that an outer edge thereof is located inside an outer edge of the first base region, and the first channel region is formed of the first base region. 2. The field effect transistor according to claim 1, wherein the field effect transistor is configured to be located on a surface between an outer edge of the first base region and an outer edge of the first source region. 3. The first gate insulating film and the second gate insulating film are connected to each other, and the first gate electrode film and the second gate electrode film are connected to each other. The field-effect transistor according to claim 1. 4. An impurity diffusion region of a first conductivity type instead of one of said first and second source regions.
4. The field effect transistor according to claim 1, wherein the field effect transistor is formed on a surface of the second base region. 5. The field effect transistor according to claim 1, wherein a semiconductor layer of a second conductivity type is provided on a back surface of said high resistance layer.