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JP2002110898A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2002110898A
JP2002110898A JP2000296328A JP2000296328A JP2002110898A JP 2002110898 A JP2002110898 A JP 2002110898A JP 2000296328 A JP2000296328 A JP 2000296328A JP 2000296328 A JP2000296328 A JP 2000296328A JP 2002110898 A JP2002110898 A JP 2002110898A
Authority
JP
Japan
Prior art keywords
electrode pad
semiconductor device
semiconductor element
wire
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000296328A
Other languages
English (en)
Other versions
JP3631120B2 (ja
Inventor
Mitsuru Komiyama
充 小宮山
Shinsuke Suzuki
臣介 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2000296328A priority Critical patent/JP3631120B2/ja
Priority to US09/963,590 priority patent/US7115977B2/en
Publication of JP2002110898A publication Critical patent/JP2002110898A/ja
Priority to US10/171,981 priority patent/US6882056B2/en
Application granted granted Critical
Publication of JP3631120B2 publication Critical patent/JP3631120B2/ja
Priority to US11/540,754 priority patent/US8053278B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

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Abstract

(57)【要約】 【目的】 本発明では、隣り合う導電ワイヤの接触を抑
制することのできる、積層された半導体素子を有する半
導体装置を提供することを目的とする。 【構成】 本発明の半導体装置は、表面に配線パターン
が形成された基板と、基板上に搭載された、第１の電極
パッドを備えた第１の半導体素子と、第１の半導体素子
上に搭載された、第２の電極パッドを備えた第２の半導
体素子と、第１の電極パッドの第１の領域と第２の電極
パッドとを接続する第１のワイヤと、第１の電極パッド
の第１の領域を除く第２の領域と配線パターンとを接続
する第２のワイヤと、を含む。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、複数の半導体素子
が積層して用いられる半導体装置に関する。
【０００２】
【従来の技術】従来、マルチチップパッケージと呼ばれ
る、１つのパッケージ内に複数の半導体素子が封止され
る技術があり、その形態として、例えば、絶縁基板上に
複数の半導体素子を積層して搭載したスタック型マルチ
チップパッケージがある。
【０００３】このような半導体装置では、積層された個
々の半導体素子の電極パッドと、絶縁基板上の内部電極
とがそれぞれワイヤにより接続されている。複数の半導
体素子、内部電極、ワイヤは封止樹脂で封止されてい
る。
【０００４】
【発明が解決しようとする課題】しかしながら、従来の
スタック型マルチチップパッケージにおいては、上段の
半導体素子と内部電極とが第１の導電ワイヤで接続さ
れ、また、下段の半導体装置と内部電極とが第２の導電
ワイヤでそれぞれ接続されているため第１の導電ワイヤ
が第２の導電ワイヤよりも長くなる。
【０００５】このため、樹脂を注入する際の圧力によ
り、長い側の第１の導電ワイヤが流され、隣り合うワイ
ヤと短絡してしまうという問題点があった。
【０００６】本発明では、隣り合う導電ワイヤの接触を
抑制することのできる、積層された半導体素子を有する
半導体装置を提供することを目的とする。
【０００７】
【課題を解決するための手段】本願発明のうち代表的な
半導体装置では、上記課題を解決するために、表面に配
線パターンが形成された基板と、基板上に搭載された、
第１の電極パッドを備えた第１の半導体素子と、第１の
半導体素子上に搭載された、第２の電極パッドを備えた
第２の半導体素子と、第１の電極パッドの第１の領域と
第２の電極パッドとを接続する第１のワイヤと、第１の
電極パッドの第１の領域を除く第２の領域と配線パター
ンとを接続する第２のワイヤと、を含む。
【０００８】
【発明の実施の形態】図１および図２は本発明の第１の
実施形態の断面図である。
【０００９】絶縁基板１上には接着剤２により下段の半
導体素子３が固定されており、下段の半導体素子３上に
は接着剤４により上段の半導体素子５が固定されてい
る。半導体素子３は、あらかじめ裏面に絶縁性の接着シ
ートが貼り付けられた半導体素子３を熱圧着にて絶縁基
板１の表面にダイスボンドすることにより絶縁基板１上
に固定することができる。半導体素子３の裏面への接着
シートの貼り付けは、ウエハ状態で行われ、接着シート
の貼り付けられたウエハを個々の半導体素子に分割する
ことで、裏面に接着シートの貼り付けられた半導体素子
が得られる。なお、半導体素子５を下段の半導体素子３
上に固定する場合も同様の手法を用いることが可能であ
る。
【００１０】絶縁基板１の表面には内部電極としての導
電パターン６が、裏面には導電パターン７がそれぞれ形
成されている。導電パターン６は絶縁基板１の表面を、
半導体素子３が搭載される領域まで引き回されている。
導電パターン６と導電パターン７とは、絶縁基板１内に
形成された図示しないスルーホールを介して互いに接続
されている。スルーホール内には例えば金などの導電材
料がメッキ等により形成されており、この導電材料によ
り導電パターン６と導電パターン７とは電気的に接続さ
れている。
【００１１】導電パターン６を絶縁基板１の表面に引き
回し、その一端を導電材料に接続することにより、絶縁
基板１の裏面の中央部分に配置される導電パターン７と
電気的に接続することが可能となる。絶縁基板１表面で
導電パターン６を引き回すことができない場合は、絶縁
基板１の裏面で導電パターン７を引き回すことも可能で
ある。
【００１２】絶縁基板１上に形成されている導電パター
ン６および導電パターン７はそれぞれソルダレジスト８
およびソルダレジスト９で覆われている。
【００１３】ソルダレジスト９から露出している導電パ
ターン７上には外部電極としての金属バンプ１０が形成
されている。金属バンプ１０としては、例えばはんだボ
ールが用いられる。この金属バンプ１０は、この半導体
装を実装基板に実装する際の電極として用いられる。
【００１４】半導体素子３の表面には電極パッド１１が
形成されている。半導体素子３の表面は、例えばシリコ
ン窒化膜などのパッシベーション膜１２で覆われてお
り、電極パッド１１はパッシベーション膜１２から露出
している。図示はされていないが、通常は電極パッド１
１の周囲はパッシベーション膜１２に覆われており、ワ
イヤがボンディングされる中央部分がパッシベーション
膜１２から露出している。
【００１５】半導体素子５においても、半導体素子３と
同様に電極パッド１３およびパッシベーション膜１４が
形成されている。
【００１６】半導体素子５は、半導体素子３よりも小さ
い外形形状を有しており、半導体素子３の電極パッド１
１と重ならないように半導体素子３上に固定されてい
る。すなわち、半導体素子５の各辺は、それぞれ半導体
素子３の各辺より短く、それぞれ半導体素子３の各辺よ
りも内側に配置される。
【００１７】半導体素子３の電極パッド１１上には金属
バンプ１５が形成されている。この金属バンプ１５は、
通常のワイヤボンディング技術を用い、ワイヤの先端の
ボール部分のみを残すことにより形成される。
【００１８】半導体素子５の電極パッド１３上にも同様
に金属バンプ１６が形成されている。
【００１９】絶縁基板１上の導電パターン６と半導体素
子３の電極パターン１１とは、導電ワイヤ１７により電
気的に接続されている。導電ワイヤ１７は、ワイヤボン
ディングの開始点であるファーストボンドが導電パター
ン６に接続するボールボンディングにより行われ、終了
点であるセカンドボンドが金属バンプ１５上に接続され
る。
【００２０】半導体素子３の電極パッド１１と半導体素
子５の電極パッド１３とは、導電ワイヤ１８により電気
的に接続されている。導電ワイヤ１８は、ファーストボ
ンドが電極パッド１１に接続するボールボンディングに
より行われ、セカンドボンドが金属バンプ１６上に接続
される。
【００２１】導電ワイヤ１７のセカンドボンドと導電ワ
イヤ１８のファーストボンドは、電極パッド１１におけ
る異なる領域において行われている。
【００２２】これら半導体素子３、半導体素子５、導電
ワイヤ１７、導電ワイヤ１８は、封止樹脂１９により封
止されている。
【００２３】図２は図１の絶縁基板１、半導体素子３、
半導体素子５のコーナー部を拡大した部分拡大図であ
り、半導体素子３の電極パッド１１における導電ワイヤ
１７および導電ワイヤ１８の接続がこの図２に示され
る。
【００２４】半導体素子３の電極パッド１１は、同一の
電極パッド内で２箇所に導電ワイヤを接続するために、
通常の電極パッドよりも大きく形成されている。電極パ
ッド１１は、本実施例では、電極パッド１１は半導体素
子３の辺近傍に設けられているとともに、この辺に沿っ
て長い矩形形状を有している。電極パッド１１は、半導
体素子３の辺近傍に設けられるとともに、この辺と直交
する方向に長い矩形形状とすることも可能である。その
場合は、下段の半導体素子３と上段の半導体素子５とを
接続する導電ワイヤ１８が半導体素子３の辺から遠い側
に、絶縁基板１と下段の半導体素子３とを接続する導電
ワイヤ１７が半導体素子３の辺に近い側にそれぞれ接続
される。電極パッド１１を辺と直交する方向に長く形成
する場合は、平行な方向に長く形成する場合に比べて、
上段の半導体素子５を搭載する領域が制限されるが、上
段と下段の半導体素子を接続する導電ワイヤ１７が、こ
れら半導体素子の辺に対して斜め方向に形成されている
場合でも、隣り合う導電ワイヤとの短絡をより効果的に
抑制できる。
【００２５】また、導電ワイヤ１７および導電ワイヤ１
８を互いに離間させて電極パッド１１上に接続できる程
度に電極パッド１１を大きく形成してもよく、その場合
は、導電ワイヤを形成する角度の自由度が向上する。
【００２６】本実施例では、上段の半導体素子３の電極
パッド１３を絶縁基板１の導電パターン６に直接接続せ
ずに、下段の半導体素子５の電極パッド１１を介して導
電パターン６に電気的に接続される。このため、電極パ
ッド１３と導電パターン６とを直接接続する長い導電ワ
イヤを用いる必要がなくなり、隣り合う導電ワイヤ間の
短絡を抑制することができる。
【００２７】また、本実施例では、下段の半導体素子５
の電極パッド１１を大きく形成し、上段の半導体素子５
と下段の半導体素子３とを接続する導電ワイヤ１８と、
下段の半導体素子３と絶縁基板１とを接続する導電ワイ
ヤ１７とを、同一の電極パッド１１における異なる領域
でそれぞれ接続している。このため、電極パッド１１に
おけるワイヤボンディングの際のストレスを低減するこ
とができる。
【００２８】電極パッド１１の周囲は図示しないパッシ
ベーション膜に覆われており、導電ワイヤ１７、導電ワ
イヤ１８がボンディングされる領域はパッシベーション
膜が除去されている。本実施の形態では、矩形形状の電
極パッド１１上で導電ワイヤ１７および導電ワイヤ１８
による２箇所のボンディングが行われる。このため、パ
ッシベーション膜が除去され、導電ワイヤがボンディン
グされる領域が電極パッド１１と略同一の矩形形状とな
る。しかしながら、電極パッド１１上でそれぞれの導電
ワイヤの間隔が離れている場合などは、電極パッド１１
上のパッシベーション膜に、それぞれの導電ワイヤに対
応する２ヶ所の開口部を形成することも可能である。
【００２９】図３は、本発明の第２の実施形態を示す図
であり、図１および図２と同一構成要素には同一の符号
が付けられている。
【００３０】第２の実施形態では、第１の実施形態とは
導電ワイヤの接続形態が異なっており、その他の構成は
第１の実施形態と同じである。
【００３１】図３において、下段の半導体素子３の電極
パッド１１上には金属バンプ２１が形成されている。金
属バンプ２１は、第１の実施形態における金属バンプ１
５、１６と同様の方法で形成される。
【００３２】下段の半導体素子３の電極パッド１１と絶
縁基板１の導電パターン６とを接続する導電ワイヤ２２
は、ファーストボンドが電極パッド１１で、セカンドボ
ンドが導電パターン６でそれぞれ行われている。
【００３３】上段の半導体素子５の電極パッド１３と下
段の半導体素子３の電極パッド１１とを接続する導電ワ
イヤ２３は、ファーストボンドが上段の半導体素子５の
電極パッド１３で、セカンドボンドが下段の半導体素子
３の電極パッド１１上に形成された金属バンプ２１上で
にそれぞれ行われる。
【００３４】本実施形態においては、上段の半導体素子
５の電極パッド１３にファーストボンドを行っており、
上段の半導体素子５の電極パッド１３上に金属バンプを
形成する必要がないため、金属バンプを形成する工数を
削減できる。
【００３５】図４および図５は、本発明の第３の実施形
態を説明する図であり、図４は断面図、図５は部分的に
拡大した斜視図である。
【００３６】本実施形態において、図１および図２と同
一の構成要件には同一の符号が付けられている。
【００３７】本実施形態では、下段の半導体素子３の電
極パッド３１上に金属バンプ３２が形成されており、下
段の半導体素子３の電極パッド３１と絶縁基板１の導電
パターン６とを接続する導電ワイヤ３３は、ファースト
ボンドが導電パターン６で、セカンドボンドが金属バン
プ３２でそれぞれ行われている。
【００３８】上段の半導体素子５の電極パッド３４には
金属バンプ３５が形成されており、上段の半導体素子５
の電極パッド３４と下段の半導体素子３の電極パッド３
１とは、ファーストボンドが導電ワイヤ３３上で行わ
れ、セカンドボンドが金属バンプ３５上で行われた導電
ワイヤ３６により接続される。
【００３９】第３の実施形態によれば、第１の半導体素
子３の電極パッド３１上において、同一個所に導電ワイ
ヤ３３のセカンドボンドと導電ワイヤ３６のファースト
ボンドとが重ねて行われるため、電極パッド３１の面積
を大きくせずに上段の半導体素子５、下段の半導体素子
３、絶縁基板１を接続することができる。
【００４０】また、下段の半導体素子３側でファースト
ボンドを、上段の半導体素子５側でセカンドボンドを行
って導電ワイヤ３６が形成されるため、半導体素子５上
における導電ワイヤ３６のループが低くなる。このた
め、上段の半導体素子５上の封止樹脂１９を薄くするこ
とができ、パッケージ全体としての薄型化を達成するこ
とができる。
【００４１】次に、図６を用いて本発明の第４の実施形
態を説明する。
【００４２】図６において、図１および図２と同一の構
成要件には同一の符号が付けられている。
【００４３】第４の実施形態では、下段の半導体素子３
の電極パッド４１上に金属バンプ４２が形成されてい
る。
【００４４】絶縁基板１と下段の半導体素子３とを接続
する導電ワイヤ４３は、ファーストボンドが導電パター
ン６で、セカンドボンドが金属バンプ４２で行われてい
る。
【００４５】下段の半導体素子３と上段の半導体素子５
とを接続する導電ワイヤ４６は、ファーストボンドが半
導体素子５の電極パッド４４で、セカンドボンドが導電
ワイヤ４３の接続された金属バンプ４２上で行われてい
る。
【００４６】本実施形態では、下段の半導体素子の電極
パッドに形成された金属バンプ上で導電ワイヤ４３およ
び導電ワイヤ４６の両方のセカンドボンドが行われてい
る。
【００４７】このため、本実施形態では、上段の半導体
素子の電極パッドに金属バンプを形成することなく上段
の半導体素子と下段の半導体素子、そして、下段の半導
体素子と絶縁基板とを接続することが可能となる。この
ため、金属バンプを形成する工数を削減することができ
る。
【００４８】本発明においては、絶縁基板上に半導体素
子を積層する実施例について説明したが、これに限ら
ず、一般に用いられるリードフレームを用いることも可
能である。リードフレームを用いる場合は、本発明にお
ける導電パターン６としてインナーリードが用いられ、
下段の半導体素子はダイパッドに固定される。
【００４９】
【発明の効果】本発明に係る半導体装置では、下段の半
導体素子の電極パッドを大きくし、絶縁基板と下段の半
導体素子とを接続する導電ワイヤと、下段の半導体素子
と上段の半導体素子とを接続する導電ワイヤとを、同一
のパッドの異なる領域に形成している。このため、下段
の半導体素子の電極パッドにおける導電ワイヤの接続を
確実に行うことができるとともに、ワイヤボンディング
により電極パッド下部に与えられるストレスを低減する
ことが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態における半導体装置の
断面図である。
【図２】本発明の第１の実施形態における半導体装置の
部分拡大斜視図である。
【図３】本発明の第２の実施形態における半導体装置の
部分拡大斜視図である。
【図４】本発明の第３の実施形態における半導体装置の
断面図である。
【図５】本発明の第３の実施形態における半導体装置の
部分拡大斜視図である。
【図６】本発明の第４の実施形態における半導体装置の
部分拡大斜視図である。
【符号の説明】
１ 絶縁基板 ２ 接着剤 ３ 半導体素子 ４ 接着剤 ５ 半導体素子 ６ 導電パターン ７ 導電パターン ８ ソルダレジスト ９ ソルダレジスト １０ 金属バンプ １１ 電極パッド １２ パッシベーション膜 １３ 電極パッド １４ パッシベーション膜 １５ 金属バンプ １６ 金属バンプ １７ 導電ワイヤ １８ 導電ワイヤ １９ 封止樹脂
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/60 ３０１

Claims (13)

    【特許請求の範囲】
  1. 【請求項１】 表面に配線パターンが形成された基板
    と、 前記基板上に搭載された、第１の電極パッドを備えた第
    １の半導体素子と、 前記第１の半導体素子上に搭載された、第２の電極パッ
    ドを備えた第２の半導体素子と、 前記第１の電極パッドの第１の領域と前記第２の電極パ
    ッドとを接続する第１のワイヤと、 前記第１の電極パッドの前記第１の領域を除く第２の領
    域と前記配線パターンとを接続する第２のワイヤと、 を含むことを特徴とする半導体装置。
  2. 【請求項２】 請求項１記載の半導体装置において、さ
    らに前記基板の裏面に形成された外部端子を含み、前記
    配線パターンと前記外部端子とは前記基板に設けられ
    た、前記基板の前記表面と前記裏面とを貫通する貫通孔
    を介して接続されることを特徴とする半導体装置。
  3. 【請求項３】 請求項１記載の半導体装置において、前
    記第１のワイヤはファーストボンドが前記第２の電極パ
    ッドに接続され、セカンドボンドが前記第１の電極パッ
    ドに接続され、前記セカンドボンドは前記第１の電極パ
    ッド上に形成されたバンプを介して前記第１の電極パッ
    ドに接続されることを特徴とする半導体装置。
  4. 【請求項４】 請求項１記載の半導体装置において、前
    記第１のワイヤはファーストボンドが前記第１の電極パ
    ッドに接続され、セカンドボンドが前記第２の電極パッ
    ドに接続され、前記セカンドボンドは前記第２の電極パ
    ッド上に形成されたバンプを介して前記第２の電極パッ
    ドに接続されることを特徴とする半導体装置。
  5. 【請求項５】 請求項１記載の半導体装置において、前
    記第１の電極パッドは、前記第１の半導体素子の周辺近
    傍に形成され、前記周辺の延在方向に長い形状を有して
    いることを特徴とする半導体装置。
  6. 【請求項６】 請求項１記載の半導体装置において、前
    記第１の電極パッドは、前記第１の半導体素子の周辺近
    傍に形成され、前記周辺と直交する方向に長い形状を有
    していることを特徴とする半導体装置。
  7. 【請求項７】 請求項１記載の半導体装置において、前
    記第１の半導体素子は前記第２の半導体素子よりも大き
    い外形形状を有することを特徴とする半導体装置。
  8. 【請求項８】 第１の電極パッドを有する第１の半導体
    素子と、 前記第１の半導体素子上に搭載された、第２の電極パッ
    ドを有する第２の半導体素子と、 内部電極と、 前記第１の電極パッドと前記第２の電極パッドとを接続
    する第１のワイヤと、 前記内部電極と前記第１の電極パッドとを接続する第２
    のワイヤと、を備え、 前記第１のワイヤと前記第２のワイヤとは前記第１の電
    極パッド上で重ならないように配置されることを特徴と
    する半導体装置。
  9. 【請求項９】 請求項８記載の半導体装置において、前
    記第１のワイヤと前記第２のワイヤとは、前記第１の電
    極パッド上で互いに離間してそれぞれ前記第１の電極パ
    ッドに接続されていることを特徴とする半導体装置。
  10. 【請求項１０】 第１の電極パッドを有する第１の半導
    体素子と、 前記第１の半導体素子上に搭載された、前記第１の電極
    パッドと接続された第２の電極パッドを有する第２の半
    導体素子と、 前記第１の電極パッドにおける前記第２の電極パッドと
    接続された領域とは異なる領域で前記第１の電極パッド
    と接続される内部電極と、 を含むことを特徴とする半導体装置。
  11. 【請求項１１】 第１の電極パッドを有する第１の半導
    体素子と、 前記第１の半導体素子上に搭載された、第２の電極パッ
    ドを有する第２の半導体素子と、 内部電極と、 前記第１の電極パッド上に形成された第１のバンプと、 前記第２の電極パッド上に形成された第２のバンプと、 前記内部電極でファーストボンドが行われ、セカンドボ
    ンドが前記第１のバンプ上で行われた第１のワイヤと、 前記第１のワイヤのセカンドボンド上でファーストボン
    ドが行われ、セカンドボンドが前記第２のバンプ上で行
    われた第２のワイヤとを含むことを特徴とする半導体装
    置。
  12. 【請求項１２】 請求項１１記載の半導体装置におい
    て、さらに基板を有し、前記内部電極は前記基板上に形
    成され、前記第１の半導体素子は前記基板上に搭載され
    ていることを特徴とする半導体装置。
  13. 【請求項１３】 請求項１２記載の半導体装置におい
    て、前記基板の前記内部電極が形成された面と反対側の
    面に外部電極が形成され、前記外部電極と前記内部電極
    とは前記基板に形成された貫通孔を介して互いに接続さ
    れていることを特徴とする半導体装置。
JP2000296328A 2000-09-28 2000-09-28 半導体装置 Expired - Fee Related JP3631120B2 (ja)

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US10/171,981 US6882056B2 (en) 2000-09-28 2002-06-17 Multi-chip package type semiconductor device
US11/540,754 US8053278B2 (en) 2000-09-28 2006-10-02 Multi-chip package type semiconductor device

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Cited By (15)

* Cited by examiner, † Cited by third party
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JP2005158767A (ja) * 2003-11-20 2005-06-16 Ibiden Co Ltd Ｉｃチップの接続構造およびｉｃチップ実装用基板
US7045899B2 (en) 2002-10-15 2006-05-16 Oki Electric Industry Co., Ltd. Semiconductor device and fabrication method of the same
US7064425B2 (en) 2002-02-19 2006-06-20 Seiko Epson Corporation Semiconductor device circuit board, and electronic equipment
WO2006101199A1 (ja) * 2005-03-24 2006-09-28 Sumitomo Bakelite Company, Ltd. エリア実装型半導体装置並びにそれに用いるダイボンド用樹脂組成物、及び封止用樹脂組成物
US7132752B2 (en) 2003-10-31 2006-11-07 Oki Electric Industry Co., Ltd. Semiconductor chip and semiconductor device including lamination of semiconductor chips
CN1296998C (zh) * 2002-06-27 2007-01-24 富士通株式会社 半导体器件、半导体封装以及用于测试半导体器件的方法
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