JP2002109836A - Device and method for adjusting phase - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for adjusting phase in which a phase deviation (a phase difference) between clocks (clock information) and MO signals (data information) is precisely detected even though clock jitter is large and phase adjustment of the clocks is conducted with high precision. SOLUTION: The device is provided with a phase detecting circuit 8 which detects phase deviation between the clocks and the MO signals read from an optical disk 1, a controller 12 which obtains a means value of the phase deviation between the clocks and the MO signals from plural detected values obtained by the circuit 8 and generates control signals from the mean value for the phase adjustment of the clocks and a delay circuit 11 which adjusts the phase of the clocks based on the control signals generated by the controller 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjusting device and a phase adjusting method for an optical disk device, and more particularly to a phase adjusting device and a phase adjusting method capable of performing a highly accurate phase adjustment.

[0002]

2. Description of the Related Art In recent years, as various types of information such as image information and audio information have been digitized, the amount of digital information has increased dramatically. Along with this, development of optical disk devices suitable for large capacity and high density has been promoted.

However, with the progress of high density,
The signal quality of a reproduced signal is degraded, and various ideas have been devised to obtain good signal quality. In the reproduction signal, in addition to main information such as images and sounds, servo information and various controls,
Contains management information. Among them, clock information is one of the most important information because it serves as a reference for operating various circuits for recording and reproducing all information.

For example, Japanese Patent Application Laid-Open No. H11-16216 discloses an optical disk and an optical disk apparatus capable of improving the signal quality of the clock information and reading the clock information without error.

Hereinafter, a conventional optical disk and an optical disk apparatus will be described.

First, the format of the optical disk will be described. Normally, an optical disc is divided into a plurality of zones in the radial direction, and one zone includes a plurality of tracks. Further, one track is composed of a plurality of sectors. In the same zone, the number of sectors per track is constant. Sectors having the same sector number are arranged at the same circumferential position on the optical disk.

FIG. 4A shows an example of a sector configuration of an optical disk. One sector is divided into 46 segments. Each segment has an address segment (A
S) and a data segment (DS). Here, AS0 at the head of the sector is an address segment, and DS0 to DS44 are data segments.

FIG. 4B shows the structure of an address segment. In the address segment, a clock mark area (CM field), an address area (Address field), and the like are arranged, and a predetermined signal is recorded in each area in advance by a change in the shape of a pit or groove.

The clock mark area is an area in which a clock mark for obtaining a clock signal is recorded in advance as described above. The address area is an area in which the address of a sector is recorded. Other areas are appropriately arranged for controlling address reading or for securing a reading margin.

FIG. 4C shows the structure of a data segment. The data segment includes a clock mark area (CM file) at the beginning of the segment, similarly to the address segment.
ld) is located. The other area is a data area (Data field), and the main information can be recorded and reproduced by, for example, magneto-optical recording.

Each segment length is, for example, 63.5 bytes, and clock marks are arranged at regular intervals of 63.5 bytes.

Next, the clock mark will be described.
FIG. 5A shows a portion around a clock mark of a disk.

As a clock mark, as shown in FIG. 5A, a convex portion is provided in a groove, a concave portion is provided in a land, and a change in light amount occurs when a laser spot moves in a track tangential direction. It has become. That is, the clock mark is detected as a differential signal of two photodetectors, that is, a tangential push-pull (TPP) signal, using the photodetector divided into two along the track (tangential direction).

FIG. 5B shows a change in the TPP signal.
If this TPP signal is binarized by, for example, a zero cross comparator, a periodic clock signal can be detected.

In the above description, since the clock signal is detected based on the clock mark, parameters such as the shape of the clock mark can be set independently of the main information to be magneto-optically recorded. Further, since the tangential push-pull signal is used, a clock signal independent of the tracking control state can be detected as compared with the case where the push-pull signal is used. As a result, signal quality can be improved.

Therefore, as compared with the case where clock information is recorded by so-called wobble in which the side wall of the track groove is meandering, the clock can be reproduced with a shorter mark length, and the density can be increased.

Next, the phase adjustment will be described. As described above, when the clock information is recorded as pits and the data information is recorded by magneto-optical recording, a shift occurs between the clock phase and the data phase.

One of the causes of the phase shift is considered to be a delay time required for a signal to propagate through a circuit. That is, it is considered that the difference between the clock phase and the data phase is caused by a delay in a signal processing circuit for reproducing a clock mark and generating a clock, a laser driving circuit for recording, and a magnetic head driving circuit.

Another cause is considered to be a change in recording power on the recording film surface. That is, it is considered that the difference between the clock phase and the data phase occurs when the size of the recording bit changes due to the fluctuation of the recording power. This is shown in FIG. It can be seen from FIG. 6 that when the recording power is small, the recording bit is small, and when the recording power is large, the recording bit is large. Here, for example, if the end of the recording bit is detected during data reproduction, the difference in the position of the end of the recording bit appears as a phase variation.

Of the two causes of the above-mentioned difference between the clock phase and the data phase, the delay time of the circuit is almost constant, so that there is no problem if the initial adjustment is made in the manufacturing process of the device.

However, the second variation of the recording power caused by the above-mentioned cause is explained by APC (Auto Power Control).
Even if the output power of the objective lens is kept constant, the warp of the disk causes distortion of the light spot shape on the recording film surface, and as a result, the effective recording power on the recording film surface decreases. Fluctuations occur. Usually, the state of the warp of a disk differs from disk to disk, and cannot be solved by initial adjustment of the apparatus.

Therefore, a phase shift between the clock phase and the data phase is detected to correct the phase. A recording pattern for detecting the phase of this data is periodically recorded in the data area. Since the area for recording the phase detection pattern is an area in which data cannot be recorded and reproduced, it is desirable to arrange the intervals widely. On the other hand, if the interval between the phase detection areas is too large, the phase is adjusted in a certain area. Also, the phase shift may increase before reaching the next phase detection area. Therefore, it is necessary to provide the phase detection regions at appropriate intervals. Here, it is assumed that the phase detection area is arranged for each sector, and the position is set immediately after the address segment.

Next, a phase adjusting method will be described.
FIG. 7 is a configuration diagram showing a main part of a recording / reproducing signal processing portion of a generally used optical disc device.

In the optical disk device shown in FIG. 7, the optical disk 101 is rotated by a spindle motor 102. There are various types of optical disks 101, but here, a description will be given as a magneto-optical disk.

The optical disk 101 is irradiated with a light beam from below through an objective lens 103 provided on a pickup 104. The intensity of the light beam differs between the time of reproduction and the time of recording, and is controlled by the LD drive circuit 105 so as to have an appropriate intensity.

The light reflected from the optical disk 101 is detected by a photodetector (not shown) installed inside the pickup 104. The reflected light is separated into a TPP signal, a magneto-optical signal (MO signal) and other signals.

The TPP signal is binarized by a clock generation circuit 109, and a bit clock is generated by a PLL circuit 110 based on the binarization. Although only one clock mark signal per segment is detected from the TPP signal as described above, the PLL circuit 110 generates a bit clock with an appropriate magnification. Here, since 63.5 bytes are used per segment, 508 (63.5 bytes × 8
) Is generated. The generated bit clock is supplied to the delay circuit 111.

On the other hand, the amplitude and offset of the MO signal are adjusted by the RF circuit 106 and converted into digital data by the A / D converter 107. As the clock of the A / D converter 107, a bit clock whose phase has been adjusted by the delay circuit 111 is used. The output of the A / D converter 107 is supplied to a demodulation circuit (not shown) and is also transmitted to a phase detection circuit 108.

The phase detection circuit 108 detects the amount of phase shift between the clock and the MO signal from the phase detection pattern included in the MO signal, and transmits the detection result to the controller 112. Based on this, the controller 112 instructs the delay circuit 111 to obtain a predetermined delay amount.

FIGS. 8A to 8D show the relationship between the phase of the clock and the MO signal when the segment on which the phase adjustment pattern is recorded is reproduced.

FIGS. 8A and 8B show the relationship between the MO signal and the clock in a state where the phase has been correctly adjusted. FIG. 8A shows an MO signal, and a black circle on the MO signal waveform indicates a sampling point of the A / D converter 107. FIG. 8B shows a clock, and sampling of the A / D converter 107 is performed at the rise of the clock.

FIGS. 8C and 8D show the relationship between the MO signal and the clock when the phase of the clock is advanced with respect to the MO signal. What is obtained as the output of the A / D converter 107 is the amplitude information of the MO signal at the sampling point. Based on the difference in the amplitude at the sampling point between FIG. 8A and FIG. The phase shift is detected by the phase detection circuit 108.

When the controller 112 shown in FIG. 7 detects that the phase of the clock is advanced by the phase detection circuit 108, it instructs the delay circuit 111 to delay the phase of the clock by the detected amount of phase advance. . Conversely, when the phase of the clock is delayed, an instruction is given to the delay circuit 111 to advance the phase of the clock.

As described above, by detecting the phase shift between the clock and the MO signal and adjusting the phase of the clock based on the detection result, the phase of the clock can always be optimized with respect to the phase of the MO signal. Becomes possible.

[0035]

However, in the above-described phase adjustment method, the phase shift between the clock and the MO signal is detected, and the phase shift of the clock is adjusted based on the detection result. In order to perform the detection with high accuracy, first, it is necessary that the phase can be detected with high accuracy. This phase detection accuracy is affected by the S / N of the MO signal and clock jitter.

Since the clock jitter is a temporal variation of the clock phase, the presence of the clock jitter causes a variation in the phase of the clock supplied to the A / D converter 107. That is, in addition to the phase fluctuation between the clock and the MO signal due to the fluctuation of the position of the end of the recording bit, the phase fluctuation due to the clock jitter is added.

Further, since the clock jitter is randomly generated without any correlation with the position of the clock mark, it leads to a decrease in phase detection accuracy.

Therefore, in the conventional phase adjusting apparatus and the conventional phase adjusting method, when the clock jitter is large as described above, the detection accuracy of the phase shift between the clock and the MO signal is reduced, and as a result, the accuracy of the phase adjustment is reduced. This causes a problem of lowering.

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to provide a method of precisely synchronizing a clock (clock information) and an MO signal (data information) even when clock jitter is large. Deviation (phase difference) can be detected,
Accordingly, it is an object of the present invention to provide a phase adjustment device and a phase adjustment method capable of adjusting a clock phase with high accuracy.

[0040]

According to the present invention, there is provided a phase adjusting apparatus for reading data from an optical disk having a clock area in which clock information is recorded and a data area in which data information is recorded. Phase detection means for detecting a phase shift between the clock information and the data information,
Calculating means for calculating a plurality of detection values obtained by the phase detecting means to generate a control signal for adjusting the phase of the clock information; and calculating the phase of the clock information based on the control signal generated by the calculating means. And adjusting means for adjusting.

According to the above configuration, a plurality of phase shifts between the clock information and the data information are detected, and the clock is generated based on the control signal for adjusting the phase of the clock information generated from the obtained plurality of detected values. Since the information phase is adjusted, the influence of clock jitter on the phase shift between the clock information and the data information can be reduced. Therefore, even if the phase of the clock information varies due to the clock jitter, the influence on the phase shift between the clock information and the data information can be reduced.

When calculating the average value of the phase shift between the clock information and the data information as the calculation of the plurality of detected values, for example, the phase shift between the clock information and the data information is calculated five times, and the average is calculated. When calculating the value, the variation in the phase of the clock information due to the clock jitter is reduced to 1 / √5.

Therefore, the influence of clock jitter on the phase shift between the clock information and the data information can be reduced, so that the phase shift between the clock information and the data information can be detected with high accuracy. Can be adjusted with high precision.

Therefore, a control signal for adjusting the phase of the clock information is generated based on the phase difference between the averaged clock information and the data information, and the phase of the clock information is adjusted based on the control signal. In addition, the phase of the clock information can always be set to an optimum state with respect to the phase of the data information.

The average value of the phase shift between the clock information and the data information may be obtained as follows.

That is, by the above-mentioned phase detecting means,
The phase shift between the clock information and the data information at the same circumferential position on the optical disk may be detected, and the arithmetic means may average the detected multiple phase shifts at the same circumferential position. .

For example, the warpage of an optical disc that greatly affects the phase shift between the clock information and the data information generally differs at each circumferential position, so that the phase shift also differs at each circumferential position. Therefore, it is desirable to detect the phase at the same circumferential position on the optical disc as described above.

However, the above-mentioned phase detection means
Detects a phase shift between clock information and data information in successive sectors in the same track of the optical disc, and averages the detected multiple phase shifts in successive sectors in the same track by the arithmetic means. You may make it.

As described above, in the averaging process, since the process is to reduce the random variation in the detected value, the effect of S / N can be reduced as in the case of the clock jitter.

In addition to averaging the detected values of the phase shift between the clock information and the data information, for example, when the number of detected values (number of elements) to be calculated is fixed,
It is not necessary to divide the sum of the detected values by the number of elements, and the same result as in the case of obtaining the average value can be obtained by adding each detected value.

For example, the average of 1, 2, 3 is (1 + 2 +
3) / 3 = 2, and the average of 2, 3, 4 is (2 + 3 +
4) / 3 = 3, but when the number of elements is fixed to 3, without dividing by the number of elements 3, 1 + 2 + 3 = 6, 2 + 3 + 4 = 9, and even if these values are used, the above-mentioned average value They are only tripled.

Therefore, when a control signal for adjusting the phase of the clock information is generated, even if the number of elements is fixed and each element is added as described above, the result is substantially the same as the case where the average value is used. .

[0053]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.

First, an optical disk device according to the present embodiment will be described. FIG. 1 is a configuration diagram showing a main part of an information recording / reproducing signal processing part of an optical disk device.

There are various types of optical disks. In this embodiment, a magneto-optical disk is used.
A case where clock information is recorded as pits and data information is recorded by magneto-optical recording will be described.

As shown in FIG. 1, the optical disk apparatus includes a spindle motor 2 for driving the optical disk 1 to rotate.
A pickup 4 for irradiating the optical disc 1 with laser light and receiving reflected light from the optical disc 1, and an LD drive circuit 5 for driving and controlling the pickup 4.

The optical disk 1 is irradiated with a light beam from below through an objective lens 3 provided on a pickup 4. The intensity of the light beam is different between the time of reproduction and the time of recording, and is controlled by the LD drive circuit 5 to have an appropriate intensity.

The reflected light from the optical disk 1 is detected by a photodetector provided inside the pickup 4, and separated into a magneto-optical signal (MO signal), a TPP signal, an address (ADR) signal and other signals.

The MO signal is mainly data information such as music and video recorded on the optical disk 1 and is output to the RF circuit 6 connected to the subsequent stage of the pickup 4. An A / D converter 7, a phase detection circuit (phase detection means) 8, and a controller (calculation means) 12 are connected to a stage subsequent to the RF circuit 6. That is, the MO signal is RF
The amplitude and offset are adjusted by the circuit 6 and converted into digital data by the A / D converter 7. The clock used for the timing adjustment and the like in the A / D converter 7 includes:
A bit clock (clock information) whose phase has been adjusted by a delay circuit (adjustment means) 11, which will be described later, is used.

The output of the A / D converter 7 is supplied to a demodulation circuit (not shown) and to a phase detection circuit 8.

The phase detection circuit 8 quantitatively detects the phase deviation from the clock from the phase detection pattern included in the MO signal, and uses the detection result as a phase detection value by the controller 1.
Tell 2

The phase detection value obtained by the phase detection circuit 8 is temporarily stored in a memory built in the controller 12, and after performing a predetermined operation, an instruction of the delay amount is sent to the delay circuit 11. Given. The storage state of the phase detection value in the memory will be described later.

The TPP signal is output to a clock extraction circuit 9 connected to the pickup 4. The PLL circuit 1 is provided after the clock extraction circuit 9.
0, the delay circuit 11 is connected. That is, the TPP signal is binarized by the clock extraction circuit 9 and a bit clock is generated by the PLL circuit 10 based on the binarization.

Although only one clock mark signal is detected per segment from the TPP signal as described above, the PLL circuit 10 generates a bit clock with an appropriate magnification. Here, since 63.5 bytes are used per segment, 508 (63.5 bytes × 8 bits) bit clocks are generated per segment.

The generated bit clock is supplied to the delay circuit 1
1 is supplied. In the delay circuit 11, the phase of the bit clock is adjusted based on a control signal from the controller 12, and the bit clock after the phase adjustment is output to the A / D converter 7.

That is, the delay circuit 11 adjusts the phase of the bit clock, which is clock information, based on the control signal (computation result) from the controller 12. The phase adjustment of the delay circuit 11 will be described later.

The ADR signal is output to a demodulation circuit 13 connected to the subsequent stage of the pickup 4. This ADR signal is demodulated by the demodulation circuit 13,
It becomes address information such as a zone number, a track number, and a sector number. The obtained address information is stored in the controller 1
It is conveyed to 2.

The controller 12 includes a phase detection circuit 8
A plurality of averages are obtained from a memory in which a phase detection value that quantitatively detects a phase shift between a clock and an MO signal from is stored, a progress of the clock signal is detected from the average value, and this detection result is obtained. The signal is output to the delay circuit 11 as a control signal.

For example, when the controller 12 detects that the phase of the clock is ahead of the phase of the MO signal based on the average value of the phase shift between the clock and the MO signal, the controller 12 determines the amount by the detected phase lead. A control signal for giving an instruction to the delay circuit 11 so as to delay the phase of the clock is output. Conversely, when detecting that the phase of the clock is delayed, a control signal that gives an instruction to the delay circuit 11 to advance the phase of the clock is output.

The delay circuit 11 adjusts the phase of the bit clock from the PLL circuit 10 according to a control signal from the controller 12. For example, in the delay circuit 11,
If the control signal from the controller 12 includes an instruction to delay the phase of the clock by a predetermined amount (corresponding to the amount of phase shift detected by the controller 12), the phase of the bit clock from the PLL circuit 10 is set to the above value. If the control signal from the controller 12 includes an instruction to advance the clock phase by a predetermined amount, the phase of the bit clock from the PLL circuit 10 is adjusted as described above. Adjust the phase to advance only the fixed amount.

Here, a method of adjusting the phase in the optical disk device having the above configuration will be described below with reference to FIGS. In this description, the controller 12
An average value obtained by performing a predetermined operation on a plurality of phase detection values stored in a memory inside the memory is used for phase adjustment.

FIG. 2 shows a state in which the phase detection value in a memory provided in the controller 12 shown in FIG. 1 is temporarily stored. In FIG. 2, the Y direction indicates a sector position, and the X direction indicates a track position. Here, the number of tracks used for the calculation is described as 5. N is the number of sectors per track. That is, the area (P) represented by the sector position and the track position of the memory shown in FIG.
(1, 1), P (1, 2),...) Quantitatively shows the phase shift between the clock and the MO signal at the sector position and the track position of the optical disk 1 corresponding to each of these areas. The value will be stored.

The processing flow of the phase adjustment method will be described below with reference to the flowchart shown in FIG.

First, prior to the reproducing operation, initialization is performed (step S1). The specific process of initialization is
The contents of the memory are all initialized, and the values of the X counter and the Y counter are set to 1 (X = 1, Y = 1). Further, the number of sectors N per track is obtained from the zone number obtained as the address information. As the memory initial value, a value that does not occur as an actual phase detection value is selected. Here, the initial value of the memory is 0, that is, P
Description will be made on the assumption that (X, Y) = 0. The X counter indicates the position of the memory in the X direction, and the Y counter indicates the position of the memory in the Y direction.

Next, reproduction is started (step S2).
If the reproduction operation is to be continued, the process proceeds to step S4; otherwise, the process ends (step S3).

In step S 4, the data information MO
The phase detection value obtained from the phase detection pattern after the addressing of the signal is stored in the memory as P (X, Y).

Next, P (1, 1) stored in the memory
Y), the average of the values of P (5, Y) is obtained, and the delay circuit 1
1 is instructed on the amount of delay (step S5). Here, in the calculation of the average value, the calculation is performed excluding the memory in which the initial value is stored. For example, if three out of five phase detection values of X from 1 to 5 remain at their initial values, the average of the remaining two is calculated.

Next, the value of the Y counter is incremented by 1 (step S6). And when the value of the Y counter is N or less,
Proceed to step S3; otherwise, proceed to step S8 (step S7).

In step S8, since the value of the Y counter exceeds N, the value of the Y counter is set to 1 and the value of the X counter is increased by 1. Since the fact that the Y counter has exceeded N indicates that the reproduction position has moved to a different subsequent track, the X counter is increased and the Y counter is returned to 1.

Subsequently, when the value of the X counter is 5 or less,
Proceed to step S3; otherwise, step S10
Go to (Step S9).

In step S10, the value of the X counter is set to 1
And returns to step S3.

As described above, in the present embodiment,
At the time of reproduction, the average value of the phase detection values at the same circumferential position of a plurality of tracks is always obtained, and the delay time is set based on the average value, so that the influence of clock jitter can be reduced.

Generally, since clock jitter occurs randomly, as shown in this embodiment, when averaging is performed five times, the variation in clock phase due to clock jitter is reduced to 1 / √5. You. Therefore, the greater the number of times of averaging the phase detection values, the greater the effect of reducing the influence of clock jitter. However, on the other hand, if an erroneous phase detection value is detected due to a defect or the like, the effect remains for a long time. Therefore,
The number of times of averaging the phase detection values is determined to be an appropriate value in consideration of these two points.

If the value of the phase detection value does not fall within the predetermined range in order to remove the influence of the defect, it is determined that an abnormal value has been detected due to a defect or the like, and is not stored in the memory. Instead, the initial value is stored. You may make it do. For the same purpose, the phase detection value outside the predetermined range may not be used for the calculation in the averaging calculation.

Specifically, in the controller 12,
If the phase detection value from the phase detection circuit 8 does not fall within the predetermined range, it is determined that the value is an abnormal value due to a defect or the like, and the initial value is stored in the storage area without storing the value in the memory. That is, the calculating means has a storage means for storing the detected value obtained by the phase detecting means, and determines whether or not the detected value falls within a predetermined range. If it does not fall within the predetermined range, it stores a preset initial value and, based on a plurality of detected values stored in the storage means, shifts the phase between clock information and data information. And a control signal for adjusting the phase of the clock information is generated from the average value.

Further, in the present embodiment, the average of the phase detection results at the same circumferential position of a plurality of tracks is obtained, but the average of the phase detection results at successive sectors in the same track may be obtained. However, the warpage of the disk, which greatly affects the phase shift between the clock and the MO signal, generally differs at each circumferential position, so that the phase shift also differs at each circumferential position. Therefore, it is desirable to take an average for each circumferential position of the disk as in the present embodiment.

In this embodiment, the position on the memory is designated by two counters of X and Y, but the track number and the sector number are obtained from the address information, and the phase detection result is stored based on the track number and the sector number. The memory location to be used may be determined. More specifically, the sector number is made to correspond to the value of the Y counter in the phase adjustment method described above, and the X counter is increased when the track number increases. In this way, the circumferential position can be obtained from the address information, and the memory position can be determined based on the circumferential position. It is possible to use the phase detection value at the circumferential position for the calculation.

As described above, according to the present invention, a plurality of phase detection values that quantitatively indicate the phase shift between the clock and the MO signal are detected, and the average value of these phase detection values is obtained. Since the clock phase is adjusted at the same time, the influence of clock jitter can be reduced, and an optical disk device capable of adjusting the clock phase with high precision can be realized.

As described above, in the averaging process, since the process is to reduce the random variation of the detection value, the influence of the S / N of the data information can be reduced as in the case of the clock jitter.

In addition to averaging the detected values of the phase shift between the clock information and the data information, for example, when the number of detected values (number of elements) to be calculated is fixed,
It is not necessary to divide the sum of the detected values by the number of elements, and the same result as in the case of obtaining the average value can be obtained by adding each detected value.

For example, the average of 1, 2, 3 is (1 + 2 +
3) / 3 = 2, and the average of 2, 3, 4 is (2 + 3 +
4) / 3 = 3, but when the number of elements is fixed to 3, 1 + 2 + 3 = 6, 2 + 3 + 4 = 9 without dividing by the number of elements, and even if these values are used, the above-mentioned average value They are only tripled.

Therefore, when a control signal for adjusting the phase of the clock information is generated, even if the number of elements is fixed and each element is added as described above, the result is substantially the same as the case where the average value is used. .

[0093]

As described above, according to the phase adjusting apparatus of the present invention, the clock information and the data information read from the optical disk having the clock area in which the clock information is recorded and the data area in which the data information is recorded are provided. Phase detecting means for detecting a phase shift of the clock information; calculating means for calculating a plurality of detection values obtained by the phase detecting means to generate a control signal for adjusting the phase of the clock information; Adjusting means for adjusting the phase of the clock information based on the control signal.

Therefore, a plurality of phase shifts between the clock information and the data information are detected, and the phase of the clock information is changed based on a control signal for adjusting the phase of the clock information generated from the plurality of obtained detection values. Since the adjustment is performed, the influence of clock jitter on the phase shift between the clock information and the data information can be reduced. Therefore, even if the phase of the clock information varies due to the clock jitter, the influence on the phase shift between the clock information and the data information can be reduced.

When calculating the average value of the phase shift between the clock information and the data information as the calculation of the plurality of detected values, for example, the phase shift between the clock information and the data information is calculated five times, and the average is calculated. When calculating the value, the variation in the phase of the clock information due to the clock jitter is reduced to 1 / √5.

Therefore, the influence of clock jitter on the phase shift between the clock information and the data information can be reduced, so that the phase shift between the clock information and the data information can be detected with high accuracy. Can be adjusted with high precision.

Accordingly, a control signal for adjusting the phase of the clock information is generated based on the phase shift between the averaged clock information and data information, and the phase of the clock information is adjusted based on the control signal. In addition, there is an effect that the phase of the clock information can always be made optimal with respect to the phase of the data information.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an optical disc device provided with a phase adjusting device of the present invention.

FIG. 2 is an explanatory diagram showing a data storage state of a phase detection value storage memory provided in the optical disk device shown in FIG.

FIG. 3 is a flowchart showing a process flow of a phase adjusting method by the phase adjusting device of the optical disk device shown in FIG. 1;

FIGS. 4A to 4C are explanatory diagrams showing the format of an optical disk.

FIGS. 5A and 5B are explanatory diagrams showing a reproduction signal of an optical disk.

FIG. 6 is an explanatory diagram showing the relationship between recording power and recording bits on an optical disc.

FIG. 7 is a schematic block diagram showing a general optical disk device.

FIGS. 8A to 8D are explanatory diagrams showing a phase relationship between a clock and an MO signal.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 optical disk 6 RF circuit 7 A / D converter 8 phase detection circuit (phase detection means) 9 clock extraction circuit 10 PLL circuit 11 delay circuit (adjustment means) 12 controller (calculation means) 13 demodulation circuit

Claims (4)

[Claims] 1. A phase detecting means for detecting a phase shift between clock information and data information read from an optical disk having a clock area in which clock information is recorded and a data area in which data information is recorded; Calculating means for calculating a plurality of detection values obtained by the detecting means to generate a control signal for adjusting the phase of the clock information; and adjusting the phase of the clock information based on the control signal generated by the calculating means. A phase adjusting device, comprising: an adjusting unit. 2. The phase detecting means detects a phase difference between the clock information and the data information at the same circumferential position on the optical disk, and the arithmetic means detects a plurality of phase shifts at the detected same circumferential position. 2. The phase adjusting device according to claim 1, wherein the deviation is averaged, and a control signal for adjusting the phase of the clock information is generated from the average value. 3. The phase detecting means detects a phase shift between clock information and data information in consecutive sectors in the same track of the optical disk, and the arithmetic means detects the detected consecutive data in the same track. 2. The phase adjustment device according to claim 1, wherein a plurality of phase shifts in the sector are averaged, and a control signal for adjusting the phase of the clock information is generated from the average value. 4. A first step of reproducing the optical disc to detect a plurality of phase shifts between clock information and data information, and calculating a plurality of phase shift detection values to adjust the phase of the clock information. A phase adjusting method, comprising: a second step of generating a control signal; and a third step of adjusting the phase of clock information based on the control signal obtained in the second step.