JP2002108510A - Reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of the unsteady state of a reset operation in a microcomputer even in a reset state at the cold start when power is sup plied. SOLUTION: When a low voltage detection flag 18 is outputted by a low voltage detecting circuit 17, an asynchronous outside reset signal 21 is selected by a reset signal selector 19 as a quasi system reset signal, and this is supplied to a microcomputer 10 as the system reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reset circuit, and more particularly to a reset circuit used for a semiconductor device having an internal system clock such as a microcomputer system.

[0002]

2. Description of the Related Art FIG. 7 shows an example of a reset circuit built in a conventional microcomputer. The reset circuit comprises an external reset signal inverter 52 connected to a reset terminal 51, and an oscillation circuit 5 whose operation is controlled by an oscillation control signal supplied to an oscillation control terminal 53.
4, a clock generator 55 for receiving a reference frequency signal from the oscillation circuit 54, and a reset signal synchronization circuit 56 to which the output of the inverter 52 and the clock generator 55 are supplied. A system clock 57 from a clock generator 55 and a system reset signal 58 from a reset signal synchronization circuit 56 are supplied to a microcomputer 59.

Although the reset circuit itself shown in FIG. 7 is actually a part of the microcomputer 59, a block composed of a CPU core, I / O ports, peripheral circuits and the like will be referred to as the microcomputer 59 for convenience of explanation. To

The operation of the conventional circuit will be described below with reference to FIGS.

As shown in FIG. 8A, when the power is turned on and the power supply voltage rises, the oscillation control signal supplied to the oscillation control terminal 57 becomes LOW as shown in FIG. 8C. Thus, the system clock 57 is not generated as shown in FIG.

In this state, an asynchronous external reset signal supplied from the outside is input from a reset terminal 51, passes through an inverter 52, adjusts the logic, and is supplied to a reset signal synchronizing circuit 56. At this time, since the system clock is not generated from the clock generator 55, the external reset signal is in an indefinite state A as shown in FIG. 8D, and the system reset signal is not supplied to the microcomputer 59.

To generate a proper system reset signal 58, a system clock 57 is required. However, as shown in FIG. 8, when the oscillation control terminal 53 is in a LOW (enable) state since power-on, the system clock is generated. Since the signal 57 is not generated, the normal system reset signal 58 is not generated, and the microcomputer 59 cannot be normally initialized as shown in FIGS. 8 (e) and 8 (f). Therefore, the I / O port of the microcomputer 59 is in an undefined state as shown in FIG.

[0008]

At this time, an I / O port, which should be used as an input port on the program of the microcomputer 59, may be fixed in an output state. As a result, a current path is formed between the / F circuit and the output collision state, and an unintended current flows. As a result, there is a possibility that peripheral circuits of the microcomputer may be damaged and power consumption may be increased.

Therefore, the present invention provides a reset circuit configured so that a reset operation does not unintentionally affect peripheral circuits of a microcomputer even when a system clock is not prepared, for example, when power is turned on. The purpose is to.

[0010]

A reset circuit according to the present invention includes a power supply voltage detection circuit for detecting a low voltage state of a power supply voltage and outputting a detection signal, a clock generation circuit having a function of generating and stopping a system clock. If the system clock is generated when the detection signal is output, an internal synchronous reset signal formed by synchronizing an asynchronous external reset signal with the system clock is selected as a system reset signal. And a reset signal selection output circuit for selecting the asynchronous external reset signal as the system reset signal when no is generated.

Further, according to the present invention, a power supply voltage detection circuit for detecting a low voltage state of a power supply voltage and outputting a detection signal, a clock generation circuit having a function of generating and stopping a system clock, If the system clock has been generated when it is output, an internal synchronous reset signal formed by synchronizing an asynchronous external reset signal with the system clock is selected as a system reset signal, and when the system clock is not generated Comprises a reset signal selection output circuit that selects the asynchronous external reset signal as the system reset signal, and a microcomputer that is reset by receiving a system reset signal from the reset signal selection output circuit. Is provided.

With this configuration, a pseudo system reset signal can be generated based on an external reset signal even when the system clock is not yet prepared, such as when the power is turned on. A reset circuit configured so that operation does not unintentionally affect peripheral circuits of the microcomputer can be provided.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 shows a block diagram of a reset circuit according to a first embodiment of the present invention. Although the reset circuit shown in FIG. 1 is actually built in the microcomputer 10, a reset circuit portion is separately shown for convenience of explanation. Therefore, the microcomputer 10 has a configuration including an I / O port and peripheral circuits in addition to the CPU core unit.

The reset circuit includes an external reset signal inverter 12 connected to a reset terminal 11, an oscillation circuit 14 whose operation is controlled by an oscillation control signal supplied to an oscillation control terminal 13, and an oscillation circuit 14. And a reset signal synchronizing circuit 16 to which the output of the inverter 12 and the clock generator 15 are supplied. Further, it has a low voltage detection circuit 17 for detecting a low voltage when the power is turned on or when the power supply voltage drops, and a reset signal selector 19 to which a low voltage detection flag 18 from the low voltage detection circuit 17 is supplied. The low voltage detection flag 1 from the low voltage detection circuit 17
8 is further supplied directly to the microcomputer 10. This low voltage detection flag 18 is used here for convenience.
Immediately after the power is turned on or when a low voltage is detected, "0",
During normal operation after the power is turned on, “1”, that is, HIG
H.

The oscillating circuit 14 includes, for example, a crystal oscillator 14A as an oscillating source, whereby a reference signal having a constant frequency is supplied to a clock generator 15.

The system clock 20 from the clock generator 15 is supplied to the microcomputer 10 and also to the reset signal synchronization circuit 16. An asynchronous external reset signal 21 is supplied from the inverter 12 to the reset signal synchronization circuit 16. This external reset signal 21 is also supplied to the reset signal selector 19.

The reset signal synchronizing circuit 16 outputs an internal synchronous reset signal 22 obtained by synchronizing an external reset signal with a system clock. This signal is selected by a reset signal selector 19 and supplied to the microcomputer 10 as a system reset signal 23. You.

The operation of the circuit according to the first embodiment will be described below with reference to FIGS.

As shown in FIG. 2A, when the power is turned on and the power supply voltage rises, the low voltage detection flag is set to the low voltage detection flag in FIG.
2C, the oscillation control signal supplied to the oscillation control terminal 13 is LOW as shown in FIG. 2D. Therefore, the system clock 20 is not generated as shown in FIG.

In this state, when an asynchronous external reset signal 21 is input from the outside from the reset terminal 11, the signal passes through the inverter 12 and is adjusted in logic, and then, as shown in FIG.
As shown in (e), the external reset signal 21 in the undefined state B
Is supplied to the reset signal synchronizing circuit 16.

However, at this time, since the system clock is not generated from the clock generator 15,
Internal synchronous reset signal 2 based on external reset signal 21
2 is not generated, and the microcomputer 10 is not supplied with the normal internal synchronization reset signal from the reset signal synchronization circuit 16.

On the other hand, the external reset signal 21 that has passed through the inverter 12 is input to the reset signal selector 19 together with the internal synchronous reset signal 22, and one of them is selected and supplied to the microcomputer 10 as a reset signal.

The signal selecting operation of the reset signal selector 19 is performed according to the contents of the low voltage detection flag 18 output from the low voltage detection circuit 17.

The operation of the low voltage detection circuit 17 is as follows.

First, as shown in FIG.
When turned on from F, the low voltage detection flag 18 is cleared to "0". The low voltage detection flag 18 is set to "1" at an arbitrary timing as needed by an application program of the microcomputer system.

When the power supply is turned on and the power supply voltage is set to "1", the power supply voltage drops and the low voltage detection circuit 17
The low-voltage detection flag is also cleared to "0" when the voltage falls below the predetermined voltage level set in.

Therefore, since the low voltage detection flag 18 is "0" immediately after the power is turned on (cold start state), the reset signal selector 19 operates as shown in FIG.
An external reset signal (asynchronous) 21 is selected as a system reset signal 23 and supplied to the microcomputer 10.

In this case, since the system reset signal 23 is supplied without using the reset signal synchronizing circuit 16, the oscillation control signal at the oscillation control terminal 13 is
As shown in FIG. 2H, the microcomputer 10 can be initialized even when the microcomputer 10 remains LOW as shown in FIG. 2D, that is, when the system clock 20 is not generated.
It is possible to prevent an unintended current due to a collision state of an output with an external I / F circuit, for example, an abnormal current between the CPU core unit, the peripheral circuit unit, and the I / O port unit.

When the low voltage detection flag is set to "1" as shown in FIG. 2C by the application program of the microcomputer system after the power is turned on, the system clock 20 has already been generated. Therefore, the internal synchronization reset signal 22 can be supplied to the microcomputer 10 as the system reset signal 23.

That is, when the low voltage detection flag is "1", the microcomputer 10 is synchronized with the conventional system clock at the time of hot start, such as when the microcomputer 10 has already been initialized once and then enters the standby state. It is also possible to set a reset timing. This state C is shown in the timing chart of FIG.

(2) Second Embodiment FIG. 3 is a block diagram showing a second embodiment of the present invention.

This second embodiment is similar to the first embodiment shown in FIG.
From the microcomputer 10 in the embodiment of FIG.
Only the portion where the O port 10B is separated and the CPU core and the peripheral circuit are left as the microcomputer 10A is different, and the circuit to which the system clock 20 and the system reset signal 23 are supplied is slightly different accordingly. Except for this point, the other parts have the same configuration as the circuit of FIG. 1, and corresponding parts are denoted by the same reference numerals, and detailed description thereof will be omitted.

That is, in FIG.
0 is I / O port 10B and microcomputer 10A
, And the system reset signal 22 is also supplied to the reset signal selector 19 together with the microcomputer 10A.
, So that the system reset signal 22 is also supplied to the I / O port 10B. Further, the low voltage detection flag 18 is supplied to the microcomputer 10A together with the reset signal selector 19.

The operation of the second embodiment will be described below with reference to FIGS.

The signal selection of the reset signal selector 19 is performed by the low voltage detection flag 18 output from the low voltage detection circuit 17, as in the embodiment of FIG.

In FIG. 4B, the system clock 2
When 0 is not generated, the system reset signal 22 is not generated in response to the external reset signal 21.
As shown in FIG. 4I, the microcomputer 10A including the CPU core unit and the peripheral circuit unit remains in an undefined state.

On the other hand, the reset signal selector 19 selects the external reset signal (asynchronous) 21 because the low voltage detection flag 18 is "0" immediately after the power is turned on (cold start state), as shown in FIG. And I / O port 10B
Port 10 as the system reset signal 23 for
B. As a result, as shown in FIG.
The / O port 10B is initialized normally and enters a normal operation state.

In this case, since the system reset signal 23 is supplied without using the reset signal synchronizing circuit 16, the oscillation control terminal 13 remains LOW as shown in FIG. 4D, that is, the system clock 20 is generated. The I / O port 10B can be initialized even when it is not in operation, and it is possible to prevent an unintended current or the like due to an output collision with an external I / F circuit.

When a predetermined time elapses after the power is turned on, the low voltage detection flag is set to "1" by an application program of the microcomputer system. In this case, the system reset signal (internal synchronous reset signal) 22 can be supplied to the I / O port 10B as the I / O port system reset signal 23.

As described above, in the second embodiment, the microcomputer 10A always performs initialization with the synchronized system reset signal (internal synchronous reset signal) 22 while maintaining the advantages of the first embodiment. This is effective for a microcomputer system in which a problem occurs if the reset timing of the microcomputer 10A is different in the state of the low voltage detection flag 18.

(3) Third Embodiment FIG. 5 shows a block diagram of still another embodiment. In this embodiment, a NOR circuit 19A and an O circuit are provided instead of the reset signal selector 19 in the second embodiment shown in FIG.
In addition to using a logic circuit composed of the R circuit 19B,
Since the configuration is the same as that of the embodiment of FIG. 3, the corresponding portions are denoted by the same reference numerals and detailed description thereof will be omitted.

The reset circuit according to the third embodiment is similar to the reset circuit shown in FIG.
Is a part of the microcomputer system similarly to the second embodiment, but for convenience of explanation, the I / O port 10
Blocks composed of a CPU core unit, a peripheral circuit unit, and the like except for B will be referred to as a microcomputer 10A.

The low voltage detection flag 18 from the low voltage detection circuit 17 is supplied to one input of the NOR circuit 19A.
The other input is supplied with an asynchronous external reset signal 21 from the reset terminal 11 on the input side of the inverter 12. The low voltage detection flag 18 is also supplied to the microcomputer 10A as in the embodiment of FIG.

The output of the NOR circuit 19A is the OR circuit 19B
, And a system reset signal 22 from the reset signal synchronizing circuit 16 is supplied to the other inverting input terminal of the OR circuit 19B. This system reset signal 22 is also supplied to the microcomputer 10A as in the embodiment of FIG.

Referring to FIGS. 5 and 6, the third
The operation of the embodiment will be described. An asynchronous external reset signal 21 supplied from the outside is input from a reset terminal 11 and supplied to one input terminal of a NOR circuit 19A. The reset signal passes through an inverter 12 for adjusting logic as necessary. The signal is supplied to the synchronization circuit 16.

Immediately after turning on the power supply shown in FIG. 6A, the oscillation control signal to the oscillation control terminal 13 is LOW as shown in FIG. 6 (b), the reset signal synchronizing circuit 16 does not operate, and the system reset signal is in an undefined state as shown in FIG. 6 (f). Therefore, the reset of the microcomputer 10A to which the system reset signal is supplied is also shown in FIG.
The state is undefined as shown in FIG.

On the other hand, the low voltage detection flag 18 is shown in FIG.
As shown in (1), the input is low immediately after the power is turned on, and one input of the NOR circuit 19A is low. At this time, FIG.
Until the external reset signal 21 of (f) becomes HIGH at the output side of the inverter 12, the input side of the inverter 12
That is, since the other input of the NOR circuit 19A is HIGH, the output of the NOR circuit 19A becomes LOW, and this becomes one input of the OR circuit 19B.

However, since the system clock 22, which is the other input of the OR circuit 19B, is not output, FIG.
The (g) I / O port system reset signal is undefined, and the I / O port 10B is also undefined as shown in FIG. 6 (h).

In this state, when the external reset signal 21 rises at the output side of the inverter 12 as shown in FIG. 6E, the input of the inverter 12, that is, the other input of the NOR circuit 19A becomes LOW, and the NOR circuit 19A The output becomes HIGH as shown in FIG. 6 (g), and I /
The O port system reset signal 23 is supplied to the I / O port 10B as a normal reset signal. At this time, the microcomputer 10A is still in an undefined state as shown in FIG.

As described above, the NOR circuit 19A, which is the I / O port system reset signal generation logic, uses the signal equivalent to the external reset signal (asynchronous) 12 as the I / O port system reset signal 23 as the I / O port system reset signal 23. 10
B.

In this case, since the system reset signal 23 is supplied without using the reset signal synchronizing circuit 16, even if the oscillation control terminal 13 remains LOW, that is, even if the system clock 20 is not generated, the I / O port 10B can be initialized, and an unintended current or the like due to a collision state of an output with an external I / F circuit can be prevented.

The low-voltage detection flag 1 is set according to an application program of the microcomputer system.
When 8 is set to “1”, the system reset signal (internal synchronous reset signal) 22 is converted into an I / O port system reset signal 23 via the OR circuit 19B.
It becomes possible to supply to the O port 10B.

Further, in the third embodiment, even when the low voltage detection flag 18 is LOW (“0”), the oscillation control terminal 1
If 3 is HIGH and the system clock 20 is supplied, the release of the I / O port system reset signal 23 can be performed in synchronization with the reset of the microcomputer 10A. This state E is shown in (f) and (g) of the timing chart of FIG.

That is, in the operation flow of the second embodiment shown in FIG. 4, the system reset signal 22 is changed from the external reset signal 21 shown in FIG.
As shown in FIG. 4F, the signal is released in synchronization with the fall of the next system clock. However, the I / O port system reset signal 23 becomes the external reset signal 2 as shown in FIG.
4 has been released in synchronization with the fall (release) of 1
(F) and (g) as shown in FIG.
And the reset release of the I / O port system reset signal 23 are not simultaneously started.

On the other hand, in the third embodiment,
As shown in FIGS. 6 (e), (f) and (g), first and second
If the system clock 20 is running while maintaining the merits of the embodiment, the low-voltage detection flag 18 becomes LOW.
(“0”), that is, the reset signals 22 and 23 simultaneously fall even in the cold start state, so that the reset of the microcomputer 10A and the I / O port 10B can be released in synchronization.

In the circuit of FIG. 5, the I / O port system reset signal 23 is supplied only to the I / O port 10B. It may be supplied to all circuits constituting the microcomputer system such as peripheral circuits at the same time. In this case, not only the I / O port 10B but also an abnormal current flowing inside the microcomputer 10A flowing to the CPU core, peripheral circuits, and the like can be suppressed.

[0058]

As described in detail above, according to the present invention,
When the power is turned on (cold start), the I / O port can be initialized without depending on the system clock, and there is no undefined state of the I / O port with respect to the asynchronous external reset signal. This is effective in preventing abnormal current due to output collision and protecting the system, and depending on the configuration of the circuit to be initialized, not only the I / O port but also the entire system can be initialized without the system clock. Immediately after the power is turned on, it is effective in suppressing static current consumption, and further, regardless of the state of the low-voltage detection circuit,
If there is a system clock, reset release can be synchronized, so that test resources can be diverted and a reset circuit and a microcomputer system that can facilitate testing can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the embodiment of FIG. 3;

FIG. 5 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the embodiment in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional reset circuit.

FIG. 8 is a timing chart for explaining the operation of the circuit in FIG. 7;

[Explanation of symbols]

 10, 10A: microcomputer, 10B: I / O port, 11: reset terminal, 12: inverter, 13: oscillation control terminal, 15: clock generator, 16: reset signal synchronization circuit, 17: low voltage detection circuit, 18 ... Low voltage detection flag, 19 ... Reset signal selector,

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroshi Tozawa 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture F-term (reference) 5B054 AA20 BB05 CC01 5B079 AA07 BA13 BA16 BB04 BC03 CC14 5J055 AX12 AX21 AX57 AX66 BX42 CX00 EY10 EZ07 EZ25 EZ28 EZ39 EZ51 GX02 GX04

Claims (7)

[Claims] A power supply voltage detection circuit for detecting a low voltage state of a power supply voltage and outputting a detection signal; a clock generation circuit having a function of generating and stopping a system clock; If the system clock has been generated, an asynchronous external reset signal is selected as the system reset signal by synchronizing the external reset signal with the system clock.If the system clock has not been generated, the asynchronous A reset signal selection output circuit that selects an external reset signal as the system reset signal. 2. An oscillation circuit for generating a reference frequency signal, oscillating and stopping the oscillation by an input to an oscillation control terminal, and the system clock based on the reference frequency signal from the oscillation circuit. 2. The reset circuit according to claim 1, further comprising: a clock generation circuit that generates a reset signal. 3. The reset signal selection output circuit includes: a NOR circuit to which an output of the power supply voltage detection circuit and an asynchronous external reset signal are supplied; a non-inverting input terminal to which an output of the NOR circuit is supplied; 3. The reset circuit according to claim 1, further comprising: an OR circuit having an inverting input terminal to which a system reset signal is supplied. 4. A power supply voltage detection circuit for detecting a low voltage state of a power supply voltage and outputting a detection signal, a clock generation circuit having a function of generating and stopping a system clock, and when the detection signal is output, If a system clock has been generated, an internal synchronous reset signal formed by synchronizing an asynchronous external reset signal with the system clock is selected as a system reset signal. A reset signal selection output circuit that selects a signal as the system reset signal; a microcomputer that is reset by receiving a system reset signal from the reset signal selection output circuit;
A microcomputer system comprising: 5. An oscillator circuit for generating a reference frequency signal, oscillating and stopping by input to an oscillation control terminal, and the system clock based on the reference frequency signal from the oscillating circuit. 5. The microcomputer system according to claim 4, further comprising: a clock generation circuit that generates a clock signal. 6. The microcomputer according to claim 4, wherein the microcomputer includes an I / O port, and a system reset signal output from the reset signal selection circuit is used as an initialization signal for the I / O port. 6. The microcomputer system according to 5. 7. The reset signal selection output circuit includes a NOR circuit to which an output of the power supply voltage detection circuit and an asynchronous external reset signal are supplied; a non-inverting input terminal to which an output of the NOR circuit is supplied; 7. The microcomputer system according to claim 6, further comprising: an OR circuit having an inverting input terminal to which a system reset signal is supplied.