JP2002076878A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Problem] Without reducing the amplitude time of an input signal,
Ensure sufficient setup time in the input buffer circuit. SOLUTION: An input buffer circuit 1 is provided with distributed delay adjusting units 2 to 4 for adjusting a delay time of an input signal. In the initial setting of the input buffer circuit 1, the delay time is set so that the setup time is about the middle between the maximum and the minimum. When the delay time is made shorter than the initial setting, the control signals CS1 to CS3 are set to the high level, the delay of the delay adjustment units 3 and 4 is not added, and the setup time is adjusted by adding only the delay time by the delay adjustment unit 2. I do. When the setup time is maximized, the control signals CS1 to CS3 are set to the low level, and the setup time is adjusted to the sum of the delay time due to the capacitance of the delay adjustment units 3 and 4 and the delay time by the delay adjustment unit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay adjustment technique for an input circuit, and more particularly to a technique effective when applied to delay adjustment in a clock synchronous input buffer circuit.

[0002]

2. Description of the Related Art According to studies made by the present inventor, various semiconductor integrated circuit devices such as microcomputers and synchronous SRAMs have a clock synchronous HSTL (High-Speed Tra) as an input buffer circuit.
In some cases, an input buffer circuit is used. This clock synchronous HSTL input buffer circuit receives an input signal having an amplitude of about ± several hundred mV with respect to a reference voltage.

The clock synchronous HSTL input buffer circuit includes a differential amplifier circuit for amplifying an input signal, and a latch circuit for latching a signal output from the differential amplifier circuit in synchronization with a clock signal.

A MOS (Metal Oxi) is provided between the differential amplifier circuit and the latch circuit as a delay adjusting element in order to satisfy the setup time of the latch circuit.
A capacitive load such as a deSemiconductor transistor is added.

[0005] As an example describing this type of semiconductor integrated circuit device in detail, see, for example, June 1, 1995.
Published by Impress Inc., Intel Japan (supervised),
There is “Introduction to Microprocessors by Illustration” P21, which describes the definition of setup time in a read cycle of a semiconductor integrated circuit device.

[0006]

However, the present inventor has found that the input buffer circuit of the semiconductor integrated circuit device as described above has the following problems.

That is, in the delay adjustment by the capacitive load, the rise / fall time of the signal (tr / tf)
If a certain amount of capacitive load is added, the amplitude will decrease significantly, and the clock signal may be reduced due to the parasitic capacitance of the clock signal wiring or the intermediate buffer that amplifies the clock signal. If the delay time becomes longer, there is a problem that delay adjustment cannot be performed.

An object of the present invention is to provide a semiconductor integrated circuit device which can ensure a sufficient setup time in an input buffer circuit without reducing the amplitude time of an input signal.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor integrated circuit device according to the present invention includes a differential amplifier for amplifying and outputting input low-amplitude data, latching the signal amplified by the differential amplifier,
A latch unit that outputs as full-amplitude data in synchronization with a clock signal, a first delay adjustment unit that is provided at a signal input unit of the differential amplifying unit and that delays and outputs input data by a certain time; Provided at a signal input portion of the latch portion,
An input buffer circuit including a second delay adjuster for delaying a signal output from the differential amplifier by a certain time and outputting the delayed signal is provided.

Further, a semiconductor integrated circuit device according to the present invention includes a differential amplifier for amplifying and outputting input low-amplitude data, a latch for the signal amplified by the differential amplifier, and a conversion to a clock signal. A latch unit that synchronously outputs data of all amplitudes, a capacitance element that is provided at a signal input unit of the differential amplification unit, delays input data by a certain time, and a capacitance element based on a control signal. A first delay adjusting section comprising a first switching section for controlling connection of the first and second sections; n capacitance elements provided at a signal input section of the latch section for delaying input data by an arbitrary time; A second delay adjusting unit comprising a second switching unit for controlling connection of the n capacitance elements based on the signal and varying a capacitance value added to a signal input unit of the latch unit; Input buffer circuit Those were.

Further, the semiconductor integrated circuit device of the present invention
A differential amplifying unit that amplifies and outputs input low-amplitude data, a latch unit that latches a signal amplified by the differential amplifying unit, and outputs the data as full-amplitude data in synchronization with a clock signal; A capacitive element provided at a signal input part of the differential amplifier and delaying input data by a certain time; and a first switching part configured to control connection of the capacitive element based on a control signal. One delay adjustment unit, n capacitance elements provided in a signal input unit of a latch unit, which delay input data by an arbitrary time, and connection of n capacitance elements based on a control signal A second delay adjusting section comprising a second switching section for performing control and varying a capacitance value added to a signal input section of the latch section, and between a signal input section of the latch section and the second delay adjusting section. Provided in
An input buffer circuit including a third delay adjustment unit including a differential amplifier circuit that delays input data by a certain time and outputs the delayed data is provided.

Further, the semiconductor integrated circuit device of the present invention provides a differential amplifier for amplifying and outputting input low-amplitude data, latches the signal amplified by the differential amplifier, and converts the amplified signal into a clock signal. A latch unit that synchronously outputs data of all amplitudes, n capacitance elements that are provided in a signal input unit of the latch unit, and that delay input data by an arbitrary time; a second delay adjusting unit including a second switching unit that controls connection of n capacitance elements and varies a capacitance value added to a signal input unit of the latch unit; N input resistors provided in the input section for delaying input data by an arbitrary time and outputting the data, and controlling connection of the n resistors based on a control signal, and adding the connection to the signal input section of the latch section The third switch that varies the input resistance value It is provided with a input buffer circuit and a fourth delay adjuster made more a quenching unit.

Further, the semiconductor integrated circuit device according to the present invention
A differential amplifying unit that amplifies and outputs input low-amplitude data, a latch unit that latches a signal amplified by the differential amplifying unit, and outputs the data as full-amplitude data in synchronization with a clock signal; And n connection control units that are provided at a signal input unit of the latch unit and delay the input data by an arbitrary time, based on a control signal. A second delay adjusting section comprising a second switching section for changing a capacitance value added to a signal input section of the latch section, and a second delay adjusting section provided between the signal input section of the latch section and the second delay adjusting section. A third delay adjustment unit including a differential amplifier circuit that delays and outputs input data by a certain time, and a signal input unit of the differential amplifier unit;
N resistances for delaying the input data by an arbitrary time and outputting, and connection control of the n resistances based on a control signal, and an input resistance value added to a signal input section of a latch section And a fourth delay adjusting section comprising a third switching section for changing the input buffer circuit.

As described above, since the delay time can be arbitrarily changed without significantly increasing the rise / fall time of the input data, the setup time in the latch section of the input buffer circuit can be optimally set. can do.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram of an input buffer circuit provided in a semiconductor integrated circuit device according to a first embodiment of the present invention.

In the first embodiment, the input buffer is provided in a semiconductor integrated circuit device having a synchronous operation, such as a synchronous SRAM, for example.
The input buffer captures input data at a predetermined timing.

As shown in FIG. 1, the input buffer circuit 1 of the input buffer includes delay adjusting units 2 to 4, a signal amplifying unit 5, and latch units 6 and 7. The delay adjustment unit (first delay adjustment unit) 2 is a P-channel MOS transistor (first switching unit) T
1 and a capacitance element C1.

One connection portion of the transistor T1 is connected so that data D _{IN as} an input signal is input. The data D _IN has a low amplitude input, and has a voltage amplitude of, for example, about ± 200 mV with respect to the reference voltage V _REF .

[0022] When the data D _IN is at the low level, becomes 200mV about a voltage lower than the reference voltage, the data D _IN
Is at a high level, the voltage is about 200 mV higher than the reference voltage.

The capacitance element C1 has an N-channel M
The transistor T1 is composed of an OS transistor, and the other connection of the transistor T1 is connected to one connection (gate of the transistor) of the capacitance element C1.

A reference potential V _SS is connected to the other connection portion (both connection portions of the transistors) of the capacitance element C1. The control signal CS is connected to the gate of the transistor T1.
1 is input.

The control signal CS1 is generated from a signal stored in a register provided in the semiconductor integrated circuit device, a signal input through an external terminal provided in the semiconductor integrated circuit device, or a fuse circuit. This signal controls ON / OFF of the transistor T1.

A signal amplifying unit 5 is connected to a stage subsequent to the delay adjusting unit 2. The signal amplifying unit 5 includes P-channel MOS transistors T2 to T4 and N-channel MOS transistors T5 to T9.

The power supply voltage V _CC is supplied to one connection of the transistor T2. The gate of the transistor T2 and one connection of the transistors T3 and T4 are connected to the other connection of the transistor T2.

The reference potential V _SS is connected to the gates of the transistors T3 and T4. The other connection of the transistor T3 is connected to one connection of the transistor T6 and the gate of the transistor T8. The reference voltage V _REF is supplied to the gate of the transistor T6.

The other connection of the transistor T4 is connected to one connection of the transistor T5 and the transistor T5.
7 gates are connected to each other. Transistor T
One connection of the transistor T1 is connected to the gate of No. 5.

The other connection of the transistor T5 is connected to the other connection of the transistor T6 and one of the transistors T7 and T8.
One connection of the transistor T9 is connected to the other connection of the transistors T7 and T8, and the reference potential V _SS is connected to the other connection.

The signal amplifying section 5 includes a transistor T2
To T9 constitute a differential amplifier circuit, which differentially amplifies the reference voltage V _REF and the input signal and outputs the result.

A delay adjuster (third delay adjuster) 3 is connected to the subsequent stage of the signal amplifier 5. The delay adjuster 3 includes an N-channel MOS transistor T
10 to T14.

One terminal of the transistor T6 is connected to the gate of the transistor T10. One terminal of the transistor T10 is connected to the transistor T1.
2 gates are connected.

At the other connection of the transistor T10,
The other connection part of the transistor T11, the transistor T1
2 and T13 are connected to each other.
One connection of the transistor T5 is connected to the gate of the transistor T11, and the gate of the transistor T13 is connected to one connection.

The other connection of the transistors T12 and T13 is connected to one connection of the transistor T14, and the other connection of the transistor T14 is connected to the reference potential V _SS .

The transistors T10 to T14 also constitute a differential amplifier circuit in the delay adjuster 3.

A delay adjustment unit (second delay adjustment unit) 4 is connected to the stage subsequent to the delay adjustment unit 3. The delay adjustment unit 4 includes P-channel MOS transistors (second switching units) T15 to T18 and capacitance elements C2 to C5. Capacitance element C2
C5 is formed of an N-channel MOS transistor like the above-mentioned capacitance element C1.

One connection of transistors T15 and T16 is connected to one connection of transistor T11, and one connection of transistors T16 and T17 is connected to one connection of transistor T10. ing.

The gates of the transistors T15 and T17 are connected to receive a control signal CS2, and the gates of the transistors T16 and T18 are connected to receive a control signal CS3.

Similarly to the control signal CS1, these control signals CS2 and CS3 are also input via a signal stored in a register provided in the semiconductor integrated circuit device and an external terminal provided in the semiconductor integrated circuit device. Signal, or a signal generated by a fuse circuit,
5 / T7 and transistors T6 and T8 are ON / O
Controls FF.

Here, in the capacitance elements C2 to C5, the capacitances of the capacitance elements C3 and C5 are respectively set so as to be twice the capacitance of the capacitance elements C2 and C4. I have.

The other connection portion of the transistors T15 to T17 is connected to one connection portion (gate of the transistor) of each of the capacitance elements C2 to C5, and the other of these capacitance elements C2 to C5. The connection portions (both connection portions of the transistors) are connected to the reference potential V _SS .

Further, a latch unit 6 is connected to a stage subsequent to the delay adjusting unit 4. The latch section 6 includes P-channel MOS transistors T19 to T24 and N-channel MOS transistors T25 to T27.

At one connection of the transistor T19,
One connection of the transistors T17 and T18 is connected, and one connection of the transistors T15 and T16 is connected to one connection of the transistor T20.

Transistors T19, T20, T23, T
The clock signal CLK supplied from the outside is supplied to the gates of T24 and T27. Also, the transistor T
The power supply voltage V _CC is supplied to one of the connection portions 21 to T24.

At the other connection of the transistor T19,
The other connection of the transistors T21 and T23, the gate of the transistor T22, and one connection of the transistor T25 are connected to each other.

At the other connection of the transistor T20,
Gates of transistors T21 and T25, transistor T
One connection portion of the transistor 26 and the other connection portion of the transistor T24 are connected to each other.

At the other connection of the transistor T25,
The other connection part of the transistor T26, the transistor T2
7 are connected to each other, and the other connection of the transistor T27 is connected to the reference potential V _SS .

The latch unit 7 is connected to a stage subsequent to the latch unit 6. The latch unit 7 includes inverters Iv1 to Iv1
v4 and a flip-flop circuit composed of NOR circuits NR1 and NR2.

The other connection of the transistor T23 is connected to the input of the inverter Iv1, and the other connection of the transistor T24 is connected to the input of the inverter Iv3.

The output of the inverter Iv1 is connected to one input of a NOR circuit NR1, and the output of the inverter Iv2 is connected to the other input of the NOR circuit NR1.

The output of the inverter Iv3 is connected to one input of the NOR circuit NR2, and the output of the inverter Iv4 is connected to the other input of the NOR circuit NR2. .

The output of the NOR circuit NR1 is connected to the input of the inverter Iv4, and the output of the NOR circuit NR2 is connected to the input of the inverter Iv2. Then, NOR circuits NR1, NR2
Are output from the input buffer circuit 1.

Next, the operation of the present embodiment will be described.

Here, in the input buffer circuit 1, the delay time is set as an initial setting so that the setup time is about halfway between the maximum and the minimum. In this initial setting, the control signals CS1 and CS3 are at a high level and the control signal C
S2 is at a low level.

These high-level control signals CS1, CS
3, the transistors T1, T15 and T17 are turned off
, And the capacitance by the capacitance elements C1, C2, C4 is not added.

On the other hand, since the transistors T16 and T18 are turned ON by the low-level control signal CS2, the capacitances of the capacitance elements C3 and C5 are added. Therefore, the setup time is initially set by the delay time due to the capacitance of the capacitance elements C3 and C5 and the delay time by the delay adjustment unit 2.

First, when making the delay time in the input buffer circuit 1 shorter than the initial setting, not only the control signals CS1 and CS3 but also the control signal CS2 is set to the high level.

These high-level control signals CS1 to CS
3, the transistors T1 and T15 to T18 are all turned off, so that the capacitance by the capacitance elements C1 to C5 is not added, and the setup time is adjusted only by the delay time by the delay adjustment unit 2.

When setting up the setup time in the input buffer circuit 1 longer than the initial setting, the control signals CS2 and CS3 are set to low level. The transistors T15 to T15 are controlled by low-level control signals CS2 and CS3.
18 are all ON, the capacitance by the capacitance elements C2 to C5 is added, and the setup time is adjusted by adding the delay time by the delay adjustment unit 2 to the delay time by the capacitance of the capacitance elements C2 to C5. Will be done.

Further, as described above, the capacitance ratio between the capacitance elements C2 and C4 and the capacitance elements C3 and C5 is
Since each is set to be 1: 2, three types of switching can be performed, and fine adjustment can be performed.

Although the capacitance ratio is set to be 1: 2 here, the number of capacitance elements is increased and the capacitance ratio is set to be 1: 2: 4 or more. The capacitance value may be set so as to increase every two times.

For example, when the capacitance ratio is set to 1: 2: 4 by controlling connection of six capacitance elements by three control signals, there are eight combinations ( (8 steps) can be switched, so that finer adjustments can be made.

In order to maximize the setup time in the input buffer circuit 1, the control signals CS1 to CS1
CS3 is all set to low level. The transistors T1 and T1 are controlled by these low-level control signals CS1 to CS3.
15 to T18 are all turned on, and the capacitance elements C1,
The delay time by the capacitances C2 to C5 and the setup time to which the delay time by the delay adjustment unit 2 is added are adjusted.

Here, the capacitance element C 1 is connected to the signal amplifying section 5.
Therefore, even if the time tf / tf of the data D _IN input by the capacitance of the capacitance element C1 becomes long, the signal amplified differentially from the signal amplifying unit 5 is output. In this case, a sufficient amplitude time can be secured. Further, the setting of the above-described delay time is adjusted so that the setup time is optimized in an electrical test such as a probe test.

Thus, according to the first embodiment, the delay time can be arbitrarily varied by the delay adjustment units 2 to 4, so that the setup time in the latch unit 6 of the input buffer circuit 1 can be reduced in a short time. It can be set optimally.

Also, the delay adjuster 2 is provided before the signal amplifying unit 5 and the delay adjusters 3 and 4 are provided separately after the signal amplifying unit 5 so that the tr / tf of the input data D _IN is increased. Since the time can be shortened, the delay time can be extended while securing a sufficient amplitude time of the data D _IN .

Further, in the first embodiment, the input buffer circuit 1 is provided with the three delay adjusters 2 to 4, but the input buffer may be provided with four or more delay adjusters. .

For example, FIG. 2 shows an input buffer circuit 1a provided with four delay adjusting sections. As shown in this figure, an input buffer circuit 1a has a delay adjustment unit (second delay adjustment unit) 4a and a signal amplification unit newly added to delay adjustment units 2 to 4 having the same circuit configuration as the first embodiment. 5
a is added.

The delay adjusting section 4a has the same circuit configuration as the delay adjusting section 4 in the first embodiment, and the signal amplifying section 5a includes the signal amplifying section 5 in the first embodiment.
It has the same circuit configuration as that of FIG.

The signal amplifying unit 5a is connected downstream of the delay adjusting unit 3, and the delay adjusting unit 4a is connected downstream of the signal amplifying unit 5a. Thus, the setup time in the latch section 6 of the input buffer circuit 1a can be made wider.

(Embodiment 2) FIG. 3 is a circuit diagram of an input buffer circuit provided in a semiconductor integrated circuit device according to Embodiment 2 of the present invention.

In the second embodiment, an input buffer circuit 1b which takes in input data at a predetermined timing
Is composed of delay adjusters 3 and 8, a signal amplifier 5a, and latches 6 and 7, as shown in FIG.

Delay adjusting section (fourth delay adjusting section) 8
Is composed of resistors R1 to R3. Signal amplifier 5
b is provided with a selector function.
OS transistors (third switching unit, fourth delay adjusting unit) T28 to T30, and N-channel MOS
Of transistors T31 to T41.

One connection of the resistor R1 is connected so as to input data D _{IN as} an input signal. The other connection of the resistor R1 is connected to one connection of the resistor R2 and The gate of the transistor T41 is connected.

The other connection of resistor R2 is connected to one connection of resistor R3 and the gate of transistor T40, and the other connection of resistor R3 is connected to the gate of transistor T39. ing.

One connection of the transistors T33 and T34 is connected to the other connection of the transistors T31 to T33. One connection of the transistors T31 to T33 is connected to the other connection of the transistors T36 to T38, respectively.

One connection of the transistors T36 to T38 is connected to the other connection of the transistor T30. The gates of these transistors T28 to T30 are connected so as to receive control signals CS4 to CS6, respectively.

These control signals CS4 to CS6 are signals stored in a register provided in the semiconductor integrated circuit device,
A signal input through an external terminal provided in the semiconductor integrated circuit device or a signal generated by a fuse circuit, and is used to turn on / off the transistors T28 to T30.
Controls FF. The circuit configurations and connection configurations of the delay adjustment unit 3 and the latch units 6 and 7 in the input buffer circuit 1b are the same as those in the first embodiment.

Next, the setting of the setup time in the input buffer circuit 1b will be described.

In this case as well, the delay time is set as an initial setting in the input buffer circuit 1b so that the setup time is about the middle between the maximum and the minimum, as in the first embodiment.

In this initial setting, control signals CS5 and CS
6 is at a high level, the control signal CS4 is at a low level, the transistors T37 and T38 are turned on, and the transistor T36 is turned off.

Therefore, the delay time due to the resistors R1 and R2 is added, and the setup time is set by the delay time and the delay time by the delay adjusting unit 3.

When the setup time is made shorter than the initial setting, the control signals CS4 and CS5 are set to low level, and only the control signal CS6 is set to high level. By the low level control signals CS4 and CS5, the transistor T
36 and T37 are turned off, and the high-level control signal CS6
This turns on the transistor T38.

Therefore, since the data D _IN is input to the signal amplifying unit 5b via only the resistor R1, the delay time is minimized by the smallest input resistance value, and the setup time can be set short. .

Further, when setting up the setup time in the input buffer circuit 1b longer than the initial setting, all the control signals CS4 to CS6 are set to the high level, and all the transistors T36 to T38 are turned on.

Therefore, the data D _IN includes all the resistors R1
Since the signal is input to the signal amplifying unit 5b through R3, the delay time is maximized by increasing the input resistance value, and the setup time can be set long.

Thus, also in the second embodiment,
The delay time can be arbitrarily adjusted by varying the input resistance value of the delay adjusting unit 8 by the signal amplifying unit 5b having a selector function, so that the setup time in the latch unit 6 of the input buffer circuit 1b can be optimized. Can be set.

The delay adjusting section 8 is connected to the signal amplifying section 5b.
Is provided before and after the signal amplifying unit 5 in a distributed manner, so that the input data D
_The delay time can be extended while ensuring a sufficient amplitude time of the data D _IN without increasing the tr / tf time of _IN .

Further, in the second embodiment, the case where the input resistance value is varied by the selector function provided in signal amplifying section 5b has been described.
As shown in (5), the input buffer circuit 1c may be configured so that the delay adjusting section (fourth delay adjusting section) 8a has a selector function.

In this case, the input buffer circuit 1c is composed of a signal amplifier 5, delay adjusters 3, 8a, and latches 6, 7, and the signal amplifier 5, delay adjuster 3, and latch 6 , 7 circuit connection configuration
This is the same as in the first embodiment.

The delay adjusting section 8a includes resistors R1 to R3,
And switching element (third switching unit) SW
1 to SW3. One connection of the resistor R1 is connected so that data D _{IN as} an input signal is input.

The other connecting portion of the resistor R1 has a resistor R
2 and one connection of the switching element SW3 are connected to each other. One connection of the resistor R3 and one connection of the switching element SW1 are connected to the other connection of the resistor R2.

The other connection of the resistor R3 is connected to one connection of the switching element SW2. The other connection of the switching elements SW1 to SW3 is connected to the gate of the transistor T5 of the signal amplification unit 5.

These switching elements SW1 to SW3
Are switching signals (control signals) SWS1 to SWS3
And the switching signals SWS1 to SWS
ON / OFF (conduction / non-conduction) is controlled by S3.

The switching signals SWS1 to SWS3 are
As in the first and second embodiments, the signal is a signal stored in a register provided in the semiconductor integrated circuit device, or a signal generated from an external terminal provided in the semiconductor integrated circuit device, a fuse circuit, or the like. .

In such a configuration, the switching elements SWS1 to SWS3 are used to switch the switching elements SW.
By controlling ON / OFF of 1 to SW3, the delay time can be arbitrarily adjusted, so that the setup time in the latch section 6 of the input buffer circuit 1c can be set optimally.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the first embodiment, the delay adjustment by the capacitance has been described, and in the second embodiment, the delay adjustment by the resistance has been described. However, as shown in FIG. Input buffer circuit 1 in combination with delay adjuster 8a using a resistor
d or the delay adjusting unit 8 (FIG. 3),
An input buffer circuit may be configured by combining the signal amplifying unit 5b (FIG. 3) provided with a selector function and the delay adjusting unit 4 (FIG. 1) using capacitance.

[0100]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the delay time can be arbitrarily changed without significantly increasing the rise / fall time of the input data, so that the setup time in the latch section of the input buffer circuit can be changed. Can be set optimally.

(2) According to the present invention, according to the above (1), the setup time can be easily and variably set by the control signal in a short time, so that it is not necessary to modify the mask used in the manufacturing process. The development period of the semiconductor integrated circuit device can be shortened and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input buffer circuit provided in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an input buffer circuit provided in a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of an input buffer circuit provided in a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of an input buffer circuit provided in a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 5 is a circuit diagram showing another example of an input buffer circuit provided in a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input buffer circuit 1a-1d Input buffer circuit 2 Delay adjuster (1st delay adjuster) 3 Delay adjuster (3rd delay adjuster) 4 Delay adjuster (2nd delay adjuster) 4a Delay adjuster (2nd) 5 signal amplifier 5a signal amplifier 5b signal amplifier 6,7 latch 8 delay adjuster (fourth delay adjuster) 8a delay adjuster (fourth delay adjuster) T1 transistor (first switching unit) ) T2-T4 transistor T5-T9 transistor T10-T14 transistor T15-T18 transistor (second switching unit) T19-T24 transistor T25-T27 transistor T28-T30 transistor (third switching unit,
Fourth delay adjustment unit) T31 to T41 Transistors C1 to C5 Capacitance elements SW1 to SW3 Switching unit (third switching unit) Iv1 to Iv4 Inverters NR1 and NR2 NAND circuit CS1 to CS6 Control signals SWS1 to SWS3 Switching signals ( Control signal)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J001 AA04 AA11 BB03 BB11 BB12 CC03 DD09 5J056 AA01 AA39 BB60 CC05 CC14 DD28 FF01 FF07 FF08 GG14

Claims (5)

[Claims] 1. A differential amplifier for amplifying and outputting input low-amplitude data, and a signal amplified by the differential amplifier is latched and output as full-amplitude data in synchronization with a clock signal. A first delay adjustment unit that is provided in a signal input unit of the differential amplification unit and that delays and outputs the input data by a certain time; and a first delay adjustment unit that is provided in a signal input unit of the latch unit. A semiconductor integrated circuit device, comprising: an input buffer circuit including a second delay adjuster that delays a signal output from the differential amplifier by a certain time and outputs the delayed signal. 2. A differential amplifier unit for amplifying and outputting input low-amplitude data, latching the signal amplified by the differential amplifier unit, and outputting the data as full-amplitude data in synchronization with a clock signal. A latch unit that is provided in a signal input unit of the differential amplifying unit, delays the input data by a certain time, and performs connection control of the capacitive element based on a control signal. First
A first delay adjustment unit including a switching unit; n capacitance elements provided at a signal input unit of the latch unit, for delaying the input data by an arbitrary time; a second switching unit configured to control connection of n capacitance elements and vary a capacitance value added to a signal input unit of the latch unit;
A semiconductor integrated circuit device provided with an input buffer circuit having a delay adjusting unit. 3. A differential amplifier for amplifying and outputting input low-amplitude data, latching the signal amplified by the differential amplifier, and outputting the data as full-amplitude data in synchronization with a clock signal. A latch unit that is provided in a signal input unit of the differential amplifying unit, delays the input data by a certain time, and performs connection control of the capacitive element based on a control signal. First
A first delay adjustment unit including a switching unit; n capacitance elements provided at a signal input unit of the latch unit, for delaying the input data by an arbitrary time; a second switching unit configured to control connection of n capacitance elements and vary a capacitance value added to a signal input unit of the latch unit;
A third delay adjustment unit that is provided between the delay adjustment unit and the signal input unit of the latch unit and the second delay adjustment unit and that delays the input data by a certain time and outputs the delayed data; A semiconductor integrated circuit device provided with an input buffer circuit comprising: 4. A differential amplifying unit for amplifying and outputting input low-amplitude data, latching a signal amplified by the differential amplifying unit, and outputting as a full-amplitude data in synchronization with a clock signal. A latch unit that is provided at a signal input unit of the latch unit and delays the input data by an arbitrary time; and the n capacitance devices based on a control signal. And a second switching unit for changing the capacitance value added to the signal input unit of the latch unit.
A delay adjusting unit, n resistors provided at a signal input unit of the differential amplifying unit for delaying the input data by an arbitrary time and outputting the data, and n resistors of the n resistors based on a control signal. A semiconductor circuit comprising: an input buffer circuit including a third switching unit configured to perform connection control and vary an input resistance value added to a signal input unit of the latch unit; Integrated circuit device. 5. A differential amplifying unit for amplifying and outputting input low-amplitude data, latching the signal amplified by the differential amplifying unit, and outputting the data as full-amplitude data in synchronization with a clock signal. A latch unit that is provided at a signal input unit of the latch unit and delays the input data by an arbitrary time; and the n capacitance devices based on a control signal. And a second switching unit for changing the capacitance value added to the signal input unit of the latch unit.
A third delay adjustment unit that is provided between the delay adjustment unit and the signal input unit of the latch unit and the second delay adjustment unit and that delays the input data by a certain time and outputs the delayed data; And n resistors provided at a signal input unit of the differential amplifying unit, for delaying the input data by an arbitrary time and outputting the data, and connection control of the n resistors based on a control signal. And a fourth delay adjusting section comprising a third switching section for changing an input resistance value added to a signal input section of the latch section, and a semiconductor integrated circuit provided with the input buffer circuit. apparatus.