JP2002064343A - Defferential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier circuit capable of being realized with a simple circuit configuration without distorting the output voltage and without causing crossover distortion even when input voltage approaches the VDD or VSS. SOLUTION: A differential couple is composed of depression type transistors MP11 and MP12, an active load is composed of enhancement transistors MN11 and MN12 and a current source is composed of an enhancement MP13. When the substrate effect coefficient of MP11 and MP12 is defined as B and the threshold voltage of MN11 and MN12 is defined as A, a threshold voltage Y of MP11 and MP12 is made -0.125<Y< (-0.875×A+0.675)×B-0.125}.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit capable of obtaining an output voltage without distortion even if an input voltage largely swings to a low potential side or a high potential side of a power supply. .

[0002]

2. Description of the Related Art In recent years, a battery has been generally used as an operating power supply of a portable electronic device, and its voltage has been decreasing due to weight reduction. Along with this, in order to efficiently use the power supply voltage of the circuit, it is necessary to increase the signal amplitude of the analog circuit particularly to both ends of the power supply voltage.

FIG. 14 shows a conventional general differential amplifier circuit 50.
FIG. 3 is a circuit diagram of an enhancement type PMOS transistor MP51, MP52, MP53, MP54, and an enhancement type NMOS transistor MN51, MN.
52 and MN53. The transistors MP51 and MP52 form a differential pair, the transistors MP53 and MP54 form a current source, and the transistors MN51 and MN52 form a differential pair transistor MP51.
A current mirror circuit as an active load of the MP 52 is configured. The transistors MN53 and MP54 form an output circuit. 51 is a non-inverting input terminal, 52 is an inverting input terminal,
53 is an output terminal and 54 is a bias terminal.

FIG. 15 shows operation waveforms of the differential amplifier circuit 50. The output terminal 53 and the inverting input terminal 52 are connected to form a voltage follower connection as shown in FIG. 7 shows waveforms of a voltage Vtail of a node TAIL, which is a common source of the differential pair transistors MP51 and MP52, and a voltage Vot of an output terminal 53 when an input signal Vin is applied to a terminal 51.

Referring to FIG. 15, when the input voltage Vin approaches the power supply voltage VDD, the voltage Vtail and the voltage Vot are clipped and distorted. This is because the input voltage Vin is equal to the power supply voltage V
When approaching DD, the differential pair transistors MP51 and MP5
2 the gate-source voltage Vgs of the transistor MP
Threshold voltages Vthp51 and Vthp52 of the differential pair transistors MP51 and MP52.
Is to cut off. Thus, in the differential amplifier circuit 50 of FIG. 14, when the input voltage Vin becomes close to the power supply voltage VDD, there is a problem that the output voltage Vot is distorted.

FIG. 16 is a circuit diagram showing another differential amplifier circuit 50 ', in which the differential pair of transistors MP51 and MP52 of the differential amplifier circuit 50 in FIG. 14 are replaced with depletion type PMOS transistors MP55 and MP56. Things. Others are the same as the differential amplifier circuit 50 of FIG.

However, in the differential amplifying circuit 50 ', the input terminal 52 is connected to the output terminal 53 to form a voltage follower connection, and when the voltage Vin is input to the input terminal 51, the input voltage Vin changes to the power supply voltage VDD. When approaching, the differential pair transistors MP55 and MP56 do not cut off, but when approaching the ground voltage VSS, the differential pair P5
5, MP56 is cut off, and the output waveform is clipped as shown in FIG. Thus, the output cannot be fully swung simply by making the differential pair transistors depletion type. FIG. 18 shows that the input voltage Vin is 0 V
FIG. 7 is a characteristic diagram of voltages Vtail, Vout, and Vot when the voltage is changed from V to 2V. As shown by 55, the voltage Vot rises only when the input voltage Vin becomes about 0.3V.

FIG. 19 shows a positive differential amplifier circuit 61 for preventing distortion on the power supply voltage VDD side and a negative differential amplifier circuit 62 for preventing distortion on the ground voltage VSS side in order to solve the above problems. Are independently configured, and both differential amplifier circuits 61 and 6
2 is a differential amplifier circuit 60 configured by connecting the input terminal and the output terminal of each of them in common. 63 and 64 are input terminals, 6
5 is an output terminal.

The positive differential amplifier 61 is an enhancement type PMOS transistor MP61, MP62, MP6.
3. Enhancement type NMOS transistor MN6
1, MN62 and a current source I61. Transistors MN61 and MN62 form a differential pair, and transistors MP61 and MP62 are the differential pair transistor MN6.
1, a current mirror circuit as an active load of MN62. The transistor MP63 forms an output circuit.

The negative differential amplifier circuit 62 includes enhancement type PMOS transistors MP64 and MP65, and enhancement type NMOS transistors MN63 and MN6.
4, MN65, and a current source I62. Transistors MP64 and MP65 form a differential pair, and transistors MN63 and MN64 are the differential pair transistor MP6.
4, a current mirror circuit as an active load of MP65 is formed. The transistor MN65 forms an output circuit.

In the differential amplifier circuit 60, the input terminal 63
Rises to near the power supply voltage VDD, the transistors MP64 and MP of the negative differential amplifier circuit 62
Although the differential pair at P65 is cut off, the output voltage Vot at the output terminal 64 is not distorted because the differential pair of the transistors MN61 and MN62 of the positive-side differential amplifier circuit 61 operates normally.

Conversely, when the voltage input to the input terminal 63 drops to near the ground voltage VSS, the positive differential amplifier 6
1, the differential pair of the transistors MN61 and MN62 is cut off.
Since the differential pair 64 and MP65 operate normally, the output voltage Vot of the output terminal 64 is not distorted. That is, even if the input voltage Vin becomes excessively large or small, the output voltage V
ot appears normally.

However, in this differential amplifier circuit 60, since the positive and negative differential amplifier circuits 61 and 62 are independent,
There is a problem that variation easily occurs between the two, and the production yield decreases. Further, since the positive differential amplifier 61 is cut off on the ground voltage VSS side and the negative differential amplifier 62 is cut off on the power supply voltage VDD, 66 and 6 in FIG.
As shown in FIG. 7, the output voltage has non-linear characteristics in the low input region of the positive differential amplifier circuit 61 and the high input region of the negative differential amplifier circuit 62. Note that Votp in FIG.
The output voltage Vont when the current source is connected to the drain of the transistor MN65 instead of the transistor MN65 is the transistor MN6
5 is an output voltage when a current source is connected to the drain of the transistor 5 instead of the transistor MP63. For this reason, as shown in FIG. 21, there is a problem that a discontinuous point 68 is generated and the output waveform is distorted.

FIG. 22 is a circuit diagram of another differential amplifier circuit 70. MP71, MP72, MP73 are enhancement type PMOS transistors, MN71, MN72, M
N73, MN74 and MN75 are enhancement type N
MOS transistors MN76 and MN77 are depletion type NMOS transistors. 71 is a non-inverting input terminal, 72 is an inverting input terminal, 73 is an output terminal, and 74 is a bias terminal.

The drains of the enhancement type differential pair transistors MN71 and MN72 are connected to a transistor MP7.
1, MP72, is connected to a current mirror circuit as an active load, each gate is commonly connected to input terminals 71, 72, and the source is a transistor MN as a current source.
74 are commonly connected.

The drains of the depletion type differential pair transistors MN71 and MN72 are connected to the transistor MN71.
The gates are connected to a current mirror circuit as an active load composed of P71 and MP72, the gates are also commonly connected to the input terminals 71 and 72, and the source is commonly connected to a transistor MN73 as a current source.

That is, the differential amplifier circuit 70 is obtained by connecting an enhancement-type differential pair and a depletion-type differential pair in parallel, and is described in Japanese Patent Application Laid-Open No. 8-256,026.

In the differential amplifier circuit 70, the enhancement-type differential pair transistors MN71 and MN72 are cut off when their threshold voltages Vthn71 and Vthn72 become lower than the threshold voltages Vthn71 and Vthn72 in the low voltage region of the voltage input to the input terminals 71 and 72. However, in the high voltage region, the operation is performed up to the power supply voltage VDD.
On the other hand, a depletion-type differential pair transistor MN7
6, MN77 has an input voltage whose threshold voltage Vthn7
6. Up to Vthn77, they operate in the same manner as the enhancement type differential pair transistors MN71 and MN72. (Vthn7
6, Vthn77) << (Vthn71, Vthn72), so the depletion type differential pair transistors MN76, MN77
Are enhancement type differential pair transistors MN71, MN
It operates up to the low voltage region from N72. That is, the enhancement type differential pair transistors MN71 and MN72 operate to cover the high voltage region of the input voltage, and the depletion type differential pair transistors MN76 and MN77 operate to cover the low voltage region of the input voltage.

However, since the source potential of the depletion type differential pair transistors MN76 and MN77 cannot be made lower than the drain voltage of the current source transistor MN73, when the input voltage becomes the ground voltage VSS, it is cut off and operates. Becomes discontinuous.

FIG. 23 is a circuit diagram of another differential amplifier circuit 80. MP81, MP82 and MP83 are enhancement type PMOS transistors, and MN81 and MN82 are enhancement type NMOS transistors. SW
Is a switch, 81 is a non-inverting input terminal, and 82 is an inverting input terminal. The output circuit is omitted.

This differential amplifier circuit 80 is disclosed in
No. 756, the substrate voltage of the differential pair transistors MP81 and MP82 is switched by a switch SW to change the operation range. Here, if the switch SW is switched to the terminal a1, the substrate potential becomes the source potential. If the threshold voltage at this time is Vthp8-1, the substrate potential when the switch is switched to the terminal a1 becomes the power supply voltage VDD. , The threshold voltage increases to Vthp8-2 (> Vthp8-1). Therefore, when the input voltage changes in a region close to the power supply voltage VDD, the switch SW is switched to the terminal a1 to set the threshold voltage to Vthp8-1, and when the input voltage changes in a region close to the ground voltage VSS. Switch to terminal a2 to set threshold voltage to Vth
By setting p8-2, the dynamic range can be widened.

However, when the input voltage is near the power supply voltage VDD, the differential pair transistors MP81 and MP82 are cut off and do not operate.

[0023]

As described above, FIG.
When the input voltage approaches the power supply voltage VDD in the differential amplifier circuit 50 of FIG. 23 and the differential amplifier circuit 80 of FIG. 23, the output voltage is clipped and distorted, and the differential amplifier circuit 50 ′ of FIG. 16 and the differential amplifier circuit of FIG. In 70, there is a problem that the output voltage is clipped and distorted when the input voltage approaches the ground voltage VSS. In the differential amplifier circuit 60 shown in FIG.
Although there is no problem as in the case of 50 ', there is a problem that the circuit configuration is complicated and crossover distortion is easily generated.

The present invention has been made in view of the above points, and an object of the present invention is to prevent the output voltage from being distorted even when the input voltage approaches VDD or VSS, and to cause no crossover distortion. An object of the present invention is to provide a differential amplifier circuit that can be realized by a simple circuit.

[0025]

According to a first aspect of the present invention, there is provided a depletion-type first and second MOS transistor of a first conductivity type which are differentially connected to each other. An enhancement-type third and fourth MOS transistor having a drain connected to the drain of the second MOS transistor and having a second conductivity type opposite to the first conductivity type and being current mirror-connected to each other; , A drain connected to a common source of the second MOS transistor, a fifth MOS transistor of an enhancement type and a first conductivity type as a current source.
Assuming that the substrate effect coefficient of the MOS transistor is B and the threshold voltage of the third and fourth MOS transistors is A, the threshold voltage Y of the first and second MOS transistors is 0 < When A, -0.125 <Y <{(-0.875 × A + 0.675) × B−0.125)} When A <0, {(0.875 × A−0.675) × B + 0.125)} <Y <0.125 It was constituted so that it might become.

According to a second aspect of the present invention, in the first aspect, a plurality of sets of the first and second MOS transistors are provided, and a source of each set of MOS transistors is connected to a drain of the fifth MOS transistor. And the drain of one of the MOS transistors in each set is individually connected to the third MOS transistor via a fuse or a switch.
And the drains of the other MOS transistors are individually connected commonly to the fourth transistor via fuses or switches.

[0027]

FIG. 1 is a diagram showing a differential amplifier circuit 10 for explaining the principle of the present invention. In FIG.
11, MP12, MP13 and MP14 are PMOS transistors, and MN11, MN12 and MN13 are NMOS transistors. The transistors MP11 and MP12 are of a depletion type forming a differential pair, and their substrates are connected to a power supply voltage VDD line. Other transistors are enhancement type. Transistor MP1
Reference numeral 3 denotes a current source, and transistors MN11 and MN12
Constitutes a current mirror circuit as an active load. The transistors MP14 and MN13 form an output circuit.

As described above, in the present invention, the substrates of the differential pair transistors MP11 and MP12 are connected not to the source but to the line of the power supply voltage VDD, and the differential pair transistors MP11 and MP12 are made to function as a depletion type. The “depression type” here means
Threshold voltage is -0.6V like enhancement type
Rather, it refers to a transistor that exhibits a negative or positive voltage near 0 V. That is, it is assumed that the threshold voltage does not show the normal normally-on characteristics but has a small value with the same polarity as that of the enhancement type.

FIG. 2 shows a connection relationship for a characteristic test of the differential amplifier circuit, in which an inverting input terminal and an output terminal are connected to form a voltage follower, a voltage is input to a non-inverting input terminal, and a voltage is applied to an output terminal. Measure the characteristics of the appearing voltage.

When the input voltage Vin to be input to the non-inverting input terminal 11 is changed from the ground voltage VSS to the power supply voltage VDD while the differential amplifier circuit 10 of FIG. Is the input voltage V
It can be said that the operation is ideal if it changes at the same potential as in.
However, conventionally, as described above, the input voltage cannot be tracked in a region close to the power supply voltage VDD due to various factors,
Similarly, in a region close to the ground voltage VSS, the tracking cannot be performed, and distortion occurs.

FIGS. 3 and 4 show the input / output characteristics. The horizontal axis represents the voltage Vin input to the non-inverting input terminal 11, the vertical axis represents the voltage Vout at the node OUT, the voltage Vtail at the node TAIL, and the output terminal. 13 is the voltage Vot.

First, FIG. 3 shows the threshold voltages Vthp11 and Vthp11 of the depletion type differential pair transistors MP11 and MP12.
This is a characteristic when Vthp12 becomes a value close to the enhancement type (a large value on the negative side: -0.3 V).
In comparison with the vicinity of VSS and the vicinity of VDD, the changes of the voltages Vout, Vtail, and Vot near the VSS are smooth, whereas the changes near the VDD greatly change as indicated by reference numeral 15, and the voltage Vout becomes VSS. Therefore, the voltage Vot is V
Stick to DD. This is because the input voltage Vin is VD
This is because the MP12 cuts off on the D side.

FIG. 4 shows the threshold voltages Vthp11 and Vthp1 of the depletion type differential pair transistors MP11 and MP12.
When the input voltage Vin is close to VSS and close to VDD, the characteristics when the deeper depletion type (0.2 V) is applied to the input voltage Vin are closer to VDD.
While the change of Vot is smooth, it largely changes near VSS, as indicated by reference numeral 16, and the voltage Vot is stuck to VDD, and the voltage Vout is also insufficient. this is,
This is because if the voltage of the node OX is the voltage Vox, the relationship of Vthn11 <Vox <Vtail (1) cannot be maintained when the input voltage Vin is around VSS. Note that Vthn11
Is the threshold voltage of MN11.

Therefore, the threshold voltage Vthn11 of the transistor MN11 may be reduced or the voltage Vtail may be increased within a range in which the expression (1) is satisfied. It was impossible.

As described above, the differential pair transistor MP1
1. It was not possible to widen the input / output operating range from VSS to VDD only by reducing the threshold voltages Vthp11 and Vthp12 of MP12 to depletion type. If the threshold voltages Vthp11 and Vthp12 are confined to a very narrow range, there is a possibility. However, this yields a very low yield in an actual production site and is not practical. It is expected that the controllability of the threshold voltage will be significantly improved in the future due to the progress of technology, but at present, a variation of about ± 150 mV of the intended value cannot be avoided.

Therefore, the present invention focuses on the relationship between another parameter and the threshold voltage which have not been considered in the past, and
An object of the present invention is to realize a differential amplifier circuit capable of continuously operating in the entire range of S to VDD.

FIG. 5 shows the differential amplifier circuit 10 of FIG.
FIG. 9 is a diagram illustrating a change in voltage Vtail in each case where the substrate effect coefficient B is set to B = 0.7, 1.3, and 1.9. As the value of the body effect coefficient B increases, the voltage Vtail increases
You can see that it moves away from t. That is, Vox in equation (1)
It can be seen that the difference between the threshold voltage Vthn11 and the threshold voltage Vthn11 increases.

FIG. 6 is a diagram for explaining the substrate effect of a single PMOS transistor MP. This shows a change in the drain current Ids when the gate voltage Vg is changed from 2V (= VDD) to 0V (= VSS).
The substrate voltage Vsb applied to the substrate of the MOS transistor is V
This is for each case of changing from DD + 0V to VDD + 2.5V at 0.5V pitch. As apparent from FIG. 6, as the substrate voltage Vsb increases, the apparent threshold voltage increases.

Regarding the substrate effect, reference materials such as “Submicron Device I, Mitsumasa Koyanagi, Maruzen” and “CMO
S. R. Jacob Baker, et al IEEE Press "and the like. According to these, the substrate effect coefficient B is represented by B = √ (2 × Es × Eo × q × Na) / Cox (2) Es is the relative dielectric constant of silicon, Eo is the dielectric constant of vacuum, Na is the impurity concentration of the substrate, and Cox is the capacitance of the insulating oxide film below the gate electrode.

At present, many FET calculation models have been proposed, and the substrate effect is expressed by a complicated equation for accurate reproduction of the characteristics. However, the substrate potential is changed to change the threshold voltage. The point at which the change is observed is always the same, and in each case, characteristics similar to those in FIG. 6 can be obtained. The formula
According to (2), it is found that the substrate effect coefficient B can be changed by changing the impurity concentration Na and the oxide film thickness. If the impurity concentration Na is doubled, the substrate effect coefficient B can be doubled. As described above, the substrate effect coefficient B and, consequently, the threshold voltage can be changed by adjusting the impurity concentration Na and the like.

FIG. 7 shows the substrate effect coefficient B of the differential pair transistors MP11 and MP12 in the differential amplifier circuit 10 of FIG.
FIG. 5 is a characteristic diagram showing changes in threshold voltages Vthp11 and Vthp12 (hereinafter, referred to as Y) with respect to the threshold voltages Vthn11 and Vt of transistors MN11 and MN12 on the load side.
hn12 (hereinafter, referred to as A) when variously changed. Note that VDD = 2V and VSS = 0V.

First, the range in which the circuit makes a full swing when A = 0.5 V is the area of the hatched portion a between the limit line 15 and the limit 16. The limit line 15 is Y = −0.125 (3) The limit line 16 is Y = 0.2375 × B−0.125 (4) These are obtained by regression analysis of many measurement data and simulation results, are graphed, further expressed by mathematical expressions, and generalized.

Next, the range in which the circuit makes a full swing when A = 0.4 V is the area of the hatched portions a and b between the limit line 15 and the limit 17. The limit line 17 is Y = 0.325 × B−0.125 (5).

The range where the circuit makes a full swing when A = 0.2 V is the area of hatched portions a, b and c between the limit line 15 and the limit 18. The limit line 18 is as follows: Y = 0.5 × B−0.125 (6)

The hatched portions a, b, and c indicating the full swing range have the substrate effect coefficient B in the range of 1.0 ≦ B ≦ 2.2 (7). It is decided and not limited to this.

In summary, the depletion type P
By setting the threshold voltage Y of the MOS differential pair transistors MP11 and MP12 in the range of −0.125 <Y <{(− 0.875 × A + 0.675) × B−0.125} (8) The voltage Vin is changed from VSS to
When a full swing is made to VDD, an output voltage Vot without distortion corresponding to the full swing can be obtained.

As described above, the range of the threshold voltage Y depends on the threshold voltage A of the load side transistors MN11 and MN12.
And the substrate effect coefficient B, it can be set within a fairly wide range, so that it can be easily realized.

The above is the case of the differential amplifier circuit in which the differential pair transistors are depletion type PMOS transistors MP11 and MP12. However, as shown in FIG. 8, the differential pair transistors have depletion type PMOS transistors MP11 and MP12. Differential amplifier circuit 20 using NMOS transistors
A similar idea applies to In FIG.
MP21, MP22 and MP23 are enhancement type PMOS transistors, MN21 and MN22 are depletion type NMOS transistors, and MN23 and MN24.
Is an enhancement type NMOS transistor.

FIG. 9 is a characteristic diagram showing the full swing range at that time. The differential pair transistors MN21 and MN
The threshold voltages Vthn21 and Vthn22 of Y.22 are Y ', and the threshold voltages Vthp2 of the load transistors MP21 and MP22.
1, when Vthp22 is A ′ of the same value, in this differential amplifier circuit, the limit line 25 is Y ′ = 0.125 (9) When A ′ = − 0.5V, the limit line 26 is Y ′ = − 0.2375 × B + 0.125 (10) The limit line 27 when A ′ = 0.4 V is as follows: Y ′ = − 0.325 × B + 0.125 (11) A The limit line 28 when '= −0.2 V is represented by Y ′ = − 0.5 × B + 0.125 (12).

To summarize the above, the depletion type N
By setting the threshold voltage Y ′ of the MOS differential pair transistors MN21 and MN22 in the range of {(0.875 × A′−0.675) × B + 0.125} <Y ′ <0.125 (13) Input voltage Vin from VSS
When a full swing is made to VDD, an output voltage Vot without distortion corresponding to the full swing can be obtained. The range of the substrate effect coefficient B is the range represented by the equation (7).

FIG. 10 is a block diagram showing the configuration of a differential amplifier circuit according to an embodiment suitable for actual manufacture. The differential amplifier circuit 100 shown in FIG. 10A is a depletion type PMOS transistor as a differential transistor. For use, the differential amplifier circuit 200 shown in FIG.
This is for the case where a MOS transistor is used.

In FIG. 10A, 101 is a current source, 1
02 is a differential pair transistor group composed of a plurality of depletion type differential pair PMOS transistors, 103 is a selecting means for selecting a transistor to be used from the differential pair transistor group 102, 104 is a load composed of a current mirror, 105, 105 106 is a differential input terminal, and the output circuit is omitted.

Here, the substrate effect coefficients B are formed so as to be different from each other within the range of the equation (7) for each differential pair transistor in the differential pair transistor group 102. The setting of the substrate effect coefficient B is performed by slightly varying the substrate concentration just below the gate oxide film of each transistor for each differential pair transistor.

In FIG. 10B, 201 is a current source, 2
02, a differential pair transistor group composed of a plurality of depletion type differential pair NMOS transistors; 203, a selection unit for selecting a transistor to be used from the differential pair transistor group 202; 204, a load composed of a current mirror circuit; , 206 are differential input terminals, and the output circuit is omitted.

Also in this case, the substrate effect coefficients B are made different from each other within the range of the equation (7) for each differential pair transistor in the differential pair transistor group 202. The setting of the substrate effect coefficient B is also performed by making the substrate concentration immediately below the gate oxide film of the transistor slightly different for each differential pair transistor.

FIG. 11 is a circuit diagram of a differential amplifier circuit 100 that embodies the configuration of FIG. The current source 101 is an enhancement type PMOS transistor MP101.
The differential pair transistor group 102 is a depletion type PM
OS transistors MP102, MP103, MP10
4, MP105, MP106, and MP107. Further, the selection means 103 includes the differential pair transistor group 10
Fuses H102, H103, H10 individually connected to the drains of the two transistors MP102 to MP107.
4, H105, H106 and H107. The load 104 includes enhancement-type NMOS transistors MN101 and MN102. FIG. 10 (a)
Similarly, the output circuit is omitted.

Adjustment of the substrate concentration of each of the transistors MP102 to MP107 of the differential pair transistor group 102 is performed by two-stage impurity implantation. The first impurity implantation is common to the transistors MP102 to MP107, and is different for each pair of transistors at the time of the second impurity implantation.
Thus, for example, the density of the differential pair of MP102 and MP107 is N1, the density of the differential pair of MP103 and MP106 is N2, and the density of the differential pair of MP104 and MP105 is N3.
Set as follows. For example, N1 <N2 <N3.

Then, the differential amplifier circuit 100 is connected by a voltage follower connection as shown in FIG.
, The change in the output voltage of the output circuit (not shown) when the voltage Vin is input and changed in the range of VSS to VDD is observed, and the differential pair having the least waveform distortion of the output voltage is left. The other differential pair is disconnected from the circuit by cutting the fuse.

More specifically, when there is distortion on the VSS side, transistors having a strong depletion tendency due to the threshold voltage being on the positive side, that is, transistors MP102, MP103, MP106 and MP107 having densities of N1 and N2.
Fuses H102, H103, H10
6, H107 are cut off, leaving only the transistor pair MP104 and MP105 with the concentration of N3. Conversely, if there is distortion on the VDD side, on the other hand, transistors having a strong threshold voltage and a strong enhancement tendency on the negative side, that is, transistors MP103 and MP10 having concentrations of N2 and N3.
4, MP105, fuse H to separate MP106
103, H104, H105, and H106 are cut off, leaving only the transistor pair MP102 and MP107 with the concentration of N1.

FIG. 12 shows the differential amplifier circuit 10 shown in FIG.
0 shows a circuit 100 ′ according to a modification example, in which the selecting means 103 is provided with analog switches S 102, S 103 and S 10
4, S105, S106 and S107, and the on / off of these switches is controlled by the selector 107, so that a set of analog switches S102 and S107, S103 and S107
Only one of the set 106 or the set of S104 and S105 is turned on.

As described above, the differential amplifier circuit 10 shown in FIG.
0 'enables the analog switches S102 to S107 to be turned on / off externally at the use stage, not at the manufacturing stage, and the selection in the manufacturing process can be omitted.

FIG. 13 is a circuit diagram of a differential amplifier circuit 200 that embodies the configuration of FIG. The current source 201 is an enhancement type NMOS transistor MN201.
The differential pair transistor group 202 is a depletion type NM
OS transistors MN202, MN203, MN20
4, MN205, MN206 and MN207. Further, the selection means 203 is provided for the differential pair transistor group 20.
, The analog switches S202, S203, respectively connected to the drains of the two transistors MN202 to MN207.
It comprises S204, S205, S206, and S207. The load 204 is composed of enhancement type PMOS transistors MP201 and MP202. FIG.
The output circuit is omitted as in (b). 207 is a selector.

Also in this case, each transistor MN2 of the differential pair
Adjustment of the substrate concentration of 02 to MN 207 is performed by two-stage impurity implantation.

In FIGS. 12 and 13 described above, the number of differential pair transistors is three, but at least two pairs of threshold voltage adjustments are provided because the accuracy is about ± 150 mV as described above. Just do it.

[0065]

As described above, according to the differential amplifier circuit of the present invention, even if the input voltage approaches VDD or VSS, the output voltage is not distorted, no crossover distortion occurs, and the circuit can be realized with a simple circuit. become able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential amplifier circuit for explaining the principle of the present invention.

FIG. 2 is a connection explanatory diagram of a voltage follower for measurement.

FIG. 3 shows a differential pair transistor MP11,
FIG. 14 is a characteristic diagram of voltages Vtail, Vout, and Vot with respect to a change in input voltage Vin when the threshold voltage of MP12 is −0.3 V.

FIG. 4 shows a differential pair transistor MP11,
Input voltage V when the threshold voltage of MP12 is 0.2V
FIG. 9 is a characteristic diagram of voltages Vtail, Vout, and Vot with respect to in change.

FIG. 5 shows a differential pair transistor MP11,
FIG. 9 is a characteristic diagram of voltages Vtail, Vout, and Vot with respect to a change in input voltage Vin at each substrate effect coefficient B of MP12.

FIG. 6 is a characteristic diagram of the source / drain current Ids when the gate voltage Vg is changed at each substrate voltage Vsb of the PMOS transistor.

FIG. 7 shows an active load transistor MN1 of the circuit of FIG.
7 is a characteristic diagram of the threshold voltage Y of the transistors MP11 and MP12 with respect to the body effect B of the differential pair transistors MP11 and MP12 at the respective threshold voltages A of MN1 and MN12.

FIG. 8 is a circuit diagram of a differential amplifier circuit in which the polarity of each transistor in the circuit of FIG. 1 is inverted.

FIG. 9 shows an active load transistor MN2 of the circuit of FIG. 8;
7 is a characteristic diagram of the threshold voltage Y ′ of the transistors MN21 and MN22 with respect to the body effect B of the differential pair transistors MN21 and MN22 at the respective threshold voltages A ′ of MP1 and MP22.

FIGS. 10A and 10B are block diagrams of a differential amplifier circuit according to an embodiment of the present invention.

FIG. 11 is a specific circuit diagram of the differential amplifier circuit of FIG.

FIG. 12 is another specific circuit diagram of the differential amplifier circuit of FIG.

FIG. 13 is a specific circuit diagram of the differential amplifier circuit of FIG.

FIG. 14 is a circuit diagram of a conventional differential amplifier circuit.

15 is a waveform diagram of voltages Vtail and Vot when an input voltage Vin is input to the differential amplifier circuit of FIG.

FIG. 16 is a circuit diagram of another conventional differential amplifier circuit.

17 is a waveform diagram of a voltage Vot when an input voltage Vin is input to the differential amplifier circuit of FIG.

FIG. 18 is a characteristic diagram of voltages Vtail, Vout, and Vot when an input voltage Vin is input to the differential amplifier circuit of FIG.

FIG. 19 is a circuit diagram of another conventional differential amplifier circuit.

20 shows voltages Vtail-p, Vtail-n, Voutp, and Vou when input voltage Vin is input to the differential amplifier circuit of FIG.
It is a characteristic diagram of tn, Votp, Vont.

21 is a waveform chart of an output voltage Vot of the differential amplifier circuit of FIG.

FIG. 22 is a circuit diagram of another conventional differential amplifier circuit.

FIG. 23 is a circuit diagram of another conventional differential amplifier circuit.

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tetsuo Omori 2-1-1 Fukuoka, Kamifukuoka-shi, Saitama F-term in Kawagoe Works, Nippon Radio Co., Ltd. 5J066 AA01 AA12 CA21 CA24 FA16 FA18 HA10 HA14 HA15 HA16 HA17 HA38 HA39 HA49 KA00 KA05 KA09 MA05 MA19 MA22 ND01 ND14 ND22 ND23 PD01 TA01 TA02 TA06 5J090 AA01 AA12 CA21 CA24 FA16 FA18 GN01 HA10 HA14 HA15 HA16 HA17 HA38 HA39 HA49 KA00 KA05 KA09 MA05 TA02 TA06

Claims (2)

[Claims] A first conductive type and depletion type first and second MOS transistor which are differentially connected;
An enhancement-type third and fourth MOS transistor having a drain connected to the drain of the second MOS transistor and having a second conductivity type opposite to the first conductivity type and being current mirror-connected to each other; , The second M
A drain connected to a common source of the OS transistor, a fifth MOS transistor of an enhancement type and a first conductivity type as a current source, wherein a substrate effect coefficient of the first and second MOS transistors is B; When the threshold voltage of the third and fourth MOS transistors is A, the threshold voltage Y of the first and second MOS transistors is: -0.125 <Y <{ (−0.875 × A + 0.675) × B−0.125)} When A <0, the differential amplifier circuit satisfies {(0.875 × A−0.675) × B + 0.125)} <Y <0.125. . 2. The device according to claim 1, wherein a plurality of sets of the first and second MOS transistors are provided, and a source of each set of MOS transistors is commonly connected to a drain of the fifth MOS transistor.
The drains of one MOS transistor of each set of MOS transistors are individually connected to the third transistor via a fuse or a switch, and the other MOS transistor is connected to the other MOS transistor.
A differential amplifier circuit, wherein drains of transistors are individually connected to the fourth transistor via a fuse or a switch.