JP2002055730A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor whose camera part is allowed to function even when current consumption is suppressed. SOLUTION: This information processor is provided with a driving processing part 30 for controlling the clock frequencies of a reference clock to be used by an image pickup part 11 for its operation according to a power source situation and a CPU (not shown in a figure) in a main body part 20 of a personal computer for controlling the processing of various data including processing based on a video signal obtained by the image pickup part 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus such as a personal computer, and more particularly, to an information processing apparatus such as a personal computer with an imaging unit.

[0002]

2. Description of the Related Art In recent years, a personal computer having a built-in camera unit (image pickup unit) or a personal computer to which a camera device can be connected has been provided. As such a personal computer, there is a so-called notebook-type personal computer which is usually driven by a battery. For example, such a notebook personal computer can output a camera image captured by a camera unit to an image output unit such as an LCD (liquid crystal display).

A notebook personal computer having such a built-in camera unit (image pickup unit) or a notebook personal computer to which a camera can be connected is provided regardless of the power supply status such as battery power drive or AC power drive (AC adapter drive). The camera unit is driven at an operating frequency at which the operation of the camera unit is obtained as the highest performance.

[0004]

By the way, since the amount of current consumption of the camera unit is not changed even when the remaining battery power is low in the battery power operation, that is, the operation is performed irrespective of the state of the remaining battery power. In such a case, when the camera unit is used, there is a serious problem that the battery runs down immediately or the camera unit cannot be used.

The present invention has been made in view of the above circumstances, and has as its object to provide an information processing apparatus capable of causing a camera unit to function while suppressing current consumption.

[0006]

In order to solve the above-mentioned problems, an information processing apparatus according to the present invention controls a clock frequency of a reference clock used for operation of an image pickup means according to a power supply condition. Clock control means is provided.

An information processing apparatus having such a configuration is:
The power consumption is changed by controlling the clock frequency of the reference clock used by the imaging means for operation by the clock control means according to the power supply status.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. In this embodiment, the present invention is applied to a so-called built-in camera type notebook personal computer (hereinafter, simply referred to as a personal computer) having a built-in camera unit (imaging device).

In a personal computer having a camera unit according to an embodiment, a microcomputer for controlling the camera unit and a central processing unit (CPU) serving as a center of the personal computer (main body) are connected to a bus (for example, an I2C bus). ), The microcomputer for controlling the camera unit and the central processing unit of the personal computer communicate with each other via the bus. For example, a personal computer (main body) has storage means such as a RAM for storing at least various data such as application programs, and a central processing unit (CPU) performs various data processing based on the application programs. Unless otherwise specified in the description of the embodiments, the devices and the equipment generally have the same equipment and functions as a personal computer. More specifically, as shown in FIG. 1, a personal computer system including a camera unit includes a camera unit 10 and a main unit 20 of the personal computer.

The camera unit 10 includes an imaging unit 11, a signal processing unit 12, a drive processing unit 30, a crystal oscillator (X'tal) 14, and a microcomputer (CAMERA uCOM,
Hereinafter, it is referred to as a camera control microcomputer. ) 15. Further, a main body 20 which forms the main configuration of the personal computer includes a graphic accelerator 21,
I2C bus host control microcomputer 22, PCI
(Peripheral Computer Interconnect) bus line 2
3, an ISA bus line 24 and an I2C bus line 25 are provided. And the personal computer is I2
A battery control microcomputer (hereinafter, referred to as a battery control microcomputer) 26 connected to the C bus line 25 is provided. Each part of the camera unit and the main unit 20 of the personal computer has the following functions and the like.

The imaging unit 11 includes a lens, a CCD, and the like, and outputs a captured image as an electric signal by photoelectric conversion. The electric signal of the video photoelectrically converted by the imaging unit 11 is input to the signal processing unit 12.

The signal processing section 12 is an imaging signal processing section that performs signal processing on the electric signal output from the imaging section 11. Specifically, the signal processing unit 12 includes a sample hold
C, an A / D converter (ADC), and the like. The electric signal input to the signal processing unit 12 is subjected to noise removal (CDS) and signal amplification (A) for obtaining an appropriate signal level.
GC), analog-to-digital conversion (ADC), and output to the drive processing unit 30 as a digital video signal.

The drive processing unit 30 includes a CCD of the imaging unit 11 and a sample and hold of the signal processing unit 12, AGC and A / D.
It has a timing generator circuit for driving a converter and the like. The function of the drive processing unit 30 is not limited by its name, that is, the drive processing unit 30 may be named, for example, a signal processing unit.

The drive processing section 30 generates a timing waveform based on the crystal oscillator 14 by a timing generator circuit. Further, the drive processing unit 30 generates and outputs various timing waveforms (or clock frequencies) by appropriately dividing the oscillation frequency of the crystal oscillator 14. The digital video signal processed in the drive processing unit 30 is input to the main unit 20 of the personal computer.

The drive processing section 30 is an essential part of the present invention, and has a function of changing a clock frequency according to a power supply state for driving a personal computer. Such a function will be described later. It will be described in detail.

The camera control microcomputer 15 includes a camera unit 1
0 is a control means for controlling each unit. Specifically, the camera control microcomputer 15 takes in the luminance detection information and the color detection information detected by the drive processing unit 30, and performs exposure (AE) control and automatic white balance (AWB) control. Further, the camera control microcomputer 15 performs a process necessary for operating the drive processing unit 30. The camera control microcomputer 15 is connected to the I2C bus line 25 of the main body 20 of the personal computer, as described later.

The details of exposure control and automatic white balance control performed by the camera control microcomputer 15 are substantially the same as those performed by a so-called camcorder, and a description thereof will be omitted.

The components of the camera unit 10 are configured as described above. The digital video signal processed in the drive processing unit 30 of the camera unit 10 is input to the graphic accelerator unit 21 of the main unit 20 of the personal computer. You. The graphic accelerator unit 21 is connected to a PCI bus line 23. An image output unit (not shown) is connected to the PCI bus line 23. The image output unit is, for example, an LCD unit. Image output unit is PC
It is controlled by control means such as a CPU (not shown) of the main body of the personal computer via the I bus line 23, and outputs a camera image and the like obtained by the camera unit 10.

The CPU is connected to an I2C bus line 25 to which a peripheral (peripheral device) of a personal computer such as a keyboard is connected, and controls the peripheral of the personal computer via the I2C bus line 25. Also, the I2C bus line has
The camera control microcomputer 15 of the camera unit 10 is connected. The camera control microcomputer 15 has a port for the I2C bus, and this port is connected to the I2C bus line 2.
5, the camera control microcomputer 15
Is recognized as a slave peripheral when viewed from the personal computer side. As described above, the CPU of the main body of the personal computer and the microcomputer 15 for controlling the camera of the camera unit 10 are connected to the I2C bus line 25.
Is connected, the mutual communication between the main unit 20 and the camera unit 10 of the personal computer is performed.

The I2C bus line 25 is controlled by the I2C bus host control microcomputer 22. Here, the I2C bus host control microcomputer 22 is connected to the ISA bus line 24. As a result, application software of a personal computer can handle data in the same manner as data transmission / reception under I / O control.

A battery control microcomputer (hereinafter referred to as a battery control microcomputer) 26 is connected to the I2C bus line 25. The battery control microcomputer 26 controls a battery power source (not shown) for driving components (including the camera unit 10 and the main unit 20) of the personal computer. Various kinds of information on the remaining battery level detected based on the control contents of the battery control microcomputer 26 are transferred to application software or the like via the I2C bus host control microcomputer 22 and the ISA bus line 24.

As described above, the camera unit 10 of the personal computer system and the main unit 20 of the personal computer are configured. Next, the main parts according to the present invention will be described. The drive processing unit 30 forms a main part of the present invention.

FIG. 2 shows a configuration example of the drive processing unit 30. As shown in FIG. 2, the drive processing unit 30 includes a timing generator unit 31, a basic clock frequency dividing unit 32, a signal processing unit 33, and an I / O unit 34 for microcomputer communication.

The microcomputer communication I / O section 34 is used to transmit and receive data between the camera control microcomputer 15 and the drive processing section 30. This is for enabling setting of each block in the unit 30.

The basic clock frequency dividing section 32 includes the camera section 10
Constitutes clock control means for controlling the clock frequency of the reference clock used for the operation in accordance with the power supply state of the main body of the personal computer. That is,
The basic clock divider 32 divides the source oscillation frequency obtained from the crystal oscillator 14 to a predetermined frequency according to the power supply state. Specifically, the frequency division setting by the basic clock frequency dividing unit 32 is performed by setting the source oscillation frequency obtained from the crystal oscillator 14 to 1
/ 1, 1/2, 1/4, 1/8. Thus, for example, when the source oscillation frequency of the crystal oscillator 14 is 24.57 MHz, when the frequency division setting is halved, the basic clock frequency divider 32 generates a clock of 12.285 MHz. In other words, in other words, it can be said that the basic clock frequency divider 32 has the same function as the case where the crystal oscillators having different oscillation frequencies are provided. In addition, such frequency division setting is performed in accordance with the remaining battery capacity, and the remaining battery capacity is determined based on the remaining battery information detected based on the control content of the battery control microcomputer 26 described above. You. The configuration of the basic clock frequency dividing unit 32 has a general configuration.
Therefore, the description of the configuration is omitted because it is a known technique.

As described above, the basic clock divider 32 has a function of dividing the source oscillation frequency obtained from the crystal oscillator 14, and the division setting is detected by the above-described battery control microcomputer 26. This is performed based on the remaining battery status. Then, based on the clock of the basic clock frequency divider 32 generated in this way, the camera unit 10
Is operated by the imaging unit 11 and the signal processing unit 12.

Generally, it is considered that the relationship between the operating frequency and the current consumption of a digital circuit is that if the operating frequency increases twice, the power consumption also doubles. In other words, the power consumption can be reduced by reducing the operating frequency. Therefore, as described above, the frequency of the basic clock is divided and the imaging unit 11 and the signal processing unit 1 are divided.
The power consumption can be reduced by reducing the clock frequency used for the operation of the second and the like operation units.

FIG. 3 shows a flow (processing procedure) for setting the frequency division of the basic clock based on the power supply status (battery remaining amount status, etc.).
This will be described with reference to the flowchart of FIG. The process of setting the frequency division of the basic clock according to the flowchart shown in FIG. 3 is realized by software.

First, in step S1, it is determined what the power supply for driving the personal computer system is currently in. That is, AC
It is determined whether the power is supplied by the adapter and driven (AC power supply) or the battery is driven by battery power (battery power supply).

If it is determined in step S1 that AC power is being driven, the flow advances to step S2 to set the frequency division setting to 1/1. This is because power consumption does not need to be taken into account when driven by the AC power supply, so that the imaging performance of the camera unit 10 and the like can be emphasized by setting the frequency division setting to 1/1, which is the setting for normal operation.

On the other hand, if it is determined in step S1 that battery power is being driven, the process proceeds to step S3.
In step S3, a determination is made as to whether or not the user wants the highest imaging performance of the camera unit even if the camera is driven by battery power. That is, step S3 is provided as a determination process for allowing the user to give priority to image quality over battery consumption. Here, in order to realize the determination processing in step S3, an input means (selection means) for inputting image pickup with priority on image quality by the user is required. Examples of such an input unit include a unit that allows a user to make an actual selection using an application for a user interface higher than software executing the processing. The application for the user interface is constructed so as to be able to perform such processing, but a detailed description thereof will be omitted.

In step S2, which proceeds when the user determines that the highest performance is required (Yes) in step S3, the frequency division is set to 1/1. On the other hand, if the user sets (No) to change the frequency division setting of the basic clock according to the power supply condition in step S3, the process proceeds to step S4. After step S4, a process of confirming the state of the remaining battery level and a frequency division setting corresponding to the confirmed state of the remaining battery level are performed.

First, in step S4, it is determined whether or not the remaining battery charge is 50% or more. If it is 50% or more (Yes), the process proceeds to step S2, and the frequency division is set to 1/1. On the other hand, if less than 50% (No), the process proceeds to step S5.

In step S5, the remaining battery power is 30%
It is determined whether or not this is the case. If it is 30% or more (Yes), the process proceeds to step S6, and the frequency division is set to 1/2. Meanwhile, 3
If less than 0% (No), the process proceeds to step S7.

In step S7, the remaining battery power is 15%
It is determined whether or not this is the case. If it is 15% or more (Yes), the process proceeds to step S8, and the frequency division is set to 1/4. Meanwhile, 1
If less than 5% (No), the process proceeds to step S9, and the frequency division is set to 1
/ 8.

As described above, the frequency division is set by the processing in steps S4 to S9. In step S10, the frequency division set as described above is set in step S10 via the camera control microcomputer 15 via the I2C bus line 25. Passed to. The camera control microcomputer 15 performs settings for operating the camera unit 10 based on the passed frequency division setting.

As described above, the frequency division of the basic clock is set according to the power status (battery remaining power status, etc.). Then, the imaging unit 11 and the signal processing unit 12 operate based on a clock obtained by dividing the basic clock. Next, the operation of the camera unit 10 when the frequency division is set will be described. More specifically, the relationship between the video output digital signal data and the timing signal which changes according to the frequency division setting of the basic clock will be described. In the description, the following assumptions are made.

The imaging unit 11 uses a signal conforming to the Zoomedvideo (ZV) format as a video digital signal. The video signal output from the imaging unit 11 is composed of 640 horizontal pixels and 48 vertical pixels which are called a VGA size.
It corresponds to the image size of 0 line. Also, 1
The number of output screens per second (frame rate) is based on the fact that 30 frames are output when the frequency division setting of the basic clock is 1/1.

FIG. 4 shows a vertical synchronization timing chart in the timing chart of the video digital signal, and FIG. 5 shows a horizontal synchronization timing chart in the timing chart of the video digital signal.

"VSYNC" in FIG. 4 is a vertical synchronizing signal, has a length of 525H (H is a horizontal scanning time), and has a falling section of 9H. “HREF” in FIG. 4 is a horizontal synchronization signal, and its frequency is set to H which is the unit of the above-described horizontal operation time. The horizontal synchronization timing chart of the horizontal synchronization signal is as shown in FIG. "DATA" in FIG. 4 is vertical video signal digital data, which is composed of 8-bit luminance signal data (Y) and 8-bit color signal data (UV), and is data in YUV 4: 2: 2 format. It is. This data format is a known general mode, and details thereof are omitted. Where DATA
Outputs the vertical video digital data of the first line at 17H from the falling edge of VSYNC, and outputs 480 lines of vertical video digital data in synchronization with HREF.

On the other hand, "HREF" in FIG. 5 is a horizontal synchronizing signal and has a length of 780 CLK (CLK is a basic clock),
It has a rising section of CLK. Also, “PC in FIG.
“LK” indicates a synchronization signal having the same basic operation clock frequency as CLK. Also, “DATA” in FIG. 5 is horizontal video signal digital data, and the first horizontal video pixel signal data (Y000, V0
00) is output, and horizontal video digital data of 640 pixels is output in synchronization with PCLK.

The basic clock frequency division setting based on the above premise is nothing but changing the frequency (PCLK frequency) of the PCLK synchronization signal as shown in FIG. In FIG.
The relationship between the frequency division setting and the PCLK frequency is shown. As shown in FIG. 6, as the frequency division setting is set to 、, ４, １ ／, the PCLK frequency is also １ ／, ４, １ ／.
Changes to Thereby, the horizontal synchronization frequency H also changes as shown in FIG. As a result, the vertical synchronization frequency also changes, so that the number of output screens per second (frame rate) changes as shown in FIG. For example, when the frequency division setting is set to 1/8, the number of output screens per second (frame rate) is 3.75 of 1/8 of 30 frames.
Become a frame.

As described above, the number of output screens (frame rate) changes depending on various frequency division settings of the basic clock.
At this time, the power consumption also changes according to the number of output screens. The above description is about the relationship between the video output digital signal data and the timing signal in the division setting of various basic clocks. Similarly, the CCD 11a of the imaging unit 11 and the sample hold of the signal processing unit 12, Various timing signals supplied to the AGC, the A / D converter, and the like also change according to various frequency division settings. This also corresponds to a change in the CCD accumulation time in FIG. That is, as the frequency division setting value decreases, the frequency of the CCD drive timing signal decreases, and as a result, the CCD accumulation time increases. For example,
Where the CCD accumulation time was 1/30 second when the frequency division setting was 1/1, the CCD accumulation time was increased to 8 times that of 1 / 3.75 second when it was set to 1/8. .

As described above, by changing the clock, the digital circuit such as the signal processing unit 12 performs processing different from the normal operation by changing the operating frequency. It manifests itself as a change.

As described above, it is generally considered that the relationship between the operating frequency and the current consumption of a digital circuit is that if the operating frequency increases twice, the power consumption also doubles. Actually, when designing an IC, in order to reduce the current consumption as much as possible, the increase in the current consumption when the operating frequency is doubled is about 1.3 times. Thus, when the present invention is applied and the frequency division setting is reduced to a half value, the current consumption of the signal processing unit 12 and the like of the camera unit 10 can be reduced by about 30%. This allows
By reducing the frequency division setting of the basic clock according to the remaining battery power, the current consumption of the camera unit 10 can be reduced, and the duration of the battery can be extended.

By reducing the set frequency division, the number of output screens per second (frame rate) decreases,
As a result, the screen becomes a frame-by-frame image, which becomes more noticeable as the frequency division setting of the basic clock becomes smaller. However, the present invention is useful when it is desired to give priority to battery duration over dropped frames in the camera image. It is. Conversely, when it is desired to prioritize the frame rate of the camera image over the battery duration time, by manually selecting the frame rate, there is an advantage in that the user can determine which one is prioritized by the user's will. When the battery duration is prioritized, the frequency division setting of the basic clock is automatically changed, so that the user does not have to worry about it.

When the clock frequency is changed, the personal computer temporarily stops the image output unit (LC).
D unit) may perform a predetermined operation.
Specifically, as a predetermined operation, the camera video output is switched to mute, black back, blue back, or the like at the timing of switching the frequency division setting, and an image is output to the image output unit. For example, such an operation is executed by application software on the personal computer side. By switching the image output in this way, it is possible to avoid output of a video disturbance that occurs at the timing of switching the frequency division setting of the basic clock.

Then, as described above, after the camera video output is switched to mute, black back, blue back, or the like, the camera video output from the camera unit 10 is switched again at a predetermined timing. For example, the timing of switching back to the camera video output from the camera unit 10 is a timing at which the disturbance of the camera video output stops or a timing after a lapse of time sufficient to stop the disturbance of the video output.

Further, the personal computer can continue to output the camera image immediately before the division setting of the basic clock is changed. Specifically, the camera video output immediately before switching the frequency division setting of the basic clock is held,
This is output to the image output unit, and after setting the textbook, switching to the camera video output from the camera unit 10 is performed again at a predetermined timing. As a result, the video output to the image output unit before and after the division of the basic clock is set is performed more naturally.

It should be noted that the processing technology using the application software of the personal computer and the technology relating to the replacement of the camera video output for realizing such processing are to be performed by generally known existing technologies.

In the above-described embodiment, an example in which the present invention is applied to a personal computer having a built-in camera has been described. However, the present invention is not limited to such an example. For example, the present invention can be provided for a personal computer in which a camera device can be freely attached. In this case, the personal computer
The camera device includes an external interface for external connection. Thus, the personal computer inputs a video signal transmitted from an externally connected camera device via the external interface, and outputs an image based on the video signal. Then, the remaining battery level is detected on the personal computer side, and on the camera device side,
The frequency division of the basic clock is set according to the remaining battery power of the personal computer, and the imaging unit and the like operate according to the clock. In a personal computer to which such a camera device is externally connected, it is assumed that the camera device and the personal computer share battery power in order to obtain the effects of the present invention.

[0052]

According to the information processing apparatus of the present invention, the clock frequency of the reference clock used for the operation of the imaging means is controlled by the clock control means in accordance with the state of the power supply. The power consumption can be changed by changing the operating frequency of.

Thus, when the remaining battery power is low, the clock frequency is changed, and each component of the imaging means can be operated at an operating frequency at which power consumption is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a camera unit and a main body of a personal computer according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration of a drive processing unit of the camera unit.

FIG. 3 is a flowchart showing a setting of a frequency division of a basic clock performed according to a power supply state.

FIG. 4 is a timing chart of vertical synchronization in a timing chart of a video digital signal.

FIG. 5 is a timing chart of horizontal synchronization in the timing chart of the video digital signal.

FIG. 6 is a diagram illustrating a relationship between a frequency division setting of a basic clock and a PCLK frequency.

[Explanation of symbols]

10 camera section, 11 imaging section, 12 signal processing section, 1
4 crystal oscillator, 15 camera control microcomputer, 20 main unit, 26 battery control microcomputer, 30 drive processing unit, 31 timing generator unit, 32 basic clock frequency dividing unit, 33 signal processing unit, 34 I / O for microcomputer communication O part

Claims (11)

[Claims] 1. A clock control means for controlling a clock frequency of a reference clock used by an imaging means for operation in accordance with a power supply condition, and various data including processing based on a video signal obtained by the imaging means. An information processing apparatus comprising: a data processing control unit that controls the processing of (1). 2. The information processing apparatus according to claim 1, wherein said image pickup means is integrally provided. 3. An information processing apparatus according to claim 1, wherein said image pickup means is detachable, and said image pickup means has an external interface connected to the outside. 4. The imaging means operates based on a reference clock, a clock generation unit for generating a clock based on the reference clock, and a clock generated by the clock generation unit, and electrically converts a captured image by photoelectric conversion. An image pickup unit including an image pickup device that converts the signal into a signal; and an image pickup signal processing unit that operates based on a clock generated by the clock generation unit and performs signal processing on an electric signal output from the image pickup unit. 2. The information processing apparatus according to claim 1, wherein the control unit controls a clock frequency generated by the clock generation unit according to a power supply state. 5. The system according to claim 1, wherein the clock control means determines an AC power drive state or a battery power drive state, and controls the clock frequency according to a remaining battery level when the battery power is being driven. The information processing apparatus according to claim 1, wherein 6. The information processing apparatus according to claim 1, wherein said clock control means controls said clock based on a power status and input information from a user made in accordance with said power status. apparatus. 7. A storage means for storing various data, and said data processing control means is a central processing unit, and controls processing of various data based on a software program stored in said storage means. The information processing apparatus according to claim 1, wherein: 8. The information processing apparatus according to claim 1, further comprising an image output unit, wherein the data processing control unit outputs a video signal obtained by the imaging unit to the image output unit. . 9. The information processing apparatus according to claim 8, wherein said data processing control means causes said image output unit to temporarily perform a predetermined operation when said clock frequency is changed. 10. The information processing apparatus according to claim 9, wherein the predetermined operation performed by the image output unit is at least a mute operation, a black-back image output operation, or a blue-back image output operation. 11. The information processing apparatus according to claim 9, wherein the predetermined operation performed by the image output unit continues to output an image immediately before the clock frequency is changed.