JP2002050901A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small sized variable delay circuit, which can set a delay time to an arbitrary value without requiring a line having the length proportional to the delay time. SOLUTION: The small sized variable delay circuit comprises: a first line 2a and a second line 2c; and a line 2b, one terminal of which is connected to a point between the first line 2a and the second line 2c through a FET 3, the other terminal of which is open, and a length of which is λg/2 (λg: the wavelength in a line that forms a stub).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a microwave band,
The present invention relates to a variable delay circuit that electrically changes a signal delay time in a millimeter wave band.

[0002]

2. Description of the Related Art FIG. 17 shows, for example, "Microwave Semiconductor Applied Engineering" (Joseph F. White, published by CQ Publishing Company) pp.
336-339 is a conventional variable delay circuit. FIG.
, 1a and 1b are input / output terminals, 2a and 2b are SP
DT (Single Pole Double Throw) switch, 3a, 3
b is a track.

Next, the operation will be described. I / O terminal 1
The high-frequency signal input from a is switched by the SPDT switch 2a. First, a case where a high-frequency signal passes through the line 3a will be described. The high-frequency signal switched by the SPDT switch 2a passes through the line 3a and
The signal is input to the PDT switch 2b. SPDT switch 2
b is linked with the SPDT switch 2a, and the high frequency signal is output from the input / output terminal 1b.

Next, a case where a high-frequency signal passes through the line 3b will be described. The high-frequency signal switched by the SPDT switch 2a passes through the line 3b and is input to the SPDT switch 2b. The SPDT switch 2b has an S
The high-frequency signal is output from the input / output terminal 1b in conjunction with the PDT switch 2a.

Here, the line 1a and the line 1b have different lengths, and the delay time can be switched between a case where the high-frequency signal passes through the line 2a and a case where the high-frequency signal passes through the line 2b.

[0006]

In the conventional variable delay circuit, lines having different lengths according to the delay time are used. Therefore, when the delay time is increased, a very long line is required, and the circuit becomes large. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and does not require a line having a length proportional to the delay time, and is capable of setting a small variable delay capable of setting an arbitrary delay time. The aim is to obtain a circuit.

[0008]

A variable delay circuit according to the present invention is connected via a switch between first and second lines and between the first and second lines, and the other end is open. Λg / 2 (λg: wavelength in the line constituting the stub)
And a line having the following line length.

Also, the first and second lines, the first and second lines,
And a line having a line length of λg / 4 (λg: wavelength in the line forming the stub), which is connected via a switch between the two lines and is grounded at the other end.

In addition, two switches, two lines switched by the two switches, and λg / 2 (λg: stub connected to at least one of the two lines and open at the other end thereof). Wavelength in the constituent lines)
And a line having the following line length.

Further, the lines having the line length of λg / 2 whose ends are open are respectively connected to the two lines, connected to one of the two lines, and the ends are open. a line having a line length of λg / 2;
The characteristic impedance is different from that of a line connected to the other line side of one line and having a line length of λg / 2 whose tip is open.

Also, two switches, two lines switched by the two switches, and λg / 4 (λg: stub connected to at least one of the two lines and grounded at the other end) Wavelength in the constituent lines)
And a line having the following line length.

Lines having line lengths of λg / 4, the ends of which are grounded, are respectively connected to the two lines, are connected to one of the two lines, and have the other end. A line having a line length of λg / 4, which is grounded, and a line connected to the other line side of the two lines and having a line length of λg / 4, the other end of which is grounded. It is characterized in that the impedance is different.

Further, two switches, two lines switched by the two switches, and a λ connected to one of the two lines and the other end grounded.
g / 4 (λg: wavelength in a line forming a stub), and a line length of λg / 2 connected to the other line side of the two lines and having an open end at the other end. And a line having:

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a circuit diagram showing a variable delay circuit according to Embodiment 1 of the present invention. FIG. 2 is a layout diagram showing the variable delay circuit according to the first embodiment of the present invention. In these figures, 1a and 2b are input / output terminals, 2a, 2b and 2c are lines, and 3 is an FET as a switching element. Here, the line 2b has a length of λg / 2 (λg: the wavelength of the line 2b constituting the stub at a desired frequency),
The tip is open.

Next, the operation will be described. I / O terminal 1
The high frequency signal input from a is input to the line 2a.
Here, when the gate bias below the pinch-off is applied to the FET 3, that is, when the FET 3 is in the OFF state, no high-frequency signal passes between the drain and the source of the FET 3, and the impedance of the FET 3 viewed from the line 2a becomes infinite. Therefore, the high-frequency signal is output from the input / output terminal 1b via the line 2c in a state where matching is achieved.

On the other hand, when a gate bias higher than the pinch-off is applied to the FET 3, that is, when the FET 3
In the N state, the high-frequency signal passes between the drain and the source of the FET 3 and is input to the line 2b having an open end. Since the length of the line 2b is λg / 2, the impedances of the FET 3 and the line 2b viewed from the line 2a become infinite, so that the high-frequency signal is transmitted from the input / output terminal 1b via the line 2c in a matched state. Is output.

As described above, by turning ON / OFF the FET 3, the line 2b having the open end can be connected or not connected, and can be changed. Since the length of the line 2b is λg / 2, the passing amplitude does not change, but the delay time changes by an amount represented by the following equation.
That is, the relationship between the characteristic impedance of the stub line 2b and the delay amount (Delay _fc ) is as follows. In the equation, Z _S is a characteristic impedance of the stub line 2b normalized by the impedance of the input / output terminal.

[0019]

(Equation 1)

FIG. 3 shows the relationship between the impedance of the stub line 2b normalized by the impedance of the input / output terminal and the delay time. As shown in FIG. 3, an arbitrary delay time can be set by changing the characteristic impedance of the stub line 2b having an open end, and a line having a length proportional to the delay time is not required. Therefore, miniaturization is possible.

Therefore, according to the first embodiment,
A line 2b connected between the lines 2a and 2b via the FET 3 and having a line length of λg / 2 and having an open end at the other end.
, So you can set any delay time,
In order not to need a line of length proportional to the delay time,
The size can be reduced.

Embodiment 2 FIG. In the above-described first embodiment, the delay time is switched by turning on / off the line whose length at the open end is λg / 2 with a semiconductor element. However, the line whose length at the end is grounded is λg / 4. The same effect can be obtained even if the semiconductor element is turned ON / OFF.

FIG. 4 is a circuit diagram showing a variable delay circuit according to Embodiment 2 of the present invention. FIG. 5 is a layout diagram showing a variable delay circuit according to Embodiment 2 of the present invention. In these drawings, the same parts as those in the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof will be omitted. As a new code, 4 is a through hole for grounding. Here, the line 2b is λg / 4 (λg:
(Wavelength on the line 2b at a desired frequency), and the tip is grounded.

Next, the operation will be described. I / O terminal 1
The high frequency signal input from a is input to the line 2a.
Here, when the gate bias below the pinch-off is applied to the FET 3, that is, when the FET 3 is in the OFF state, no high-frequency signal passes between the drain and the source of the FET 3, and the impedance of the FET 3 as viewed from the line 2a becomes infinite. Therefore, the high-frequency signal is output from the input / output terminal 1b via the line 2c in a state where matching is achieved.

On the other hand, when a gate bias higher than the pinch-off is applied to the FET 3, that is, when the FET 3
In the N state, a high-frequency signal passes between the drain and the source of the FET 3, and the high-frequency signal is input to the line 2b whose tip is grounded. Since the length of the line 2b is λg / 4, the impedance of the FET 3 and the line 2b as viewed from the line 2a becomes infinite, so that the high-frequency signal is transmitted from the input / output terminal 1b via the line 2c in a matched state. Is output.

As described above, by turning ON / OFF the FET 3, the line 2b having the grounded end can be connected or not connected. Since the length of the line 2b is λg / 4, the passing amplitude does not change, but the delay time changes.

Embodiment 3 In the above embodiment, the delay time is switched by connecting or disconnecting the stub line by the semiconductor element. However, the same effect can be obtained by switching between the line connected to the stub line and the line not connected. Can be

FIG. 6 is a circuit diagram showing a variable delay circuit according to Embodiment 3 of the present invention. FIG. 7 is a layout diagram showing a variable delay circuit according to Embodiment 3 of the present invention. In these figures, a new reference numeral 5
a and 5b are SPDT switches. Here, line 2c
Has a length of λg / 2 (λg: the wavelength on the line 2b at a desired frequency) and has an open end.

Next, the operation will be described. I / O terminal 1
The high-frequency signal input from a is input to the SPDT switch 5a. The SPDT switches 5a and 5b are connected to the line 2a
When the signal passes through the line and the line 2b is cut off, the high-frequency signal is output from the input / output terminal 1b via the SPDT switch 5a, the line 2a, and the SPDT switch 5b.

The SPDT switches 5a and 5b are connected to the line 2a
When the line is cut off and the line 2b is passed, the high-frequency signal is output from the SPDT switch 5a, line 2b, line 2d, S
It is output from the input / output terminal 1b via the PDT switch 5b. The line 2c having an open end has a length of λg / 2.
Therefore, at the center frequency, the impedance viewed from the line 2b is open, and the impedance matching between the input / output terminals 1a and 1b is achieved.

Here, when the circuits that pass through are switched by the SPDT switches 5a and 5b, the sum of the length of the line 2a, the length of the line 2b and the length of the line 2d, and the sum of the delay due to the line 2c whose tip is open. The delay time can be switched by the difference.

Embodiment 4 FIG. In the third embodiment, only one line 2c having an open end is used, but the same effect can be obtained by using a plurality of lines.

FIG. 8 is a circuit diagram showing a variable delay circuit according to Embodiment 4 of the present invention. FIG. 9 is a layout diagram showing a variable delay circuit according to Embodiment 4 of the present invention. Here, the line 2b and the line 2d are λg /
2 (λg: wavelength at the line 2b at a desired frequency), and the tip is open.

Next, the operation will be described. When the circuits that pass through are switched by the SPDT switches 5a and 5b, the delay time can be switched by the difference between the length of the line 2a, the length of the line 2c, and the sum of the delays of the open lines 2b and 2d. Become. Further, when the distance between the line 2b and the line 2d is set to λg / 4, when reflection occurs on the line 2b and the line 2d, they can cancel each other out and reduce the reflection.

Embodiment 5 FIG. In the fourth embodiment, the lines 2b and 2d having open ends are connected to the SPDT switch 5
Although it was used for only one of the circuits that can be switched between a and 5b,
The same effect can be obtained by using both circuits switched by the SPDT switch.

FIG. 10 is a circuit diagram showing a variable delay circuit according to the fifth embodiment of the present invention. Here, the track 2a,
The line 2c, the line 2d, and the line 2f are λg / 2 (λ
g: the wavelength of the line 2b at a desired frequency), the tip is open, and the lines 2a and 2c, and the lines 2d and 2f are displayed with different thicknesses in the drawing. Thus, the characteristic impedances are different.

Next, the operation will be described. When the circuits passing through are switched by the SPDT switches 5a and 5b, the sum of the length of the line 2b, the delay due to the line 2a having the open end and the delay due to the line 2c having the open end, and the length and the end of the line 2e It is possible to switch the delay time by the difference between the delay due to the line 2d having the open end and the sum of the delay due to the line 2f having the open end.

Embodiment 6 FIG. In the fifth embodiment, the circuit is configured by using the line having the open end. However, the same effect can be obtained by using a line having a grounded end and a length of λg / 4.

FIG. 11 is a circuit diagram showing a variable delay circuit according to Embodiment 6 of the present invention. FIG. 12 is a layout diagram showing a variable delay circuit according to Embodiment 6 of the present invention. Here, the line 2b and the line 2d are λ
g / 4 (λg: wavelength at the line 2b at a desired frequency), and the tip is grounded.

Next, the operation will be described. When the circuits that pass through are switched by the SPDT switches 5a and 5b, the difference between the length of the line 2a and the sum of the length of the line 2c and the delay due to the line 2b having the grounded end and the delay due to the line 2d having the grounded end Only the delay time can be switched.

Embodiment 7 FIG. In the sixth embodiment, the line whose tip is grounded is used for only one of the circuits that can be switched by the SPDT switches 5a and 5b. However, the same effect can be obtained by using both lines that are switched by the SPDT switches 5a and 5b. Can be

FIG. 13 is a circuit diagram showing a variable delay circuit according to Embodiment 7 of the present invention. Here, the track 2a,
The line 2c, the line 2b, and the line 2d are λg / 4 (λ
g: wavelength at each line at a desired frequency), the tip is grounded, and lines 2a and 2c,
The line 2d and the line 2f have different characteristic impedances so as to be displayed with different thicknesses in the drawing.

Next, the operation will be described. When the circuits passing through are switched by the SPDT switches 5a and 5b, the sum of the length of the line 2b and the delay due to the line 2a having the grounded end and the delay due to the line 2c having the grounded end, and
The delay time can be switched by the difference between the length of e and the delay due to the line 2d whose tip is grounded and the sum of the delay due to the line 2f whose tip is grounded.

Embodiment 8 FIG. SPDT switches 5a, 5
a line whose tip is open to one of the circuits switched by b,
On the other hand, the same effect can be obtained by using a circuit whose tip is grounded.

FIG. 14 is a circuit diagram showing a variable delay circuit according to Embodiment 8 of the present invention. Here, the ends of the line 2a and the line 2c are open, and the line length is λg / 2.
It is. The ends of the line 2d and the line 2f are grounded, and the line length is λg / 4.

Next, the operation will be described. When the circuits passing through are switched by the SPDT switches 5a and 5b, the sum of the length of the line 2b and the delay due to the line 2a having an open end and the delay due to the line 2c having an open end, and the line 2
The delay time can be switched by the difference between the length of e and the delay due to the line 2d whose tip is grounded and the sum of the delay due to the line 2f whose tip is grounded.

Embodiment 9 FIG. Embodiments 1 to 8 above
In the above, a layout in which a circuit is formed on one substrate is shown, but the same effect can be obtained by using a plurality of substrates.

FIG. 15 is a layout diagram showing a variable delay circuit according to the ninth embodiment of the present invention. In FIG. 15, reference numerals 6a, 6b, and 6c denote dielectric substrates. Here, the same effect can be obtained even if the dielectric substrates 6a, 6b, and 6c are configured using semiconductor substrates such as GaAs.

Embodiment 10 FIG. In the first to eighth embodiments, one line is used as a line whose tip is open or a line whose tip is grounded. However, a plurality of lines are connected, and the total electrical length is λg /. 2 (in the case of a line with an open end) or λg / 4 (in the case of a line with a grounded end), the same effect can be obtained.

FIG. 16 is a layout diagram showing a variable delay circuit according to the tenth embodiment of the present invention. As shown in the figure, a circuit is formed by cascade-connecting a line 2b and a line 2c having different impedances, and the sum of the electrical lengths of the lines 2b and 2c is λg / 2.

[0051]

As described above, according to the present invention, an arbitrary delay time can be set, and a line having a length proportional to the delay time is not required, so that the size can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a variable delay circuit according to Embodiment 1 of the present invention.

FIG. 2 is a layout diagram illustrating a variable delay circuit according to Embodiment 1 of the present invention;

FIG. 3 is an explanatory diagram showing a relationship between the impedance of a stub line 2b normalized by the impedance of an input / output terminal and a delay time.

FIG. 4 is a circuit diagram showing a variable delay circuit according to a second embodiment of the present invention.

FIG. 5 is a layout diagram showing a variable delay circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a variable delay circuit according to Embodiment 3 of the present invention.

FIG. 7 is a layout diagram showing a variable delay circuit according to Embodiment 3 of the present invention.

FIG. 8 is a circuit diagram showing a variable delay circuit according to Embodiment 4 of the present invention.

FIG. 9 is a layout diagram showing a variable delay circuit according to Embodiment 4 of the present invention.

FIG. 10 is a circuit diagram showing a variable delay circuit according to a fifth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a variable delay circuit according to Embodiment 6 of the present invention.

FIG. 12 is a layout diagram showing a variable delay circuit according to Embodiment 6 of the present invention.

FIG. 13 is a circuit diagram showing a variable delay circuit according to a seventh embodiment of the present invention.

FIG. 14 is a circuit diagram showing a variable delay circuit according to Embodiment 8 of the present invention.

FIG. 15 is a layout diagram showing a variable delay circuit according to Embodiment 9 of the present invention.

FIG. 16 is a layout diagram showing a variable delay circuit according to Embodiment 10 of the present invention.

FIG. 17 is a circuit diagram showing a conventional variable delay circuit.

[Explanation of symbols]

1a, 1b input / output terminals, 2a, 2b, 2c, 2d, 2
e, 2f line, 3FET, 4 through hole, 5a,
5b SPDT switch.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhiko Nakahara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Nao Takagi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo 3 Rishi Electric Co., Ltd. F-term (reference) 5J012 GA13 HA02 HA03

Claims (7)

[Claims] 1. A first and second line, λg / 2 (λg: a line constituting a stub), connected between the first and second lines via a switch and having an open end at the other end. Having a line length of (wavelength). 2. A λg / 4 (λg: stub constituting a stub) which is connected between a first and a second line via a switch between the first and the second line and whose other end is grounded. Having a line length of (wavelength). 3. Two switches, two lines that are switched by the two switches, and λg / 2 (λg: stub connected to at least one of the two lines and open at the other end. And a line having a line length corresponding to the wavelength of the line constituting the variable delay circuit. 4. The variable delay circuit according to claim 3, wherein a line having an open end and a line length of λg / 2 is connected to each of the two lines, and one of the two lines A line connected to the line side and having a line length of λg / 2 with an open end, and a line connected to the other line side of the two lines and having an open end.
A variable delay line having a characteristic impedance different from that of a line having a line length of 2. 5. Two switches, two lines switched by the two switches, and λg / 4 (λg: stub connected to at least one of the two lines and grounded at the other end) And a line having a line length corresponding to the wavelength of the line constituting the variable delay circuit. 6. The variable delay circuit according to claim 5, wherein a line having a line length of λg / 4 whose tip is grounded is connected to each of said two lines, and one of said two lines A line connected to the line side and having a line length of λg / 4, the other end of which is grounded; and λg / connected to the other line side of the two lines and having the other end grounded. A variable delay line having a characteristic impedance different from a line having a line length of 4. 7. Two switches, two lines that are switched by the two switches, and λg / 4 (λg: λg: connected to one of the two lines and the other end grounded). A line having a line length of (wavelength of a line forming a stub), and a line connected to the other line side of the two lines and having a line length of λg / 2, the other end of which is open. Variable delay circuit.