JP2002043935A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that suppress occurrence of jitter due to an external noise. SOLUTION: In the PLL circuit configured with an LSI provided with a charge pump circuit 2, a voltage resulting from sampling an output of the charge pump circuit 2 by a sampling circuit 7 is applied to other terminal of an AC conversion gain setting resistance Rd connected to an output terminal of the charge pump circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL capable of generating a signal having a frequency which is a coefficient times the frequency of an input clock signal.
The present invention relates to a circuit, and more particularly to suppression of jitter due to external noise.

[0002]

2. Description of the Related Art Description of a conventional PLL circuit High-precision signal processing in a digital signal processing system is performed by:
This is realized by a PLL (phase locked loop) circuit that can generate a stable high-frequency clock signal that cannot be easily generated by the X'tal oscillation circuit. As described above, the PLL circuit is a very useful circuit and is widely used.

FIG. 8 shows a configuration example of a conventional PLL circuit. From the X'ta1 oscillation circuit 12, a reference clock signal KR of 30 MHz or less, which can be easily generated only by the crystal oscillator, is output, and is input to the reference signal input R of the phase comparison circuit 1. The variable frequency oscillation circuit 4 controlled by the control voltage VD outputs a desired high frequency reference clock KV used in the system.

The reference clock KV is input to a frequency dividing circuit 5, outputs a frequency-divided n clock signal, and is input to a comparison input V of the phase comparing circuit 1. In the phase comparison circuit 1, the phase of the comparison signal V is delayed with respect to the reference signal R (the phase is advanced).
And an up pulse U (down pulse D). If the phases of the comparison signal V and the reference signal R match, neither the up pulse U nor the down pulse D is output (or both have the same pulse width). These up pulse U and down pulse D are input to the charge pump circuit 2 to generate an error voltage VC. The error voltage VC is input to the control signal generation circuit 3. The control signal generation circuit 3 generates a control voltage VD for generating a control current for determining the output frequency of the variable frequency oscillation circuit 4. The control voltage VD is input to the variable frequency oscillation circuit 4.

The output of the charge pump circuit 2 includes a resistor Rd
And a capacitor Co, one of which is grounded. This secures loop stability which is hindered by setting (or amplifying) the control phase error in the variable frequency oscillation circuit 4 by setting the AC conversion gain to a predetermined finite value. Since the above-mentioned capacitance Co for setting the AC conversion gain generally has to be set to a value of 1000 pF or more, LSI
(Large-scale integrated circuits) are disadvantageous to be realized inside. For this reason, as shown in FIG.
nl and pin2 (LSI internal GND) are required.
If the GND of the printed circuit board is used as the ground point, the pin 2 is not necessary. Jitter components due to noise can be suppressed.

At present, a digital phase comparison circuit is generally employed for the phase comparison circuit 1. Since this digital phase comparison circuit has a frequency detection capability in addition to a phase difference detection capability, the PLL circuit can realize a stable configuration without a malfunction condition. The output reference clock KV is X ′
This is a high frequency stable clock signal having a frequency n times higher than the clock signal generated by the tal oscillation connection 12 and which cannot be generated by the X'tal oscillation circuit. This meaningful PLL circuit is generally used in a digital signal processing circuit (LSI) that is becoming more and more accurate.

[0007]

However, the conventional PLL circuit has the following problems. One or two LSI pins are consumed for setting the AC conversion gain, which is a restriction on the configuration of the digital signal processing LSI. In addition, a restriction is imposed on the mounting of a printed circuit board to prevent jitter due to extraneous noise, which is extremely difficult to take measures, making it difficult to use a digital signal processing LSI.

The present invention has been made under such circumstances, and a PLL capable of suppressing jitter due to external noise.
It is intended to provide a circuit.

[0009]

In order to achieve the above object, according to the present invention, a PLL circuit is configured as in the following (1) to (4).

(1) LS with charge pump circuit
A PLL circuit configured to supply a voltage obtained by sampling an output of the charge pump circuit by a sampling circuit to the other end of an AC conversion gain setting resistor connected to an output terminal of the charge pump circuit. .

(2) In the PLL circuit according to (1), the sampling circuit divides a frequency of a reference clock input to the PLL circuit and samples the frequency as a sampling pulse.

(3) The PLL circuit according to (1), wherein the charge pump circuit is a differential signal.

(4) In a PLL circuit which receives a first clock signal and generates a second clock signal having a frequency which is a multiple of the frequency of the first clock signal, an output terminal of a charge pump circuit included in the PLL circuit , A voltage sampling circuit having an output terminal of the charge pump circuit connected to an input terminal, and a signal having a frequency division cycle of the first clock signal or the second clock signal. As a sampling pulse, and a voltage signal based on an output signal of the voltage sampling circuit is supplied to the other end of the resistance element.
circuit.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described by using a PLL.
This will be described in more detail with reference to embodiments of the circuit.

[0015]

FIG. 1 is a block diagram showing the configuration of a "PLL circuit" according to an embodiment. The difference from the conventional PLL circuit of FIG. 8 will be described. The blocks corresponding to those of the conventional PLL circuit are denoted by the same reference numerals.

FIG. 2 shows a general configuration of a conventional charge pump circuit 2. The negative-polarity up pulse NU and the positive-polarity down pulse PD are respectively input to MPl / G (which indicates the gate of the FET MP1, and hereinafter similarly indicated) and MNl / G. Outputs voltage VC. MNl / S has a down current Il
Is generated by MN2, and the up current I
2 is generated by MP2, MP3 and MN3. MN2
/ G and MN3 / G receive the same bias VBl to ensure the correlation between currents Il and I2.

Normally, the (W / L) ratio of the related transistors is set so that the down current Il and the up current I2 become equal. However, this charge pump circuit has 2
There are two problems. It is impossible to design the drain-source voltages of MN2 and MN3 and the drain-source voltages of MP2 and MP3 to be substantially equal, and fluctuates with respect to the absolute variation of the element (particularly, current driving capability) and the environment (operating temperature and power supply voltage). Therefore, the down current I1 and the up current I2 cannot be balanced by the Early effect. This means that, when considered steadily, an equilibrium state is established when the input up-pulse width and the down-pulse width are shifted, and the comparison signal V
Converge in a state where the phase is shifted with respect to the reference signal R. In addition, up pulse and down pulse cause M
When Pl and MNl are OFF, MPl / S and M
Nl / S moves in potential toward the power supply and GND, respectively, and the current drive capability of MP2 and MN2 is lost.

When MPl (MNl) changes to ON from this state, first, MPl / S (MNl / S) is lowered (increased), and then the current drive capability of MP2 (MN2) is restored to increase the up current I2 (down). By generating the current Il), a current is supplied to the charge pump terminal to change the error voltage VC. As described above, in the charge pump circuit of FIG. 2, the transient characteristics are not ideally performed, and not only there is a problem in high-speed operation, but also in a state where the comparison signal V in the equilibrium state is out of phase with the reference signal R. Have convergent factors.

The time chart shown in FIG. 4A shows the waveforms of the reference signal R, the comparison signal V, the up pulse U, and the down pulse D in a balanced state when the charge pump circuit 2 performs an ideal operation. As can be seen from the figure, since both the up pulse U and the down pulse D are narrow and equal in width, ripple due to the charge pump operation is unlikely to occur in the error voltage. On the other hand, in the charge pump circuit of FIG. 2, since the phases of the reference signal R and the comparison signal V are balanced as shown in FIG. 4B, the pulse widths of the up pulse U and the down pulse D do not match (in this case, The pulse width of the pulse U is large). For this reason, the ripple due to the charge pump operation is superimposed on the error voltage VC, causing jitter in the output reference clock signal KV.

In this embodiment, a charge pump circuit having the configuration example shown in FIG. 3 is used. The differential up pulses (NU, PU) converted into differential signals are input to MP1 / G and MP4 / G, respectively, and the differential down pulses (PD, ND) similarly converted into differential signals are respectively input to MNl / G. G
And MN4 / G. MP1 / S and MP4 /
S is connected and supplies an up current I2 to MP
2 / D, while MN1 / S and MN4 / S are connected and connected to MN2 / D, which supplies the down current. MP1 / D and MN1 / D and MP4 / D and M
N4 / D are connected to each other, and the connection point of MP1 / D and MN1 / D is connected to the power supply and the capacitors Cl and C connected to GND.
2 and output as an error voltage VC. The error voltage VC is input to the voltage buffer 11, and the output is
4 / D and MN4 / D. The voltage buffer 11 has, for example, the configuration shown in FIG.
It is preferable to realize a voltage buffer having a wide input / output dynamic range by using a CMOS transistor in combination with a CMOS transistor.

In FIG. 3, the same bias VB as MN2 is used.
The MN3 driven by 1 generates a coefficient current of the down current Il and is connected to MP3 / D. MP3 / G and MP2 / G
Is connected, a coefficient current of an up current is generated in MP3 / D. And the current value of MP3 / D is MN3 /
MN5, MN6, MN so as to be equal to the current value of D
7, MP5, MP6 and resistors R1, R2 control the current balance of the up current I2 and the down current Il. The voltage in the current balance is determined by the resistors R1 and R2, and is usually set to half of the power supply voltage at which the operating voltage range of the error voltage VC is the widest (that is, Rl =
R2).

The charge pump circuit shown in FIG. 3 not only dramatically improves the balance between the up current and the down current, but also has the MPl or MNl related to the charge pump operation.
Is OFF, MP4 or MN4 turns ON and MP
By maintaining the 1 / S and MNl / S voltages, the up current source MP2 and the down current source MN2 can be always operated. Moreover, since the error voltage VC is input to the connection point between MP4 / D and MN4 / D via the voltage buffer 11, the voltage between the drain and the source when the transistors MP1 and MP4 and the transistors MN1 and MN4 are turned on and off. , The charge pump operation for the change of the up pulse and the down pulse is remarkably quick. Regarding the element values of the capacitors Cl and C2 connected to the error voltage VC terminal, the resistance ratio (R1 / R2) and the capacitance ratio (C2 / Cl)
If it is set so as to satisfy, the power supply noise becomes strong. Error voltage V output from charge pump circuit 2
C is input to the control signal generation circuit 3 and is input to the sampling circuit 7 to output a sampling voltage VS.

The configuration of the sampling circuit 7 is, for example, as shown in FIG. Based on the circuit configuration of the voltage buffer in FIG. 6, a wide input / output dynamic range is ensured. MP7 / G is different from voltage buffer
And a sampling pulse SB (sampling at L level) is input to MPIO / G and the sampling pulse SB
Functions as a voltage buffer only when is input. Capacitors C3 and C4 are connected to the output terminal VS, and perform a holding operation after canceling the sampling operation. On the other hand, the input reference signal K
R is input to the reference signal R of the phase comparator 1 and is also input to the frequency divider 8 to generate a sampling pulse SB (sampled at L level) divided by m and input to the sampling circuit 7. The sampling voltage VS is input to a voltage buffer 6 (preferably the configuration shown in FIG. 6).
The voltage is supplied to the resistor Rd as a holding voltage Vo of the AC conversion gain setting resistor Rd. The other end of the resistor Rd is connected to the output of the charge pump circuit 2 as in a conventional PLL circuit.

FIG. 7 is a time chart showing the operation of the PLL circuit of this embodiment. In the embodiment, the reference clock signal K
The frequency dividing circuit 8 divides R by 8 to generate a sampling pulse SB. The error voltage output from the charge pump circuit 2 is controlled by the charge pump operation in the cycle of the reference signal R (comparison signal V) as shown in FIG. If this error voltage VC is used as a holding voltage of the resistor Rd via the voltage buffer, the resistor Rd has no meaning. When the error voltage VC of FIG. 7 is sampled at the timing of the pulse SB, only the error voltages Va and Vb at the sampling point are output as the signal VS, and high-speed voltage fluctuation is suppressed. This is an operation in which the error voltage VC is held by a capacitor. Therefore, if this voltage VS is used as a holding voltage of the resistor Rd via a voltage buffer, an AC conversion gain setting circuit of a PLL circuit can be realized.

In the frequency dividing circuit 8, the reference clock KR
Is divided into sampling pulses, but the present invention is not limited to this, and the frequency of the reference clock KV may be divided and used as sampling pulses.

As described above, in the PLL circuit of this embodiment, the operation of the PLL circuit can be completed in the LSI, so that jitter due to external noise can be suppressed, and unnecessary (significant) IC pins are unnecessary for the LSI user. do not need.

[0027]

As described above, according to the present invention,
Jitter due to external noise can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a circuit diagram of a general charge pump circuit;

FIG. 3 is a circuit diagram of a charge pump circuit used in the embodiment.

FIG. 4 is a diagram showing waveforms at various parts in the circuits of FIGS. 2 and 3;

FIG. 5 is a circuit diagram of a sampling circuit.

FIG. 6 is a circuit diagram of a voltage buffer.

FIG. 7 is a time chart showing the operation of the embodiment.

FIG. 8 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 2 Charge pump circuit 7 Sampling circuit Rd AC conversion gain setting resistor

Claims (4)

[Claims] 1. A PLL circuit comprising an LSI having a charge pump circuit, wherein an output of the charge pump circuit is connected to the other end of an AC conversion gain setting resistor connected to an output terminal of the charge pump circuit. A voltage supplied by a sampling circuit. 2. The PLL circuit according to claim 1, wherein the sampling circuit divides a frequency of a reference clock input to the PLL circuit and samples the frequency as a sampling pulse. 3. The PLL circuit according to claim 1, wherein said charge pump circuit is a differential signal. 4. A PLL circuit which receives a first clock signal and generates a second clock signal having a frequency which is a multiple of the frequency of the first clock signal, wherein an output terminal of a charge pump circuit included in the PLL circuit is provided. Connect a resistance element,
A voltage sampling circuit in which an output terminal of the charge pump circuit is connected to an input terminal; a signal having a frequency division cycle of the first clock signal or the second clock signal is input to the voltage sampling circuit as a sampling pulse; A PLL circuit, wherein a voltage signal based on an output signal of the voltage sampling circuit is supplied to the other end of the resistance element.