JP2002043930A - Clock signal generator and microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock signal generator that can reduce power consumed by its circuit sections not substantially requiring operations. SOLUTION: A frequency divider side selection output means 35 stops the operation of a frequency divider circuit 24 as required and allows a selector 25 to output a reference clock signal in place of a 1/N frequency division clock signal to a multiplier circuit 26 in this case. Furthermore, a multiplier side selection output means 36 stops the operation of the multiplier circuit 26 as required and allows a selector 27 to output the 1/N frequency division clock signal from the frequency divider 24 or a reference clock signal outputted from an external oscillation section 23 externally without any modification in place of an (M/N) multiple clock signal in this case.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency dividing circuit for dividing a reference clock signal by N, and multiplying a frequency divided clock signal outputted from the frequency dividing circuit by M to an externally (M / N) multiplied clock. The present invention relates to a clock signal generator including a multiplying circuit for outputting a signal.

[0002]

FIG. 4 is a functional block diagram showing an example of the configuration of a clock signal generator including both a frequency dividing circuit and a multiplying circuit. External oscillator 1
The reference clock signal having the frequency f0 is output to the frequency multiplying circuit 3 through the frequency dividing circuit 2. In the frequency dividing register 4 and the frequency multiplying register 5, a frequency dividing value N and a frequency multiplying value M are set by a CPU (not shown) via a cis address bus 6 and a data bus 7.

[0003] The clock signal generator 8 thus configured
Can generate both a clock signal with a frequency lower than the frequency f0 of the reference clock signal and a clock signal with a higher frequency. Further, the frequency of the clock signal to be output to the outside is set to f0 * (M / N) by a combination of the setting of the frequency dividing value N in the frequency dividing circuit 2 in the preceding stage and the setting of the multiplying value M in the frequency multiplying circuit 3 in the subsequent stage. It is possible to change variously as follows.

However, depending on the application, for example, a case where it is not necessary to use the multiplier circuit 3 to obtain a desired clock signal frequency is also assumed. In order to generate a clock signal with a higher frequency, the multiplier circuit 3 may generate a clock signal with an extremely high frequency as compared with the frequency of the reference clock signal in some cases, and its power consumption is not small. . Therefore, when the multiplying circuit 3 operates even though it is not necessary to use the multiplying circuit 3, there is a problem that the amount of wasteful power consumption increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a clock signal generator capable of reducing power consumed by a circuit part which does not need to be operated substantially. It is in.

[0006]

According to the clock signal generator of the present invention, the multiplying-side selection output means stops the operation of the multiplying circuit as necessary, and at that time, (M /
N) The frequency-divided clock signal output from the frequency-dividing circuit instead of the multiplied clock signal is directly output to the outside. Therefore, when a desired clock signal can be obtained only by using the frequency divider, the operation of the frequency multiplier can be stopped, so that wasteful power consumption by the frequency multiplier can be reduced.

According to the clock signal generator of the present invention, the frequency dividing side selection output means stops the operation of the frequency dividing circuit as required, and at that time, replaces the frequency divided clock signal with the reference clock signal. Is output to the multiplier circuit as it is. Therefore, when a desired clock signal can be obtained only by using the frequency multiplier, the operation of the frequency divider can be stopped, so that wasteful power consumption by the frequency divider can be reduced.

According to the third aspect of the present invention, the clock signal generating apparatus of the first aspect also includes a frequency dividing side selection output means to stop the operation of the frequency dividing circuit as necessary. The operation of the multiplying circuit and / or the frequency dividing circuit can be stopped, and wasteful power consumption can be further reduced.

According to the clock signal generating device of the present invention, the multiplying side selection output means stops the operation of the multiplying circuit when the multiplied value set in the multiplied value setting means is "1". Therefore, the user can stop the operation of the multiplier circuit only by setting the specific value in the multiplier value setting means.

According to the clock signal generating device of the present invention, the frequency-dividing-side selecting and outputting means operates the frequency dividing circuit when the frequency dividing value set in the frequency dividing value setting means is "1". Stop. Therefore, the user can stop the operation of the frequency dividing circuit only by setting the specific value in the frequency dividing value setting means.

According to the clock signal generator of the present invention, the selection output means is provided when the multiplication value set in the multiplication value setting means is equal to the division value set in the division value setting means. , Stop the operation of the multiplying circuit and / or the frequency dividing circuit. That is, when the operation of both the multiplication circuit and the frequency divider circuit is configured to be stopped, if the multiplication value and the frequency division value are set to the same value, the multiplication circuit and the frequency division circuit are operated. No need. Therefore, when such a setting is performed, the operation of the multiplying circuit and / or the frequency dividing circuit can be appropriately stopped.

According to the clock signal generator of the present invention, the multiplying circuit is constituted by using a DPLL circuit. That is, the DPLL circuit includes a ring oscillator or the like to generate a clock signal of an extremely high frequency. Therefore, the oscillation stabilization time is short, the oscillation operation can be started in an extremely short time from the oscillation stop state, and there is an advantage that the operation as the multiplication circuit can be started quickly, but the power consumption during operation is low. Will be relatively high. Therefore, by applying the configuration according to any one of claims 1, 3, 4 and 6 to a multiplier circuit configured using a DPLL circuit, the effect of reducing power consumption of the present invention can be exhibited effectively. Can be.

According to an eighth aspect of the present invention, since the microcomputer is provided with the clock signal generating device according to any one of the first to seventh aspects, depending on the setting of the clock signal used in the microcomputer, It is possible to reduce power consumption.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a functional block diagram illustrating an example of an electrical configuration of the single-chip microcomputer. The microcomputer (microcomputer) 11 mainly includes a CPU 12,
ROM 13 and R accessed by the CPU 12
AM14, clock generator (clock signal generator) 1
5, serial communication circuit 16, PWM circuit 17, timer 1
And a plurality of peripheral circuits 20 including an A / D converter 19 and the like. The CPU 12 and each peripheral circuit 20 are connected via a common address bus 21 and data bus 22.

The clock generator 15 is configured to supply a common clock signal MCK to the CPU 12 and the peripheral circuit 20. The CPU 12 and the peripheral circuit 20 operate in synchronization with the clock signal MCK. I have. The clock generator 15 is configured so that the frequency of the clock signal MCK can be variably set by the CPU 12.

FIG. 1 is a functional block diagram showing a detailed configuration of the clock generator 15. The reference clock signal of frequency f0 output from the external oscillating unit 23 is
, As well as directly to the selector 25 on the frequency dividing side and the selector 27 on the multiplying side. The N-divided clock signal output from the frequency dividing circuit 24 is
5 is provided to the multiplication circuit 26. The N-divided clock signal output via the selector 25 is also directly supplied to the selector 27. The M / N multiplied clock signal output from the multiplying circuit 26 is externally output as a clock signal MCK via a selector 27.

In a frequency dividing register (frequency dividing value setting means) 28 and a frequency multiplying register (multiplied value setting means) 29, the CPU 12 sets a frequency dividing value N and a frequency multiplying value M via an address bus 21 and a data bus 22. (N, M = 1, 2, 3,...). The frequency dividing value N set in the frequency dividing register 28 is given to the frequency dividing circuit 24,
It is also provided to comparators (magnitude comparators) 30 and 31. The multiplication value M set in the multiplication register 29 is supplied to the multiplication circuit 26 and also to the comparators 31 and 32.

The comparator 30 compares whether or not the frequency division value N is equal to "1". If N = 1, the match signal ("YES", high level) is output to the OR gate 33. Output to one of the input terminals. The non-coincidence signal (“NO”, high level) of the comparator 30 is provided to the selector 25 as a selection switching signal. This mismatch signal is always output unless N = 1.

The selector 25 selects and outputs the N-divided clock signal supplied to the input port "1" when the mismatch signal is output, and outputs the input port "0" when the mismatch signal is not output. Is selectively output.

The comparator 32 compares whether the multiplication value M is equal to "1" or not, and outputs a match signal ("YE
S ") is output to one input terminal of the OR gate 34.
Further, the mismatch signal (“NO”) of the comparator 32 is given to the selector 27 as a first selection switching signal.

The comparator 31 compares whether the divided value N and the multiplied value M are equal or not, and outputs a coincidence signal ("YES") to the other input terminals of the OR gates 33 and 34. Output to Further, the non-coincidence signal (“N
O ”) is given to the selector 27 as a second selection switching signal.

When a mismatch signal is output from the comparators 31 and 32, the selector 27 inputs the input port "1".
And outputs the (M / N) multiplied clock signal supplied to the input port "0" if the mismatch signal is not output from the comparator 32. . Further, when the mismatch signal is not output from the comparator 31, the reference clock signal supplied to the input port "0 '" is selectively output.

The output signals of the OR gates 33 and 34 are supplied to a frequency dividing circuit 24 and a multiplying circuit 26, respectively. The frequency dividing circuit 24 and the multiplying circuit 26 are provided with an OR gate 33,
When the output signal level of 34 becomes high, the frequency division operation and the multiplication operation of the input clock signal are stopped.

The frequency dividing circuit 24 is constituted by a plurality of stages of flip-flops and the like. Although the detailed configuration of the multiplying circuit 26 is not shown, a DPLL (Digital Phase Locked)
Loop) circuit is applied, data latch,
It is provided with a control circuit, a counter, a digitally controlled oscillator having a ring oscillator, and the like (for a detailed configuration, see, for example, JP-A-8-265111).

The operation is briefly described. The multiplied value M set in the multiplying register 29 is set in the data latch, and the control circuit sets the control cycle based on, for example, the N-divided clock signal output from the selector 25. It counts and outputs a control signal. The counter counts the N-divided clock signal cycle by the high-speed clock signal output from the ring oscillator, and the digitally controlled oscillator performs timing control based on the count value and the multiplied value M (M / N ) Output the multiplied clock signal as MCK. That is, the multiplying circuit 26 has a configuration in which the phase synchronization function part in the DPLL circuit is omitted.

In the above configuration, the selector 25,
The comparators 30 and 31, and the OR gate 33 constitute a frequency-dividing-side selection output means 35, and the selector 27 and the comparator 31
, 32, and an OR gate 34
Is composed.

Next, the operation of the present embodiment will be described. <Clock signal MCK = (M / N) multiplied clock signal> First, the clock signal MCK is set to (M / N) of the reference clock signal.
/ N) The case of generating as a multiplied clock signal will be described. In this case, the CPU 12 sets an arbitrary frequency division value N in the frequency division register 28 of the clock generator 15 and
In the multiplication register 29, an arbitrary multiplication value M (however, N is not M) is set. At this time, the comparison results of the comparators 30 to 32 are as follows.

Therefore, the frequency dividing circuit 24 divides the frequency of the reference clock signal by N and outputs it to the selector 25,
Outputs the N-divided clock signal to the multiplication circuit 26. The multiplying circuit 26 multiplies the input N-divided clock signal by M and outputs the multiplied clock signal to the selector 27.
Outputs the (M / N) multiplied clock signal to the outside as MCK (supplies it to the internal circuit of the microcomputer 11).

<Clock signal MCK = N-divided clock signal> Next, a case where the clock signal MCK is generated as a N-divided clock signal of the reference clock signal will be described (that is, M multiplication is not performed). In this case, the CPU 12 stores an arbitrary frequency division value N in the frequency division register 28 of the clock generator 15.
(However, N = 1 is not set), and a multiplication value M = 1 is set in the multiplication register 29. At this time, the comparison results of the comparators 30 to 32 are as follows.

Accordingly, the frequency dividing circuit 24 divides the reference clock signal by N and outputs it to the selector 25 in the same manner as described above, and the selector 25 outputs the N-divided clock signal to the multiplying circuit 26. On the side of the multiplier circuit 26, since the comparator 32 outputs a coincidence signal, the output signal level of the OR gate 34 becomes high, and the multiplier circuit 26 stops the multiplying operation.
At this time, the multiplying circuit 26 specifically stops the oscillation operation of the built-in ring oscillator.

A plurality (for example, 32) of ring oscillators
Since the inverter gates of the stages are connected on a ring, and the oscillation frequency thereof is extremely high, the power consumption is relatively large. Therefore, the effect of reducing power consumption by stopping the oscillation operation of the ring oscillator is significant.

Then, since the comparator 32 stops outputting the non-coincidence signal, the selector 27 selects N on the input port "0" side.
A divided clock signal is selected, and the N-divided clock signal is output to the outside as MCK.

<Clock Signal MCK = M-Multiplied Clock Signal> Next, a case where the clock signal MCK is generated as an M-multiplied clock signal of the reference clock signal will be described (that is, N frequency division is not performed). In this case, the CPU 12 sets the frequency division value N = 1 in the frequency division register 28 of the clock generator 15 and sets the arbitrary multiplication value M in the frequency multiplication register 29.
(However, M is not 1) is set. At this time, the comparison results of the comparators 30 to 32 are as follows.

In this case, on the side of the frequency dividing circuit 24, the comparator 3
Since 0 outputs a coincidence signal, the output signal level of the OR gate 33 becomes high, and the frequency dividing circuit 24 stops the frequency dividing operation. Specifically, the supply of the reference clock signal to the built-in flip-flop is stopped. Further, since the comparator 30 stops outputting the mismatch signal, the selector 25 selects the reference clock signal on the input port “0” side and outputs it to the frequency multiplier 26.

The multiplying circuit 26 multiplies the input reference clock signal by M and outputs it to the selector 27. The selector 27 outputs the M multiplied clock signal to the outside as MCK.

<Clock signal MCK = reference clock signal> Next, the reference clock signal is directly used as the clock signal MCK.
(Namely, dividing by N, M
No multiplication is performed). In this case, the CPU 12 operates the frequency divider register 28 and the multiplication register 2 of the clock generator 15.
In 9, a division value N = 1 and a multiplication value M = 1 are set. At this time, the comparison results of the comparators 30 to 32 are as follows.

Accordingly, the frequency dividing circuit 24 stops the frequency dividing operation in the same manner as described above, and the selector 25 selects the reference clock signal and outputs it to the frequency multiplying circuit 26. Also, the multiplication circuit 26
Stops the multiplying operation in the same manner as in (1), and the selector 27 selects the reference clock signal provided from the external oscillating unit 23 and outputs it as MCK to the outside. In this case, both the comparators 32 and 31 stop outputting the non-coincidence signal, but the selector 27 preferentially selects the reference clock signal on the input port “0 ′” side and outputs it to the outside. Has become.

When the reference clock signal is directly generated as the clock signal MCK, the frequency dividing register 28 and the frequency multiplying register 29 are set to the frequency dividing value N = 1 and the frequency multiplying value M = 1. Without limitation, N = M (= 2, 3,
4,...). At this time, each of the comparators 30 to 3
The comparison result of No. 2 is as follows.

In this case, since the comparator 31 outputs a coincidence signal, the output signal levels of the OR gates 33 and 34 are both high, the frequency dividing circuit 24 stops the frequency dividing operation, and the frequency multiplying circuit 26 performs the frequency multiplying operation. To stop. Further, since the comparator 31 stops outputting the mismatch signal, the selector 27 selects the reference clock signal provided from the external oscillating unit 23 and outputs it as MCK to the outside.

As described above, according to the present embodiment, the frequency dividing side selection output means 35 stops the operation of the frequency dividing circuit 24 as necessary, and at that time, the reference clock is used instead of the N frequency-divided clock signal. The signal is output to the multiplying circuit 26, and the multiplying-side selection output means 36 stops the operation of the multiplying circuit 26 as necessary. At that time, the frequency dividing circuit 24 replaces the (M / N) multiplied clock signal. The N-divided clock signal output from the controller or the reference clock signal output from the external oscillating unit 23 is directly output to the outside.

That is, when a clock signal of a desired frequency can be obtained only by using one of the multiplying circuit 26 and the dividing circuit 24, the operation of the dividing circuit 24 and the multiplying circuit 26 is selectively stopped. Can be done. When the frequency of the reference clock signal is a desired frequency, the operations of the frequency dividing circuit 24 and the multiplying circuit 26 can be stopped at the same time.

Therefore, wasteful power consumption by the frequency dividing circuit 24 and the multiplying circuit 26 can be reduced. Also,
Since the multiplying circuit 26 is configured using the DPLL circuit, the multiplying operation can be started quickly from the stop state. Then, the effect of reducing the power consumption when the operation of the multiplying circuit 26 is stopped can be effectively achieved.

When the frequency division value N set in the frequency division register 28 is "1", the frequency division side selection output means 35 stops the operation of the frequency division circuit 24, and the multiplication side selection output means 3
6 indicates that the multiplication value M set in the multiplication register 29 is “1”.
In this case, the operation of the frequency multiplying circuit 26 is stopped. Therefore, the user can stop the operations of the frequency dividing circuit 24 and the frequency multiplying circuit 26 only by setting specific values in the frequency dividing register 28 and the frequency multiplying register 29.

Further, according to the present embodiment, the selection output means 3
5, 36 can stop the operation of the frequency divider 24 and the frequency multiplier 26 even when the frequency M set in the frequency multiplier 29 is equal to the frequency N set in the frequency divider 28. it can. Since the microcomputer 11 includes the clock generator 15, the power consumption of the microcomputer 11 can be reduced depending on the setting of the clock signal used in the microcomputer 11.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. explain. The clock generator (clock signal generator) 37 of the second embodiment includes a select register 38.
The select register 38 is used to select whether or not to stop the operation of each of the frequency dividing circuit 24 and the frequency multiplying circuit 26 independently of the setting of the frequency dividing value N and the frequency multiplying value M for the frequency dividing register 28 and the frequency multiplying register 29. This is a register for performing directly. The select register 38 includes the frequency division register 28
The setting is performed by the CPU 12 via the address bus 21 and the data bus 22 in the same manner as the multiplication register 29.

The output of the frequency division stop setting bit of the select register 38 is given to the additional input terminal of the OR gate 33A obtained by adding one input terminal to the OR gate 33 of the first embodiment, and the AND gate 39 Are also supplied to the negative logic input terminal. The other positive logic input terminal of the AND gate 39 is supplied with a mismatch signal of the comparator 30. The output terminal of the AND gate 39 is connected to the selector 25.
Is provided as a selection switching signal.

On the other hand, the output of the multiplication stop setting bit of the select register 38 is given to the additional input terminal of the OR gate 34A obtained by adding one input terminal to the OR gate 34 of the first embodiment, and the AND gate 34A It is also provided to 40 negative logic input terminals. The other positive logic input terminal of the AND gate 40 is supplied with the mismatch signal of the comparator 32, and the output terminal of the AND gate 40 is supplied to the selector 27 as a first selection switching signal.

The output of the division stop setting bit and the output of the multiplication stop setting bit of the select register
Each of the input terminals of the D gate 41 is
The output terminal of the ND gate 41 is supplied to the selector 27 as a second selection switching signal via the negative logic input terminal of the AND gate 42. The other input terminal of the AND gate 42 is supplied with a mismatch signal of the comparator 31.

In the above configuration, the selector 25,
The comparators 30 and 31, the OR gate 33A, the select register 38, and the AND gate 39 are connected to the frequency-dividing-side selection output means 4.
3. The selector 27, comparators 31 and 32, OR gate 34A, select register 38, A
ND gate 40, NAND gate 41, AND gate 4
Reference numeral 2 denotes a multiplying-side selection output unit 44.

Next, the operation of the second embodiment will be described. In the second embodiment, the frequency dividing circuit 24 and the frequency multiplying circuit 2 are set by setting the frequency dividing value N and the frequency multiplying value M just like the first embodiment.
6 Each operation can be stopped. In addition, the operation of each of the frequency dividing circuit 24 and the frequency multiplying circuit 26 can be stopped by the CPU 12 setting the frequency dividing stop setting bit and the frequency multiplying stop setting bit of the select register 38. .

That is, when the frequency division stop setting bit of the select register 38 is set, the output signal level of the OR gate 33A becomes high, and the operation of the frequency division circuit 24 stops. Further, since the output signal of the AND gate 39 becomes low level, the selector 25 selects the reference clock signal on the input port “0” side and outputs it to the multiplication circuit 26. On the other hand, when the multiplication stop setting bit of the select register 38 is set, the output signal level of the OR gate 34A becomes high, so that the operation of the multiplication circuit 26 is stopped. Also, A
Since the output signal of the ND gate 40 is at a low level, the selector 27 selects the N-divided clock signal on the input port “0” side and outputs it as a clock signal MCK to the outside.

When both the division stop setting bit and the multiplication stop setting bit of the select register 38 are set at the same time, the output signal of the AND gate 41 goes high and the output signal of the AND gate 42 goes low. The selector 27 selects a reference clock signal on the input port “0 ′” side and outputs it as a clock signal MCK to the outside.

As described above, according to the second embodiment, the clock generator 37 is provided with the select register 38 so that the CPU
12 sets the frequency division stop setting bit and the frequency multiplication stop setting bit of the select register 38, respectively, so that the frequency dividing circuit 2
4. The operation of each of the multiplying circuits 26 is directly stopped. Therefore, when the operations of the frequency dividing circuit 24 and the multiplying circuit 26 are stopped, the operations can be stopped by a simple setting without considering the setting of the frequency dividing value N and the multiplying value M.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. In the first embodiment, the comparator 31 may be omitted. Even if only one of the dividing-side selecting and outputting means 35 and the multiplying-side selecting and outputting means 36 in the first embodiment or the dividing-side selecting and outputting means 43 and the multiplying-side selecting and outputting means 44 in the second embodiment is provided. good. In the second embodiment, the comparators 30 to 32 may be deleted.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a detailed electrical configuration of a clock generator according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram illustrating an example of an electrical configuration of a single-chip microcomputer.

FIG. 3 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

FIG. 4 is a diagram corresponding to FIG. 1 showing a conventional technique.

[Explanation of symbols]

11 is a microcomputer, 15 is a clock generator (clock signal generator), 24 is a frequency dividing circuit, 26 is a multiplying circuit, 28 is a frequency dividing register (frequency dividing value setting means), 29
Is a multiplication register (multiplier value setting means), 35 is frequency division side selection output means, 36 is multiplication side selection output means, 37 is a clock generator (clock signal generator), 43 is frequency division side selection output means, and 44 is 3 shows a multiplying side selection output means.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hideaki Ishihara 1-1-1 Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (Reference) 5B011 HH02 LL13 5B079 AA07 BA04 BA11 BB04 DD03 DD04 5J039 AC01 AC15 AC18 KK01 KK27 MM04

Claims (8)

[Claims] 1. A frequency dividing circuit for dividing a reference clock signal by N (N is a natural number of 2 or more), and a frequency dividing clock signal output from the frequency dividing circuit to M (M
Is a natural number of 2 or more) and outputs a (M / N) multiplied clock signal to the outside. The operation of the multiplying circuit is stopped if necessary.
A multiplying-side selection output unit configured to output the frequency-divided clock signal output from the frequency-dividing circuit as it is in place of the (M / N) frequency-multiplied clock signal. Signal generator. 2. A frequency dividing circuit for dividing a reference clock signal by N (N is a natural number of 2 or more), and a frequency dividing clock signal output from the frequency dividing circuit by M (M
Is a natural number of 2 or more) and outputs a (M / N) multiplied clock signal to the outside, and stops the operation of the frequency dividing circuit as necessary.
A clock signal generation device comprising: a frequency-divider-side selection output unit configured to directly output the reference clock signal to the multiplying circuit instead of the frequency-divided clock signal. 3. A frequency-divider-side selection output configured to stop the operation of the frequency-divider circuit as necessary and output the reference clock signal to the frequency multiplier circuit as it is in place of the frequency-divided clock signal. 2. The clock signal generator according to claim 1, further comprising: 4. The multiplying circuit further comprises multiplying value setting means for setting a multiplying value of the frequency-divided clock signal, and the multiplying side selection output means sets the multiplying value set in the multiplying value setting means to “1”. 4. The clock signal generating device according to claim 1, wherein the operation of the multiplying circuit is stopped when "." 5. The frequency dividing circuit further comprises frequency dividing value setting means for setting a frequency dividing value of the frequency dividing clock signal, wherein the frequency dividing side selection output means is set to frequency dividing value setting means. 3. The clock signal generation device according to claim 2, wherein when the frequency division value is "1", the operation of the frequency division circuit is stopped. 6. A multiplication value setting means for setting a multiplication value of the divided clock signal in the multiplication circuit, and a division value for setting a division value of the divided clock signal in the frequency dividing circuit. Setting means, wherein the selection output means, when the multiplied value set in the multiplied value setting means is equal to the divided value set in the divided value setting means, the multiplying circuit and / or 4. The clock signal generator according to claim 3, wherein the operation of the frequency dividing circuit is stopped. 7. The clock signal generator according to claim 1, wherein the multiplying circuit is configured using a DPLL circuit. 8. A microcomputer comprising the clock signal generator according to claim 1. Description: