JP2002033681A - Digital correlation unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital correlation unit that can realize respective correlation arithmetic operations for in-phase and quadrature components with common multipliers and adders so as to halve the number of both the multipliers and the adders having been required for the conventional digital correlation unit thereby reducing the scale of gates. SOLUTION: A digital correlation circuit is provided with a 1st selection means that selects an in-phase component or a quadrature component, a 1st storage means that stores a 1st spread code corresponding to the in-phase component of a received signal with a spread code length L, a 2nd storage means that stores a 2nd spread code corresponding to the quadrature component of the received signal with the spread code length L, L-sets of 2nd selection means that select either of the 1st and 2nd spread codes, L-sets of multipliers multiply the selection result by the 1st selection means with the selection result by the 2nd selection means, (L-1)-sets of 2-stage transfer type shift registers, (L-2)-sets of adders, a register means with a summing function that receives an output of the shift register placed at a head receiving an output of the corresponding multiplier and receives a sum of outputs of the shift registers placed at the next and succeeding stages corresponding to the multipliers and an output of the shift register placed at the pre-stage, an output adder that sums an output of a final stage of the register means with the summing function and an output of the corresponding multiplier, and in-phase/quadrature component registers alternately storing an output of the output adder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital correlation circuit suitable for use in synchronous processing (synchronization acquisition (establishment) and synchronization tracking) of a spread spectrum signal.

[0002]

2. Description of the Related Art Here, code division multiplexing (CDMA) is a typical example of a spread spectrum system.
ltiple Access) A communication system will be described. In general, a receiver of a wireless communication system using the CDMA system requires a phase locked loop. A correlator is used for this kind of phase synchronization circuit. In recent years, a digital correlator constituted by a digital shift register has attracted attention. Regarding the configuration of the phase locked loop circuit using such a digital correlator, for example, “Coherent matched filter demodulation method spread spectrum communication apparatus (Hamamoto,
Others: IEICE 1985 SAT85-16) "
Has been reported.

According to the above document, a digital correlator is
The maximum output is obtained when all the chips match with each chip value of the input spread code (hereinafter referred to as “PN code”) and the nature of the PN code prepared on the local side. Call. This matched pulse is 1
Since it appears only once in the PN frame, the timing of the PN frame can be detected by detecting the matched pulse.

However, in a real system, since noise is mixed in a communication path, there is a possibility that a pulse due to noise other than the matched pulse is generated. Thus, in order to detect a true matched pulse from the noise pulses, the correlator outputs of the in-phase component and the quadrature component of the input PN code and the local PN code are obtained, and the sum of squares of these orthogonal components is obtained. After that, the cyclic integration of the sum of squares is further calculated, and a matched pulse is detected based on the calculation result. This configuration is shown in FIG.

In FIG. 2, reference numeral 301 denotes a digital correlator for an in-phase component (hereinafter, referred to as an "I component").
2 is a digital correlator for orthogonal components (hereinafter referred to as “Q component”), 303 and 304 are square calculation circuits corresponding to the I component and Q component, and 305 is a square calculation circuit 30
An adder for adding the outputs of 3 and 304, 306 is a cyclic integration circuit for integrating the output of the adder 305, and 307 is a matched pulse detection circuit.

Here, the I component of the received signal dropped to the baseband is input to the digital correlator 301, and the correlation with the local PN code held inside the digital correlator 301 is calculated. The calculated correlation value is input to the corresponding square calculation circuit 303.

On the other hand, the Q component of the received signal dropped to the baseband is input to the digital correlator 302, and the correlation with the local PN code held inside the digital correlator 302 is calculated. The calculated correlation value is input to the corresponding square calculation circuit 304.

The I and Q components squared in each of the square calculation circuits 303 and 304 are added in an adder 305. This addition result is output to the cyclic integration circuit 306.
Is cyclically integrated the number of times determined in. Based on the result of the cyclic integration, a matched pulse detection circuit 307 detects a matched pulse using a maximum value determination method or a threshold value determination method.

The present invention particularly relates to the configuration of a digital correlator in FIG. The prior art includes, for example, one shown in FIG. FIG. 4 shows the case where the PN code length is 64. 4, reference numeral 401 denotes an input terminal of a digital input D, 402 denotes a spread code memory storing 64 chip values, and 40301 to 403.
64 is a multiplier corresponding to each bit of the spread code memory 402; 40401 to 40644 are registers;
02 to 40564 are adders.

In FIG. 4, a digital input D is input from an input terminal 401 in series for each chip value. Multipliers 40301 to 40364 multiply the one-chip value by the chip values P1 to P64 of the spreading code given from spreading code memory 402. First stage multiplier 40301
Is stored in the register 40491. on the other hand,
The multiplication results of multipliers 40302 to 40364 at the next and subsequent stages are provided to adders 40502 to 40564, and are added to the values held in registers 40401 to 40463 at the previous stage. Outputs of these adders 40502 to 40564 are respectively provided to registers 40402 to 4404 arranged at the subsequent stage.
0464. Note that the result of the correlation operation is output from the register 40465 located at the last stage.

[0011]

However, in the case of such a conventional technique, a digital correlator having a PN code length of L requires L multipliers and (L-1) adders. Since the digital correlator requires one I component and one Q component, 2 × L multipliers and 2 × L
(L-1) adders were required. For this reason, there was a problem that the gate scale was increased.

In addition, in the case of the prior art, to calculate the sum of squares of the correlation values of the I component and the Q component, and to take the square of the correlator output for each of the I component and the Q component, two A squarer was needed. For this reason, the gate scale also becomes large.

In order to simplify the circuit more than a squarer,
The square root of the sum of squares is obtained by the following approximate expression (1),
It can also be used for cyclic integration and matched pulse detection. However, even in this case, a circuit for calculating the absolute value of each of the I component and the Q component was required.
For this reason, the gate size also becomes large.

{(I ² + Q ² )} max (| I |, | Q |) + min (| I |, | Q |) / 2 (1)

[0015]

(A) In order to solve this problem, the digital correlation circuit according to the first aspect of the present invention comprises: (1) a first method for selecting an in-phase component or a quadrature component of a received baseband signal; Selecting means; (2) first storing means for storing a first spreading code corresponding to an in-phase component of a received signal having a spreading code length L having a value of +1 or -1; (3) +1
Or a second storage means for storing a second spreading code corresponding to an orthogonal component of a received signal having a spreading code length L having a value of -1; and (4) one of the first and second spreading codes. L second selecting means for selecting each bit; (5) L multipliers for multiplying the selection result of the first selector and the selection result of the second selector; (6) (L -1) two-stage transfer type shift registers and (L-2) adders, and the shift register arranged at the top receives the output of the corresponding multiplier and is arranged at the next and subsequent stages. The shift register further includes a register means with an addition function for inputting an addition result of the output of the corresponding multiplier and the output of the shift register arranged in the preceding stage, and (7) the output of the last stage of the register means with the addition function. An output adder for adding the output of the corresponding multiplier,
(8) A register for the in-phase component and a register for the quadrature component which alternately accumulate the output of the output adder are provided.

In the digital correlation circuit according to the first invention, each section is operated by an operation clock having a frequency twice as high as a change cycle of the reception baseband signal (in-phase component and quadrature component). Then, in the first half and the second half of the change cycle of the received baseband signal, the operation on the in-phase component and the operation on the quadrature component are alternately executed (for example, if the operation on the in-phase component is performed in the first half, If the calculation is performed on the orthogonal component and the calculation is performed on the orthogonal component in the first half, the calculation on the in-phase component is performed in the second half.

Here, since a two-stage transfer type shift register is used as the shift register into which the multiplication result or the addition result is input, the multiplication result or the addition result calculated by the current operation clock is stored in the first stage. The second stage holds the multiplication result or the addition result calculated and transferred one operation clock before.

Therefore, the output adder outputs a correlation value for the in-phase component and a correlation value for the quadrature component in the first and second half of the change cycle of the received baseband signal.

(B) In order to solve the problem, in the digital correlation circuit according to the second invention, (1) first selecting means for selecting an in-phase component or a quadrature component of a received baseband signal; ) A first storage means for storing a first spread code corresponding to an in-phase component of a received signal having a spread code length L having a value of +1 or -1; and (3) a spread code having a value of +1 or -1. Second storage means for storing a second spreading code corresponding to the orthogonal component of the received signal having a length L; and (4) L for selecting one of the first and second spreading codes for each bit.
(5) L multipliers for multiplying the selection result of the first selector and the selection result of the second selector,
(6) (L-1) two-stage transfer type shift registers and (L-
2) The number of adders is provided, and the shift register arranged at the head receives the output of the corresponding multiplier, and the shift registers arranged at the next and subsequent stages are arranged at the preceding stage with the output of the corresponding multiplier. (7) an output adder for adding the output of the last stage of the register means with the addition function and the output of the corresponding multiplier, and (8) an absolute value calculating means for calculating the absolute value of the output adder, (9) a register for the in-phase component and a register for the quadrature component which alternately accumulate the output of the absolute value calculating means, and (10) A comparator for comparing the contents of the register for the in-phase component and the register for the quadrature component; (11) a third selector for selecting a value determined to be large by the comparator; A fourth selector for selecting the determined value, and (13) a fourth selector. By shifting the output of the fourth selector right by one bit, a shift register for halving the output of the fourth selector is provided.

In the case of the digital correlation circuit according to the second aspect of the invention, the operation halfway is the same as that of the digital correlation circuit according to the first aspect.

That is, the operation on the in-phase component and the operation on the quadrature component are alternately executed in the first half and the second half of the change cycle of the received baseband signal (for example,
If the operation on the in-phase component is performed in the first half, the operation on the quadrature component is performed in the second half. If the operation on the quadrature component is performed in the first half, the operation on the in-phase component is performed in the second half.)

Since a two-stage transfer type shift register is used as the shift register to which the multiplication result or the addition result is input, the first stage holds the multiplication result or the addition result calculated by the current operation clock. The multiplication result or the addition result calculated and transferred one operation clock before is held in the second stage.

Therefore, the output adder outputs a correlation value for the in-phase component and a correlation value for the quadrature component in the first half and the second half of the change cycle of the received baseband signal. These correlation values are input to absolute value calculation means arranged at the subsequent stage of the output adder, and their absolute values are stored in a register for the in-phase component and a register for the quadrature component, respectively.

The correlation value stored in the register for the in-phase component and the correlation value stored in the register for the quadrature component are compared by a comparator, and a value determined to be larger as a result of the comparison is output from a third selector, and As a result, the value determined to be smaller is output from the fourth comparator. For example, if the correlation value for the in-phase component is output from the third selector, the correlation value for the quadrature component is output from the fourth selector.

The output of the fourth selector is further supplied to a shift register which multiplies the output by 1/2. Here, the outputs from the third selector and the fourth selector are the same as the two values forming the approximate expression for calculating the square root of the sum of squares of the in-phase component and the quadrature component. That is, the digital correlation circuit according to the second aspect of the invention operates as a digital correlation circuit of a system not using a squarer at a subsequent stage.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First Embodiment (A-1) Circuit Configuration FIG. 1 shows a first embodiment of the present invention. In FIG. 1, 101 is a digital correlator, 303 and 304 are square calculation circuits, 305 is an adder, 306 is a cyclic integration circuit,
307 is a matched pulse detection circuit. Figure 2 of these
The same blocks as in FIG. 2 are the same as those in FIG. That is, the only component unique to the present embodiment is the digital correlator 101.

In FIG. 1, the I component and the Q component of the received signal dropped to the baseband are input to the digital correlator 101. The I component correlation value output terminal and the Q component output terminal of the digital correlator 101 are connected to the input terminals of the square calculation circuits 303 and 304, respectively. Output terminals of the square calculation circuits 303 and 304 are connected to input terminals of the adder 305, respectively. The output terminal of the adder 305 is connected to the input terminal of the cyclic integration circuit 307, and the output terminal of the cyclic integration circuit 307 is connected to the matched pulse detection circuit 307.
Is connected to the input terminal of

FIG. 4 shows a detailed configuration of the digital correlator 101 which is a configuration unique to this embodiment. 4, reference numeral 201 denotes an I-component local PN code accumulator;
2 is a local PN code accumulator for the Q component, 203 is a first selector for selecting either the in-phase component or the quadrature component of the received baseband signal, and 20401 to 20464 are 2
A second selector for selecting one of the two PN codes;
20501 to 20564 are multipliers corresponding to each bit and multiplying the output of the first selector by the output of the second selector;
20602 to 20664 are multipliers 20502 to 2056
4, 20701 to 20763 are first registers forming the first stage of the two-stage transfer type shift register, and 20801 to 20863 are second registers forming the second stage of the two-stage transfer type shift register. , 20664 is a register for storing the correlation value of the in-phase component, and 20864 is a register for storing the correlation value of the quadrature component.

The baseband reception signal input in FIG. 4 is input to two input terminals of the first selector 203.

Here, the I-component local PN code accumulator 201 has a 64-bit width. That is, the spreading code length here is 64. Each bit of the PN code accumulator 201 stores a value of +1 or -1. In addition,
Each bit of the I-component local PN code accumulator 201 is connected to one input terminal of the second selectors 20401 to 20464.

One of the Q component local PN code accumulators 2
02 also has a 64-bit width. Each bit of the PN code accumulator 202 also stores a value of +1 or -1. Each bit of the PN code accumulator 202 is connected to the other input terminal of each of the second selectors 20401 to 20464.

Here, the control signal s of the first selection terminal 203
Control signals sel2 of the el1 and the second selectors 20401 to 20464 are input at timings shown in FIGS.

The output terminal of the first selector 203 is connected to the multiplier 2
0501-20564 and one input terminal of the second
Are connected to the other input terminals of the multipliers 20501 to 20564, respectively.

The first stage multiplier 20 out of the 64 multipliers
The output terminal of 501 is connected to the input terminal of the first register 20701. The output terminals of the second and subsequent multipliers 20502 to 20564 of the 64 multipliers are connected to one input terminals of the adders 20602 to 20664, respectively.

The output terminals of the second registers 20801 to 20863 are connected to the other input terminals of the adders 20602 to 20664, respectively. Adder 20602
To the output terminals of the first register 20.
702-20763.

The adder 20664 located at the last stage
Is output from a register 207 for storing the correlation value of the in-phase component.
Register 20864 for storing correlation values of 64 and orthogonal components
Is connected to the input terminal of

The output terminals of the first registers 20701 to 20763 constituting the first stage of the two-stage transfer type shift register are connected to the second registers 20801 to 2802 constituting the second stage.
0863 are connected to their respective input terminals.

Here, the first registers 20701 to 20701
763 and the second register 20801 to 20863, the register 20768 for storing the correlation value of the in-phase component, and the register 20864 for storing the correlation value of the quadrature component, the operation clock of which is twice as fast as the chip clock of the input data. It is input (FIG. 5A).

The enable signal EN1 of the register 20768 for storing the correlation value of the in-phase component and the enable signal EN2 of the register 20864 for storing the correlation value of the quadrature component.
Are input at the timings shown in FIGS. 5 (F) and 5 (G).

(A-2) Correlation Value Calculation Operation Now, I1, I
, I3... Are sequentially given, and Q1, Q
2, Q3... Are sequentially given.

At this time, the contents of the first and second registers shown in FIG. 4 and the contents of the in-phase component and quadrature component correlation value storage registers are as shown in FIG. Here, the operation clocks applied to these registers are as shown in FIG.
As shown in FIG. 5, the frequency has twice the change cycle of the input data (FIGS. 5B and 5C). It is also assumed that the enable signals supplied to the in-phase component correlation value storage register 20768 and the quadrature component correlation value storage register 20864 change at the timing shown in FIG.

As shown in FIG. 6, registers 20768 for storing the correlation values of the in-phase components have l1-l64, l2-l.
The correlation values of the I component in the 64-chip section such as 65, 13 to 166... Are sequentially stored. Similarly, the last stage 20864 of the second register has Q1-Q64, Q2-Q65,
Correlation values of the Q component in the 64-chip section, such as Q3 to Q66, are sequentially stored.

These values are the same as those calculated by using two digital correlators having the configuration shown in FIG.

(A-3) Effects of the First Embodiment As described above, if the digital correlator having the configuration according to the present embodiment is used, the digital correlator in the receiver of the radio communication system using the CDMA system has the following advantages. I component and Q
The calculation of the correlation value of the components can be calculated using the same multiplier and adder, and both the number of adders and the teaching of the multiplier can be halved compared to the conventional circuit. Thus, a significant reduction in gate size can be realized.

(B) Second Embodiment (B-1) Circuit Configuration FIG. 7 shows a second embodiment of the present invention. 7, 701 is a digital correlator, 305 is an adder, 30
6 is a cyclic integration circuit, and 307 is a matched pulse detection circuit. The difference from the first embodiment is that there is no square calculation circuit provided for each of the I component and the Q component. That is, the second embodiment describes a digital correlator 701 of a system in which a squarer is not arranged at the subsequent stage.

In FIG. 7, the I component and the Q component of the received signal dropped to the baseband are input to a digital correlator 701. The I component correlation value output terminal and the Q component output terminal of the digital correlator 701 are connected to the input terminal of the adder 305. An output terminal of the adder 305 is connected to an input terminal of the cyclic integration circuit 307.
Is connected to the input terminal of the matched pulse detection circuit 307.

FIG. 8 shows a detailed configuration of the digital correlator 701 which is a configuration unique to this embodiment. In FIG. 8, reference numeral 201 denotes an I-component local PN code accumulator;
2 is a local PN code accumulator for the Q component, 203 is a first selector for selecting either the in-phase component or the quadrature component of the received baseband signal, and 20401 to 20464 select one of the two PN codes. A second selector, 2
Numerals 0501 to 20564 correspond to each bit, and are multipliers for multiplying the output of the first selector and the output of the second selector, 2
0602 to 20663 are multipliers 20502 to 20564
, 20701 to 20763 are first registers constituting the first stage of the two-stage transfer type shift register,
20801 to 20864 are second registers constituting the second stage of the two-stage transfer type shift register, 809 is an absolute value calculation circuit for obtaining the absolute value of the output of the adder 20664 at the last stage, and 20765 is the correlation value of the in-phase component. A register for storing the absolute value, a register for storing the absolute value of the orthogonal component correlation value, a comparator for comparing the magnitude of the value of the register with the value of the register,
Numeral 11 denotes a third selector for selectively outputting the larger correlation value, and 812 a fourth selector for selectively outputting the smaller correlation value.
Is a shifter (1/2 multiplier) that shifts the output of the fourth selector 812 right by one bit.

In FIG. 8, the same parts as those in FIG. 4 are denoted by the same reference numerals. That is, the difference from the first embodiment is the configuration subsequent to the adder 20664 at the last stage.

The baseband reception signal input in FIG. 8 is input to two input terminals of the first selector 203.

The I-component local PN code accumulator 201 has a width of 64 bits. That is, also in this embodiment, the spread code length is 64. PN code storage 2
A value of +1 or -1 is stored in each bit of 01. Each bit of the I-component local PN code accumulator 201 is connected to one input terminal of each of the second selectors 20401 to 20464.

One local PN code accumulator 2 for Q component
02 also has a 64-bit width. Each bit of the PN code accumulator 202 also stores a value of +1 or -1. Each bit of the PN code accumulator 202 is connected to the other input terminal of each of the second selectors 20401 to 20464.

Here, the control signal s of the first selector 203
Control signals sel2 of the el1 and the second selectors 20401 to 20464 are input at timings shown in FIGS.

The output terminal of the first selector 203 is connected to the multiplier 2
0501-20564 and one input terminal of the second
Are connected to the other input terminals of the multipliers 20501 to 20564, respectively.

The first stage multiplier 20 of the 64 multipliers
The output terminal of 501 is connected to the input terminal of the first register 20701. 64 multipliers 20502-20
The output terminals of 564 are respectively connected to adders 20602 to 206.
64 is connected to one input terminal.

The output terminals of the second registers 20801 to 20863 are connected to the other input terminals of the adders 20602 to 20664, respectively. Adder 20602
To the output terminals of the first register 20.
702-20763.

The adder 20664 located at the last stage
Is connected to the input terminal of the absolute value calculation circuit 809. An output terminal of the absolute value calculation circuit 809 is connected to an input terminal of a register 20768 for storing a correlation value of an in-phase component and a register 20864 for storing a correlation value of a quadrature component.

The output terminals of the first registers 20701-20763 forming the first stage of the two-stage transfer type shift register are connected to the second registers 20801-2 formed of the second stage.
0863 are connected to their respective input terminals.

Here, the first registers 20701 to 20701
763 and the second register 20801 to 20863, the register 20768 for storing the correlation value of the in-phase component, and the register 20864 for storing the correlation value of the quadrature component, the operation clock of which is twice as fast as the chip clock of the input data. It is input (FIG. 5A).

The enable signal EN1 of the register 20864 for storing the correlation value of the in-phase component and the enable signal EN2 of the register 20864 for storing the correlation value of the quadrature component.
Are input at the timings shown in FIGS. 5 (F) and 5 (G).

Register 207 for storing the correlation value of the in-phase component
The output of 64 is connected to one input terminal of a comparator 810, a third selector 811, and a fourth selector 812. On the other hand,
The output of the orthogonal component correlation value storage register 20864 is connected to the other input terminals of the comparator 810, the third selector 811 and the fourth selector 812.

The comparison result in the comparator 810 is connected from the output terminal to the control signal input terminals of the third selector 811 and the fourth selector 812. The output terminal of the fourth selector 812 is connected to the input terminal of the one-pit right shifter 813. An output terminal of the third selector 811 and an output terminal of the 1-bit right shifter 813 are connected to the adder 305 as outputs of the digital correlator 701, respectively.

(B-2) Correlation Value Calculation Operation Now, I1, I are input to the I component input terminal of the digital correlator 701.
, I3... Are sequentially given, and Q1, Q
2, Q3... Are sequentially given.

At this time, the contents of the first and second registers shown in FIG. 8 and the contents of the in-phase component and quadrature component correlation value storage registers are as shown in FIG. Here, the operation clocks applied to these registers are as shown in FIG.
As shown in the figure, the frequency has twice the change cycle of the input data (5 (B), (C)). The enable signals of the in-phase component correlation value storage register 20768 and the quadrature component correlation value storage register 20864 also change at the timing shown in FIG.

As shown in FIG. 9, each first register 20
701-20763 and second register 20801-2
9863 is the same as the digital correlation circuit according to the first embodiment.

However, the difference from the first embodiment is that the output of the adder 20664 at the last stage is input to the absolute value calculation circuit 809 and its absolute value is obtained, and that the absolute value Register 20774 for storing the correlation value of
This is a point stored in each of the registers 20864 for storing the correlation value of the orthogonal component.

The magnitude relation between the stored values is obtained in comparator 810. By using the comparison result,
The third selector 811 selects the larger absolute value. Thus, at the output end of the third selector 811, the first term on the right side in the above-mentioned equation (1) is obtained.

On the other hand, the fourth selector 812 selects the smaller absolute value, and supplies the selected absolute value to the 1-bit right shifter 813. Here, the input absolute value is 1
Shifting to the right by one bit reduces the input absolute value by 1 /
It is the same as doubling. Thus, at the output end of the 1-bit right shift 813, the second term on the right side in the above equation (1) is obtained.

Each output is input to the adder 305, and from its output terminal, a value determined by the equation (1) and a value corresponding to the square root of the sum of squares of the in-phase component and the quadrature component are output. By providing such a value to the cyclic integration circuit 306 and the matched pulse detection circuit 307, detection of a true matched pulse is realized.

(B-3) Effects of the Second Embodiment As described above, when the digital correlator according to the present embodiment is used, the same effects as those of the first embodiment can be obtained. Can be further obtained. That is,
In the conventional circuit, a square calculation circuit or an absolute value calculation circuit was required for each of the I component and the Q component of the correlator output. However, if the digital correlator according to the present embodiment is used, the case where the absolute value calculation circuit is used However, the circuit scale can be reduced by half. Thus, the number of gates can be reduced.

[0070]

As described above, according to the first aspect of the present invention, the correlation operation of each of the in-phase component and the quadrature component can be realized by a common multiplier and an adder. , The number of multipliers and the number of adders can be halved. Thus, the gate size can be reduced.

According to the second aspect, as described above,
An absolute value calculating means for calculating an absolute value, a register for an in-phase component and a register for a quadrature component for alternately storing outputs of the absolute value calculating means, and a register for an in-phase component A comparator for comparing the contents of the register for orthogonal components and the register for the orthogonal component, a third selector for selecting a value determined to be large by the comparator, and a third selector for selecting a value determined to be small by the comparator. By shifting the output of the fourth selector and the output of the fourth selector one bit to the right,
By providing a shift register for halving the output of the fourth selector, the circuit scale can be halved compared to the conventional device. Thus, the number of gates can be reduced.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a first embodiment of a receiving system portion of a wireless communication system using a CDMA system.

FIG. 2 is a functional block diagram showing a conventional configuration example of a receiving system portion of a wireless communication system using the CDMA system.

FIG. 3 is a block diagram showing a conventional example of a digital correlator.

FIG. 4 is a block diagram showing a digital correlator according to the first embodiment.

FIG. 5 is a timing chart showing a change of a control signal in the embodiment.

FIG. 6 is a table showing data in each register used for explaining the operation of the first embodiment.

FIG. 7 is a functional block diagram showing a second embodiment of a receiving system portion of a wireless communication system using the CDMA system.

FIG. 8 is a block diagram showing a digital correlator according to a second embodiment.

FIG. 9 is a table showing data in each register used for explaining the operation of the second embodiment.

[Explanation of symbols]

101, 301, 302, 701 ... Digital correlator,
303, 304: square calculation circuit, 305: adder, 30
6 cyclic integration circuit 307 matched pulse detection circuit
201, 202: PN code accumulator, 203: first selector, 20401 to 20464: second selector, 2050
1-20564 Multiplier, 20602-20664 Adder, 20701-20763 First register, 20
801 to 20863... Second register, 20664... In-phase component correlation value storage register, 20864... Quadrature component correlation value storage register, 809.
10 comparator, 811 third selector, 812 fourth selector, 813 1-bit right shifter.

Claims (2)

[Claims] 1. A first selecting means for selecting an in-phase component or a quadrature component of a received baseband signal, and a first spreader corresponding to an in-phase component of a received signal having a spreading code length L having a value of +1 or -1. First storage means for storing codes, second storage means for storing second spread codes corresponding to orthogonal components of a received signal having a spread code length L having a value of +1 or -1; And L second selecting means for selecting any one of the first and second spreading codes for each bit, and L second selecting means for multiplying the selection result of the first selector and the selection result of the second selector. A multiplier; (L-1) two-stage transfer type shift registers; and (L-2)
Have the same number of adders, and the shift register arranged at the top receives the output of the corresponding multiplier, and the shift registers arranged at the next and subsequent stages are arranged at the preceding stage with the output of the corresponding multiplier. Register means with an addition function for inputting the result of addition with the output of the shift register; an output adder for adding the output of the multiplier corresponding to the output of the last stage of the register means with the addition function; A digital correlation circuit comprising a register for an in-phase component and a register for a quadrature component for alternately accumulating the outputs of the adders. 2. A first selecting means for selecting an in-phase component or a quadrature component of a received baseband signal, and a first spreading unit corresponding to an in-phase component of a received signal having a spreading code length L having a value of +1 or -1. First storage means for storing codes, second storage means for storing second spread codes corresponding to orthogonal components of a received signal having a spread code length L having a value of +1 or -1; And L second selecting means for selecting any one of the first and second spreading codes for each bit, and L second selecting means for multiplying the selection result of the first selector and the selection result of the second selector. A multiplier; (L-1) two-stage transfer type shift registers; and (L-2)
Have the same number of adders, and the shift register arranged at the top receives the output of the corresponding multiplier, and the shift registers arranged at the next and subsequent stages are arranged at the preceding stage with the output of the corresponding multiplier. Register means with an addition function for inputting the result of addition with the output of the shift register; an output adder for adding the output of the multiplier corresponding to the output of the last stage of the register means with the addition function; An absolute value calculating means for calculating an absolute value of the adder, a register for an in-phase component and a register for a quadrature component for alternately storing the output of the absolute value calculating means, a register for the in-phase component and a register for the quadrature component. , A third selector for selecting a value determined to be large by the comparator, and a fourth selector for selecting a value determined to be small by the comparator. Vessels and, above by the fourth shift the output to 1 bit to the right of the selector, the digital correlation circuits; and a 1/2 multiplying the shift register the output of the fourth selector.