JP2002027282A - Sync separation circuit - Google Patents

Abstract

(57) Abstract: An object of the present invention is to realize a synchronization separation circuit that does not deteriorate jitter performance even when the shape of a signal waveform of a composite synchronization signal changes. A phase comparison circuit for outputting a phase comparison result from a composite synchronization signal in which a horizontal synchronization signal and a vertical synchronization signal are superimposed, a phase comparison reference signal, and a decimal point component of a frequency division ratio, and a phase comparison circuit based on an output of the phase comparison circuit A loop filter for calculating a frequency division ratio for generating a reference signal, and a frequency dividing circuit for inputting an integer component of the frequency division ratio output from the loop filter and generating a phase comparison reference signal are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal synchronization separation circuit in a color television receiver.

[0002]

2. Description of the Related Art In digital television signal processing, a sync separation circuit is used to reproduce a horizontal sync signal from CS sampled by a clock.
An example of a conventional sync separation circuit will be described.

[0003] The synchronization separation circuit includes a phase comparison circuit 10 that outputs a phase comparison result from CS and a phase comparison reference signal;
A loop filter 11 for calculating a frequency division ratio for generating a phase comparison reference signal from an output of the phase comparison circuit 10, and a frequency division for generating a phase comparison reference signal by inputting an integer component of the frequency division ratio output from the loop filter 11 It is composed of a circuit 12. Also, the decimal point component of the frequency division ratio is
Feedback to itself.

According to this method, the frequency dividing circuit 12 divides the clock according to the frequency division ratio indicated by the integer component of the frequency division ratio to generate a phase comparison reference signal. for that reason,
The phase comparison reference signal is shifted from the original phase by an amount corresponding to the decimal point component of the frequency division ratio. This shift appears as an error in phase detection from the phase comparison circuit 10 and is superimposed on the output of the phase comparison circuit 10 and appears. The loop filter 11 calculates the decimal point component of the frequency division ratio to cancel the phase detection error generated by the phase comparison circuit 10 at the input unit, and suppresses accumulation of the phase detection error in the loop filter 11.

However, the amount of this phase detection error due to the phase shift of the phase comparison reference signal generated by the phase comparison circuit 10 varies depending on the shape of the CS signal waveform, and sufficient error cancellation cannot be performed, resulting in jitter. There is a problem that performance is deteriorated. For example, when the signal amplitude of CS is large, the error of phase detection becomes large, and C
When the signal amplitude of S is small, the error of the phase detection becomes small.

[0006]

The object of the present invention is to provide a CS
Is realized, even if the shape of the signal waveform changes, the phase shift of the phase comparison reference signal can be canceled.

[0007]

In order to solve the above-mentioned problems, a synchronization separation circuit according to the present invention comprises a CS on which a horizontal synchronization signal and a vertical synchronization signal are superimposed, a phase comparison reference signal, and a decimal point component of a frequency division ratio. A phase comparison circuit that outputs a phase comparison result;
A loop filter for calculating a frequency division ratio for generating the phase comparison reference signal from the output of the phase comparison circuit, and a component for inputting an integer component of the frequency division ratio output from the loop filter to generate the phase comparison reference signal. Equipped with a circuit
In this method, the decimal point component of the frequency division ratio, which is the output of the loop filter, is returned to the phase comparison circuit, and the phase comparison circuit corrects the phase shift of the phase comparison reference signal.

According to the present invention, it is possible to provide a sync separation circuit capable of canceling the phase shift of the phase comparison reference signal even if the shape of the CS signal waveform changes.

[0009]

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The synchronization separation circuit according to the first embodiment of the present invention includes:
Phase comparison circuit 20, loop filter 21, frequency dividing circuit 22
It consists of.

In FIG. 2, the CS, the phase comparison reference signal, and the decimal point component of the frequency division ratio are input to a phase comparison circuit 20. The output of the phase comparison circuit 20 is input to the loop filter 21. The integer component of the frequency division ratio, which is the output of the loop filter 21, is input to the frequency dividing circuit 22.

The above-mentioned phase comparison reference signal is generated by dividing the clock in accordance with a frequency division ratio represented by an integer component of the frequency division ratio. Therefore, the phase comparison reference signal includes a deviation from the original phase by an amount corresponding to the decimal point component of the frequency division ratio.

FIG. 3 shows a circuit of the phase comparison circuit 20. In FIG. 3, the phase correction circuit 30 receives CS and the decimal point component of the frequency division ratio, and outputs 1 corresponding to the decimal point component of the frequency division ratio.
A phase shift within a clock is performed on CS. This correction has the effect of giving CS the same amount of phase shift as the phase shift of the phase comparison reference signal. The phase detector 31 receives the output of the phase correction circuit 30 and the phase comparison reference signal, and detects a phase error from the output of the phase correction circuit 30 and the phase comparison reference signal.

The phase detection by the phase detection circuit 31 is performed by the phase-corrected CS having no phase shift relative to the phase comparison reference signal, so that the phase shift between the two signals is canceled. Is not output.

According to the synchronization separation circuit of this embodiment, CS
, The phase shift of the phase comparison reference signal can be canceled.

(Embodiment 2) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The synchronization separation circuit according to the first embodiment of the present invention includes a phase comparison circuit 20, a loop filter 21, and a frequency division circuit 22.

In FIG. 2, CS, the phase comparison reference signal, and the decimal point component of the frequency division ratio are input to the phase comparison circuit 20. The output of the phase comparison circuit 20 is input to the loop filter 21. The integer component of the frequency division ratio, which is the output of the loop filter 21, is input to the frequency dividing circuit 22.

The above-mentioned phase comparison reference signal is generated by dividing the clock in accordance with the division ratio indicated by the integer component of the division ratio. Therefore, the phase comparison reference signal includes a deviation from the original phase by an amount corresponding to the decimal point component of the frequency division ratio.

FIG. 4 shows a circuit of the phase comparison circuit 20. 4, the phase correction circuit 40 receives the phase comparison reference signal and the decimal point component of the frequency division ratio, and performs a phase shift within one clock corresponding to the decimal point component of the frequency division ratio on the phase comparison reference signal. This correction has the effect of canceling out the phase shift of the phase comparison reference signal generated in the frequency dividing circuit 22. The phase detector 41 receives the output of the phase correction circuit 40 and the phase comparison reference signal, and detects a phase error from the output of the phase correction circuit 40 and the phase comparison reference signal.

The phase detection in the phase detection circuit 41 cancels the phase shift of the phase comparison reference signal immediately before the phase detection, and no error of the phase comparison is output to this output.

According to the synchronization separation circuit of this embodiment, CS
, The phase shift of the phase comparison reference signal can be canceled.

[0021]

As described above, according to the present invention, even if the shape of the CS signal waveform changes, the phase shift of the phase comparison reference signal can be canceled and the jitter performance can be prevented from deteriorating. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a synchronization separation circuit according to a conventional invention.

FIG. 2 is a block diagram illustrating a configuration of a synchronization separation circuit according to the first and second embodiments of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a phase comparison circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a phase comparison circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 10, 20 Phase comparison circuit 11, 21 Loop filter 12, 22 Divider circuit 30, 40 Phase correction circuit 31, 41 Phase detection circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Nobuo Takeya 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 72) Inventor Hitoshi Ando 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] A phase comparison circuit that outputs a phase comparison result from a composite synchronization signal (hereinafter referred to as CS) in which a horizontal synchronization signal and a vertical synchronization signal are superimposed, a phase comparison reference signal, and a decimal point component of a frequency division ratio; A loop filter for calculating a frequency division ratio for generating the phase comparison reference signal from an output of a phase comparison circuit; and a frequency division for generating an input of an integer component of the frequency division ratio output from the loop filter to generate the phase comparison reference signal. Synchronous separation circuit with circuit. 2. A phase correction circuit, wherein the phase comparison circuit corrects the CS based on a decimal component of a frequency division ratio;
2. A phase detection circuit for detecting a phase error from an output of the phase correction circuit and the phase comparison reference signal.
Synchronous separation circuit as described. 3. A phase correction circuit for correcting the phase correction reference signal based on a decimal component of a frequency division ratio, and detecting a phase error from an output of the phase correction circuit and the CS. 2. A phase detection circuit comprising:
Synchronous separation circuit as described.