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JP2002026714A - High withstand voltage level shift circuit for high withstand voltage IC - Google Patents

High withstand voltage level shift circuit for high withstand voltage IC

Info

Publication number
JP2002026714A
JP2002026714A JP2001123762A JP2001123762A JP2002026714A JP 2002026714 A JP2002026714 A JP 2002026714A JP 2001123762 A JP2001123762 A JP 2001123762A JP 2001123762 A JP2001123762 A JP 2001123762A JP 2002026714 A JP2002026714 A JP 2002026714A
Authority
JP
Japan
Prior art keywords
voltage
low
potential
withstand
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001123762A
Other languages
Japanese (ja)
Other versions
JP3384399B2 (en
Inventor
Tatsuhiko Fujihira
龍彦 藤平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2001123762A priority Critical patent/JP3384399B2/en
Publication of JP2002026714A publication Critical patent/JP2002026714A/en
Application granted granted Critical
Publication of JP3384399B2 publication Critical patent/JP3384399B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

(57)【要約】 【課題】第1もしくは第2の電圧発生手段に流れる電流
により発生する電圧が高耐圧nチャネルもしくはpチャ
ネルトランジスタのゲート・ソース間電圧を低下させ、
トランジスタの発熱を小さくする。 【解決手段】高耐圧レベルシフト回路図を示す。電圧発
生手段であるRN1、RP1、負荷手段であるRN2、RP2
は抵抗もしくはデプレツ ションモードのMOSFETな
どによる定電流源を用いるのがよい。電圧制限手段であ
るZN1、ZP1はツェナーダイオードを用いてもよいが、
MOSダイオード(MOSFETのソースとゲートを短
絡してダイオードとして用いたもの)を用いるほうがツ
ェナー電圧を低く抑えられるので優れている。電流制限
手段であるRN3、RP3は抵抗で、この場合、MOSダイ
オードであるZN1、ZP1に流れる電流を制限するために
付加してあるが、流れる電流を制限する必要が無い場合
は当然この抵抗は付加しなくても良い。
(57) Abstract: A voltage generated by a current flowing through first or second voltage generating means reduces a gate-source voltage of a high breakdown voltage n-channel or p-channel transistor,
Reduce the heat generated by the transistor. A high voltage level shift circuit diagram is shown. A constant current source such as a resistor or a depletion mode MOSFET is preferably used for R N1 and R P1 as voltage generating means and R N2 and R P2 as load means. Although the voltage limiting means Z N1 and Z P1 may use a Zener diode,
It is better to use a MOS diode (a diode in which the source and gate of the MOSFET are short-circuited and used as a diode) because the Zener voltage can be suppressed low. R N3 and R P3 as current limiting means are resistors. In this case, they are added to limit the current flowing through the MOS diodes Z N1 and Z P1 , but if there is no need to limit the flowing current, Of course, this resistor need not be added.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、パワーデバイスの制
御駆動用などに用いられる高耐圧ICで、パワーデバイ
スとは別の半導体基板または同一半導体基板上に形成さ
れる高耐圧ICに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage IC used for controlling and driving a power device and the like, and relates to a high withstand voltage IC formed on a semiconductor substrate different from the power device or on the same semiconductor substrate.

【0002】[0002]

【従来の技術】ここでは参考文献が多数あるため、文献
名はまとめて番号を付けて〔発明が解決しようとする課
題〕の項の最後に記載し、文章中では文献名の番号を[
]で示すことに留めた。また参考文献のUSP Noの後に
( )で示した内容は特許内容を簡単に説明したもので
ある。
2. Description of the Related Art Here, since there are many references, the names of the documents are numbered collectively and described at the end of the section [Problems to be Solved by the Invention].
]. The contents in parentheses after the USP No in the reference are brief descriptions of the patent contents.

【0003】パワーデバイス[1] 〜[4] は、モータ制御
用のインバータやコンバータ、照明用のインバータ、各
種電源およびソレノイドやリレーの駆動用スイッチ等の
多くの分野で広く利用されている。このパワーデバイス
の駆動や制御は、従来個別の半導体素子や電子部品を組
み合わせて構成した電子回路[5],[6] によっていたが、
近年LSI(高集積度IC、ICとは集積回路のこと)
技術を利用した数十V級の低耐圧IC[7],[8] や数百V
級の高耐圧IC[9],[10]が実用化されており、さらに駆
動・制御回路とパワーデバイスとを同一半導体基板に集
積化したパワーIC[11],[12] が用いられインバータや
コンバータなどの変換装置の小型化や高信頼性化が図ら
れている。
The power devices [1] to [4] are widely used in many fields such as inverters and converters for motor control, inverters for lighting, various power supplies, and switches for driving solenoids and relays. The drive and control of this power device has traditionally been performed by electronic circuits [5] and [6] that are configured by combining individual semiconductor elements and electronic components.
In recent years LSI (highly integrated IC, IC is an integrated circuit)
Tens of volt class low-voltage ICs using technology [7], [8] and hundreds of volts
Class high withstand voltage ICs [9] and [10] have been put to practical use, and power ICs [11] and [12] in which drive / control circuits and power devices are integrated on the same semiconductor substrate are used. 2. Description of the Related Art Converters such as converters have been reduced in size and higher in reliability.

【0004】図6はモータ制御用インバータのパワー部
分を中心に説明する回路構成図である。三相モータMo
を駆動するために用いるパワーデバイス(ここではIG
BTであるQ1〜Q6とダイオードであるD1〜D6を
示す)はブリッジ回路を構成し同一パッケージに収納さ
れたパワーモジュール[13]の構造をしている。ここでI
GBTとは絶縁ゲート型バイポーラトランジスタのこと
である。主電源VCCは通常直流100〜400Vと高電
圧である。主電源VCCの高電位側をVCCH 、低電位側を
CCL と表した場合、VCCH に接続されるIGBTQ1
〜Q3を駆動するためには、IGBTのゲート電極の電
位はこれよりさらに高電位となるため、駆動回路にはフ
ォトカプラー(PC:Photo Coupler)や
高耐圧IC(HVIC:High Voltage I
ntegrated Circuit)が用いられる。
駆動回路の入出力端子I/O(Input/Outpu
t)は通常マイクロコンピュータへ接続され、そのマイ
クロコンピュータによりインバータ全体の制御がなされ
る。
FIG. 6 is a circuit diagram mainly illustrating a power portion of a motor control inverter. Three-phase motor Mo
Power device (here, IG
BTs Q1 to Q6 and diodes D1 to D6) constitute a bridge circuit and have a structure of a power module [13] housed in the same package. Where I
GBT is an insulated gate bipolar transistor. The main power supply V CC is normally a high voltage of 100 to 400 VDC. When the high potential side of the main power supply V CC is represented by V CCH and the low potential side is represented by V CCL , the IGBT Q1 connected to V CCH
To drive Q3, the potential of the gate electrode of the IGBT becomes higher than this, so that the drive circuit includes a photocoupler (PC) or a high voltage IC (HVIC: High Voltage I).
integrated circuit) is used.
Input / output terminal I / O (Input / Output) of the drive circuit
t) is usually connected to a microcomputer, which controls the entire inverter.

【0005】図7は図6で用いられる高耐圧IC(HV
IC)の内部構成ユニットのブロック図を示す。その構
成をつぎに説明する。入出力端子I/Oを通してマイク
ロコンピュータと信号のやりとりを行い、どのIGBT
をオンさせ、どれをオフさせるかの制御信号を発生させ
る制御回路CU(Control Unit)と、この
制御回路CUからの信号を入力ラインSIN4〜6で受
けてIGBTのゲートドライブ用の出力ラインOUT4
〜6から信号を出力し、またIGBTの過電流を電流検
出端子[14]OC4〜6で、過熱を温度端子[15]OT4〜
6で検出し、異常信号を出力ラインSOUT4〜6で出
力し、図6の主電源VCCの低電位側VCC L に接続するI
GBTQ4〜Q6を駆動する、ゲート駆動回路GDU
(GateDrive Unit)4〜6と、GDU4
〜6と同じ機能で主電源VCCの高電位側VCCH に接続す
るQ1からQ3を駆動するゲート駆動回路GDU1〜3
と、VCCL レベルの制御回路CUの信号とVCCH レベル
とVCCL レベルの間を行き来するGDU1〜3の信号
(SIN1〜3、SOUT1〜3)との間を媒介する働
きをするレベルシフト回路LSU(Level Shi
ft Unit)とから構成されている。GDU1〜3
におけるドライブ電源VDD1 〜VDD3 (図8参照)から
の高電位側をVDDH1〜VDDH3、低電位側をVDDL1〜V
DDL3で示し、GDU4〜6におけるドライブ電源からの
共通電源がVDDC (図8でも省略されている)であり、
この共通電源VDDC の高電位側をVDDHC、低電位側をV
DDLCで示す。またGDU4〜6およびCUにおけるドラ
イブ共通電源VDDC は10〜20V程度であり、この共
通電源VDDC の低電位側VDDLCは図6の主電源VCCの低
電位側VCCL に接続する。
FIG. 7 shows a high breakdown voltage IC (HV) used in FIG.
2 shows a block diagram of an internal configuration unit of IC). Its structure
The operation will be described below. Microphone through input / output terminal I / O
Exchanges signals with the computer, which IGBT
To generate a control signal to turn on and turn off
Control circuit CU (Control Unit)
Signals from control circuit CU are received on input lines SIN4 to SIN6.
IGBT gate drive output line OUT4
6 to IGBT, and the overcurrent of IGBT
Output terminal [14] OC4 ~ 6, overheat the temperature terminal [15] OT4 ~
6 and an abnormal signal is output on output lines SOUT4-6.
And the main power supply V of FIG.CCLow potential side V ofCC L I connect to
Gate drive circuit GDU for driving GBTs Q4 to Q6
(GateDrive Unit) 4-6 and GDU4
Main power supply V with the same function asCCHigh potential side V ofCCH Connect to
Gate driving circuits GDU1 to GDU3 for driving Q1 to Q3
And VCCL Level control circuit CU signal and VCCH level
And VCCLGDU1-3 signals that go back and forth between levels
(SIN1-3, SOUT1-3)
Level shift circuit LSU (Level Shi
ft Unit). GDU1-3
Drive power supply VDD1 ~ VDD3 (See Fig. 8)
V on the high potential side ofDDH1~ VDDH3, Low potential side VDDL1~ V
DDL3From the drive power supply in GDUs 4-6.
Common power supply is VDDC (Also omitted in FIG. 8),
This common power supply VDDC V on the high potential side ofDDHC, Low potential side V
DDLCIndicated by GDU 4-6 and CU
Eve common power supply VDDC Is about 10 to 20 V.
Power supply VDDC Low potential side V ofDDLCIs the main power supply V in FIG.CCLow
Potential side VCCL Connect to

【0006】図8は図7のGDU1とIGBTQ1のさ
らに詳細な接続図を示す。ここではその他のGDUとI
GBTは省略している。GDU1のドライブ電源VDD1
は10〜20V程度であり、その低電位側VDDL1はIG
BTQ1 のエミッタ端子Eに即ちインバータ出力のU相
に接続され、IGBTQ1のコレクタ端子Cが主電源V
CCの高電位側VCCH に接続されている。このため、IG
BTQ1がオンした時はVDDL1の電位はVCCH の電位と
ほぼ等しくなり、またIGBTQ1がオフした時はV
DDL1の電位はVCCL の電位とほぼ等しくなる。従って、
GDU1と他の回路ユニットとの間には主電源VCCの電
圧より、さらに高い絶縁耐圧が必要であり、このことは
GDU2、3についても同様である。そしてレベルシフ
ト回路LSUはそれ自体が高耐圧でなければならない。
同図においてIGBTQ1は電流検出端子[16]Mと温度
検出素子θおよび温度検出端子[17]Tempを備え、ゲ
ート駆動回路GDU1は電流検出端子OC1や温度検出
端子OT1によりIGBTQ1の異常を検出し、異常信
号を出力ラインSOUT1から出力する。OUT1はゲ
ート駆動端子である。
FIG. 8 shows a more detailed connection diagram between GDU1 and IGBTQ1 in FIG. Here are the other GDUs and I
GBT is omitted. Drive power supply V DD1 for GDU1
Is about 10 to 20 V, and the lower potential side V DDL1 is IG.
The collector terminal C of the IGBT Q1 is connected to the emitter terminal E of the BTQ1, that is, to the U phase of the inverter output.
Connected to the high potential side V CCH of CC . For this reason, IG
When BTQ1 is turned on, the potential of V DDL1 becomes substantially equal to the potential of V CCH , and when IGBTQ1 is turned off, V DDL1 becomes V
The potential of DDL1 becomes substantially equal to the potential of V CCL . Therefore,
A higher withstand voltage than the voltage of the main power supply V CC is required between the GDU 1 and the other circuit units, and the same is true for the GDUs 2 and 3. The level shift circuit LSU itself must have a high breakdown voltage.
In the figure, the IGBT Q1 includes a current detection terminal [16] M, a temperature detection element θ and a temperature detection terminal [17] Temp, and the gate drive circuit GDU1 detects an abnormality of the IGBT Q1 by the current detection terminal OC1 and the temperature detection terminal OT1, An abnormal signal is output from the output line SOUT1. OUT1 is a gate drive terminal.

【0007】図9は図6と同一回路をインテリジェント
パワーモジュール[18]と呼ばれる製品を用いて構成した
構成図である。この場合ゲート駆動回路GDU1〜GD
U6は、低耐圧ICや個別電子部品および半導体素子か
らなり、パワーデバイス(Q1〜Q6、D1〜D6)と
ともにパワーデバイス側のパッケージに備えられてい
る。この場合でも、外付けの駆動回路としてはフォトカ
プラー(PC)や高耐圧IC(HVIC)が用いられ
る。
FIG. 9 is a block diagram of the same circuit as that of FIG. 6 using a product called an intelligent power module [18]. In this case, the gate drive circuits GDU1 to GD
U6 is composed of a low-voltage IC, an individual electronic component, and a semiconductor element, and is provided in a package on the power device side together with the power devices (Q1 to Q6, D1 to D6). Even in this case, a photocoupler (PC) or a high withstand voltage IC (HVIC) is used as an external drive circuit.

【0008】図10は図9のIGBTQ1およびGDU
1のまわりの回路を詳細に示したものである。SIN1
およびSOUT1は外部の構成となるPCやHVICに
接続される。またその他の構成例として、GDU1とQ
1を1チップ(同一の半導体基板)に集積化するパワー
IC技術[19],[20] や図9の全ての回路を1チップに集
積化するパワーIC技術[11],[12] も開示されている。
FIG. 10 shows IGBT Q1 and GDU of FIG.
1 shows the circuit around 1 in detail. SIN1
And SOUT1 are connected to an externally configured PC or HVIC. As another configuration example, GDU1 and Q
Also disclosed are power IC technologies [19] and [20] that integrate 1 on one chip (same semiconductor substrate) and power IC technologies [11] and [12] that integrate all circuits in FIG. 9 on one chip. Have been.

【0009】図11は図7に示した高耐圧IC(HVI
C)のチップの平面図を示し、各回路ユニットの配置が
分かるように描いている。他の回路ユニットから高耐圧
で分離される必要のあるGDU1は接合分離[21],[22],
[10]や誘電体分離[23],[11],[12]により電気的に分離さ
れた島の中に形成されており、その周縁部を高耐圧接合
終端構造[11],[21] HVJT(絶縁するために高電圧が
印加される接合の終端部の構造をいう)により囲まれて
いる。レベルシフト回路LSUの中には主電源VCCの低
電位側の電位VCCL レベルの信号をドライブ電源VDD1
の低電位側の電位VDDL1レベルの信号(入力ラインSI
N1の信号)にレベルシフトするための高耐圧nチャネ
ルMOSFET(HVN)が設けられている。この高耐
圧nチャネルMOSFETには、中心のドレイン電極D
N を囲んで高耐圧接合終端構造[10],[11] HVJTが設
けられている。またGDU1の分離された島の中にはV
DD L1レベルの信号(出力ラインSOUT1の信号)をV
CCL レベルの信号にレベルシフトするための高耐圧pチ
ャネルMOSFET(HVP)が設けられており、この
場合もドレイン電極DP を囲んで高耐圧接合終端構造H
VJTが設けられている。そして、GDU1の入力ライ
ンSIN1と出力ラインSOUT1が、高耐圧接合終端
構造HVJTの上を通ってGDU1とLSUの間にそれ
ぞれ跨がって配線されている。また各GDUには図8で
示したOUT端子、OC端子、OT端子が配置され、G
DU1〜GDU3にはVDDH1〜VDDH3の端子、VDDL1
DDL3の端子が配置され、またGDU4〜GDU6には
DDHCの端子とVDDLCの端子が配置されている。同図で
はGDU1とGDU4の詳細な説明をし、他のGDUは
詳細な配置説明は省略した。
FIG. 11 shows a high voltage IC (HVI) shown in FIG.
C) shows a plan view of the chip, and shows the arrangement of each circuit unit.
It is drawn so that it can be understood. High withstand voltage from other circuit units
GDU1 that needs to be separated by the splicing separation [21], [22],
[10] and dielectric isolation [23], [11], [12]
Is formed in a closed island, and its periphery is
Termination structure [11], [21] HVJT (High voltage to insulate
The structure of the end of the applied junction)
I have. The main power supply V is included in the level shift circuit LSU.CCLow
The potential V on the potential sideCCL Drive signal V level signalDD1
Potential V on the lower potential side ofDDL1Level signal (input line SI
N1 channel)
A MOSFET (HVN) is provided. This high endurance
A central drain electrode D
N HVJT is set around the high voltage junction termination structure [10], [11].
Have been killed. Also, VDU is in the isolated island of GDU1.
DD L1The level signal (the signal of the output line SOUT1) is
CCLHigh voltage p-ch for level shift to level signal
A channel MOSFET (HVP) is provided.
Drain electrode DP High-voltage junction termination structure H
VJT is provided. Then, the input line of GDU1 is
SIN1 and the output line SOUT1 are connected to a high-voltage junction termination.
Pass it over the structure HVJT and between GDU1 and LSU
They are wired over each other. Each GDU is shown in FIG.
OUT terminal, OC terminal, and OT terminal shown in FIG.
V for DU1 to GDU3DDH1~ VDDH3Terminal, VDDL1~
VDDL3Are arranged, and GDU4 to GDU6 are
VDDHCTerminal and VDDLCTerminals are arranged. In the figure
Gives a detailed description of GDU1 and GDU4, and other GDUs
Detailed description of the arrangement is omitted.

【0010】前記した従来の高耐圧ICやパワーICの
課題は600Vを越える高耐圧化が困難なこと、製造コ
ストが高いことなどであるが、さらに詳細に説明すると
次のようになる。 (1)分離技術に関する課題 先に述べたように、他の部分と電位の大きく異なる回路
ユニット(例えば図11のGDU1、2、3)を他の部
分から電気的に高耐圧で分離する分離技術には誘電体分
離[11],[12],[23]、接合分離[10],[21],[22]、自己分離
[20],[24] などの技術がある。しかし誘電体分離や接合
分離は分離構造が複雑で製造コストが高く、耐圧が高く
なるほど、この製造コストがさらに高くなる。また自己
分離は製造コストは低く抑えられるが、CMOS(相補
形MOSFET)構成では高耐圧化技術が未だ開発され
ておらず、一方、高耐圧化が可能なNMOS(nチャネ
ルMOSFET)構成ではアナログ回路(先で述べた電
流検出回路や温度検出回路を指す)の高精度化が極めて
困難である。 (2)高耐圧接合終端構造HVJTに関する課題 高耐圧接合終端構造は、縦型パワーデバイス用のもの[2
5],[26] 、横型高耐圧デバイス用のもの[27],[28],[29]
など個々の用途別に各種構造が開示されている。しかし
ながら、高耐圧化したICであるHVICやパワーデバ
イスを集積した高耐圧パワーICにおいては、集積回路
ユニット間の高耐圧接合終端構造(図11のGDU1〜
3の回り)、高耐圧横型nチャネルMOSFET用の高
耐圧接合終端構造(図11のHVNのDN の回り)、高
耐圧横型pチャネルMOSFET用の高耐圧接合終端構
造(図11のHVPのDP の回り)、さらには縦型パワ
ーデバイス用の高耐圧接合終端構造など多くの用途の高
耐圧接合終端構造を同一チップ上に形成する必要があ
る。従来のような汎用性の少ない構造で高耐圧ICやパ
ワーICを実現しようとすると、多くの異なる高耐圧接
合終端構造HVJTを同一チップ上に形成しなければな
らず、製造コストが高くなる。
The problems of the above-mentioned conventional high-voltage IC and power IC are that it is difficult to increase the withstand voltage exceeding 600 V, and the manufacturing cost is high. The more detailed description is as follows. (1) Problems Regarding Separation Technology As described above, a separation technology for electrically separating a circuit unit (for example, GDU1, 2, 3 in FIG. 11) having a significantly different potential from other portions with high withstand voltage electrically from other portions. Has dielectric isolation [11], [12], [23], junction isolation [10], [21], [22], self isolation
There are technologies such as [20] and [24]. However, dielectric isolation and junction isolation have a complicated isolation structure and a high manufacturing cost, and the higher the breakdown voltage, the higher the manufacturing cost. Although self-isolation can keep the manufacturing cost low, a technology for increasing the withstand voltage has not yet been developed in the CMOS (complementary MOSFET) configuration, while an analog circuit has been developed in the NMOS (n-channel MOSFET) configuration capable of increasing the breakdown voltage. It is extremely difficult to improve the accuracy of the current detection circuit and the temperature detection circuit described above. (2) Issues related to high-breakdown-voltage junction termination structure HVJT The high-breakdown-voltage junction termination structure is for vertical power devices [2
5], [26] for horizontal high voltage devices [27], [28], [29]
For example, various structures are disclosed for individual uses. However, in the HVIC which is a high breakdown voltage IC or a high breakdown voltage power IC in which a power device is integrated, a high breakdown junction termination structure between the integrated circuit units (GDU1 to GDU1 in FIG. 11).
3), a high-breakdown-voltage junction termination structure for a high-breakdown-voltage lateral n-channel MOSFET (around DN of HVN in FIG. 11), and a high-breakdown-voltage junction termination structure for a high-breakdown-voltage lateral p-channel MOSFET (D of HVP in FIG. 11). It is necessary to form a high-breakdown-voltage junction termination structure for many applications such as a high-breakdown-voltage junction termination structure for a vertical power device on the same chip. In order to realize a high breakdown voltage IC or a power IC with a structure having less versatility as in the related art, many different high breakdown voltage junction termination structures HVJT must be formed on the same chip, and the manufacturing cost increases.

【0011】[0011]

【発明が解決しようとする課題】信号配線下の高耐圧接
合終端構造に関する課題として次のものがある。高耐圧
ICでは、電位の大きく異なる集積回路ユニット(例え
ば図11のGDU1とLSU)間での信号のやり取りを
行うため、高耐圧接合終端構造HVJT上に信号配線を
通すことが必要とされる。ところが、高耐圧接合終端構
造HVJT上を信号配線を通すとこの信号配線の電位の
影響を受けて、高耐圧接合終端構造HVJTの耐圧が低
下する問題がある[30]。この問題を解決するために、い
くつかの構造[10],[11],[12],[31] が提案されている
が、構造が複雑なため製造コストが高くなる。またこれ
らの提案されている構造では信号配線の影響を皆無にで
きなく、耐圧低下の程度を少なくしている丈であり、6
00V程度の耐圧までは実用化できても、それ以上の耐
圧のものはまだ実現していない。
Problems relating to the high-breakdown-voltage junction termination structure under the signal wiring include the following. In the high-withstand voltage IC, signals are exchanged between integrated circuit units (for example, GDU1 and LSU in FIG. 11) having greatly different potentials, and therefore, it is necessary to pass signal wiring over the high-breakdown-voltage junction termination structure HVJT. However, when a signal wiring is passed over the high-breakdown-voltage junction termination structure HVJT, there is a problem that the withstand voltage of the high-breakdown-voltage junction termination structure HVJT decreases due to the influence of the potential of the signal wiring [30]. In order to solve this problem, several structures [10], [11], [12], [31] have been proposed, but the cost is high due to the complicated structure. Further, these proposed structures cannot eliminate the influence of the signal wiring at all, and have a length that reduces the degree of reduction in withstand voltage.
Although a voltage withstand voltage of about 00 V can be put to practical use, a voltage withstand voltage higher than that has not yet been realized.

【0012】この発明は、高耐圧接合終端構造HVJT
上を信号配線を通すとこの信号配線の電位の影響を受け
て、高耐圧接合終端構造HVJTの耐圧が低下するとい
う前記課題を解決し、低コストな高耐圧ICおよびそれ
に用いる高耐圧レベルシフト回路を提供することを目的
とする。 参考文献 〔1〕USP 4,364,073(IGBT関連) 〔2〕USP 4,893,165(ノンパンチスルー形IGBT関連) 〔3〕USP 5,008,725(パワーMOSFET関連) 〔4〕EP 0,071,916、特開昭58-39065に対応( 高速ダイ
オード内蔵パワーMOSFET関連) 〔5〕USP 5,091,664(駆動回路関連) 〔6〕USP 5,287,023(駆動回路関連) 〔7〕USP 4,947,234(低耐圧ICとパワーデバイス関連) 〔8〕USP 4,937,646(低耐圧ICとパワーデバイス関連)
The present invention provides a high-breakdown-voltage junction termination structure HVJT.
To solve the above-mentioned problem that the withstand voltage of the high-breakdown-voltage junction termination structure HVJT is reduced due to the influence of the potential of the signal line when the signal wire passes therethrough, a low-cost high-breakdown-voltage IC and a high-breakdown-voltage level shift circuit used therefor The purpose is to provide. References [1] USP 4,364,073 (related to IGBTs) [2] USP 4,893,165 (related to non-punch-through IGBTs) [3] USP 5,008,725 (related to power MOSFETs) [4] Compliant with EP 0,071,916 and JP-A-58-39065 (high speed) [5] USP 5,091,664 (drive circuit related) [6] USP 5,287,023 (drive circuit related) [7] USP 4,947,234 (low voltage IC and power device related) [8] USP 4,937,646 (low voltage IC and (Power device related)

〔9〕A.Wegener and M.Amato "A HIGH VOLTAGE INTERF
ACE IC FOR HALF-BRIDGECIRCUITS" Electrochemical So
ciety Extended Abstracts,vol.89-1,pp.476-478(1989) 〔10〕T.Terashima et al "Structure of 600V IC an
d A New Voltage Sensing Device" IEEE Proceeding of
the 5th International Symposium on Power Semicond
uctor Devices and ICs,pp.224-229(1993) 〔11〕K.Endo et al "A 500V 1A 1-chip Inverter IC
with a New Electric Field Reduction Structure" IE
EE Proceeding of the 6th International Symposium o
n Power Semiconductor Devices and ICs,pp.379-383(1
994) 〔12〕N.Sakurai et al "A three-phase inverter IC
for AC220V with a drasticall small chip size and
highly intelligent functions" IEEE Proceeding of T
he 5th International Symposium on Power Semiconduc
tor Devices andICs,pp.310-315(1993) 〔13〕M.Mori et al "A HIGH POWER IGBT MODULE FOR
TRACTION MOTOR DRIVE"IEEE Proceeding of the 5th I
nternational Symposium on Power Semiconductor Devi
ces and ICs,pp.287-289(1993) 〔14〕USP 5,159,516 (電流検出方法関連) 〔15〕USP 5,070,322 (温度検出方法関連) 〔16〕USP 5,097,302 (電流検出用素子関連) 〔17〕USP 5,304,837 (温度検出用素子関連) 〔18〕K.Reinmuth et al "Intelligent Power Module
s for Driving Systems"IEEE Proceeding of the 6th I
nternational Symposium on Power Semiconductor Devi
ces and ICs,pp.93-97(1994) 〔19〕USP 4,677,325 (IPS関連) 〔20〕USP 5,053,838 (IPS関連) 〔21〕R.Zambrano et al "A New Edge Structure for
2kVolt Power IC Operation" IEEE Proceeding of the
6th International Symposium on Power Semiconducto
r Devices and ICs,pp.373-378(1994) 〔22〕M.F.Chang et al "Lateral HVIC with 1200-V
Bipolar and Field-Effect Devices"IEEE Transactions
on Electron devices,vol.ED-33,No.12,pp.1992-2001
(1986) 〔23〕T.Ohoka et al "A WAFER BONDED SOI STRUCTUR
E FOR INTELLIGENT POWER ICs" IEEE Proceeding of th
e 5th International Symposium on Power Semiconduct
or Devices and ICs,pp.119-123(1993) 〔24〕J.P.MILLER "A VERY HIGH VOLTAGE TECHNOLOGY
(up to 1200V) FOR VERTICAL SMART POEWR ICs" Electr
ochemical Society Extended Abstracts,vol.89-1,pp.4
03-404(1989) 〔25〕USP 4,399,449 (パワーデバイスのHVJT関連) 〔26〕USP 4,633,292 (パワーデバイスのHVJT関連) 〔27〕USP 4,811,075 (横型MOSFETのHVJT関連) 〔28〕USP 5,258,636 (横型MOSFETのHVJT関連) 〔29〕USP 5,089,871 (横型MOSFETのHVJT関連) 〔30〕P.K.T.MOK and C.A.T.SALAMA "Interconnect I
nduced Breakdown in HVIC's" Electrochemical Societ
y Extended Abstracts,vol.89-1,pp.437-438(1989) 〔31〕USP 5,043,781 ( パワーIC関連)
[9] A. Wegener and M. Amato "A HIGH VOLTAGE INTERF
ACE IC FOR HALF-BRIDGECIRCUITS "Electrochemical So
ciety Extended Abstracts, vol. 89-1, pp. 476-478 (1989) [10] T. Terashima et al "Structure of 600V IC an
d A New Voltage Sensing Device "IEEE Proceeding of
the 5th International Symposium on Power Semicond
uctor Devices and ICs, pp.224-229 (1993) [11] K. Endo et al "A 500V 1A 1-chip Inverter IC
with a New Electric Field Reduction Structure "IE
EE Proceeding of the 6th International Symposium o
n Power Semiconductor Devices and ICs, pp.379-383 (1
994) [12] N. Sakurai et al "A three-phase inverter IC
for AC220V with a drasticall small chip size and
highly intelligent functions "IEEE Proceeding of T
he 5th International Symposium on Power Semiconduc
tor Devices and ICs, pp. 310-315 (1993) [13] M. Mori et al "A HIGH POWER IGBT MODULE FOR
TRACTION MOTOR DRIVE "IEEE Proceeding of the 5th I
nternational Symposium on Power Semiconductor Devi
ces and ICs, pp.287-289 (1993) [14] USP 5,159,516 (related to current detection method) [15] USP 5,070,322 (related to temperature detection method) [16] USP 5,097,302 (related to current detection element) [17] USP 5,304,837 (related to temperature detection element) [18] K. Reinmuth et al "Intelligent Power Module
s for Driving Systems "IEEE Proceeding of the 6th I
nternational Symposium on Power Semiconductor Devi
ces and ICs, pp. 93-97 (1994) [19] USP 4,677,325 (IPS related) [20] USP 5,053,838 (IPS related) [21] R. Zambrano et al "A New Edge Structure for
2kVolt Power IC Operation "IEEE Proceeding of the
6th International Symposium on Power Semiconducto
r Devices and ICs, pp. 373-378 (1994) [22] MFChang et al "Lateral HVIC with 1200-V
Bipolar and Field-Effect Devices "IEEE Transactions
on Electron devices, vol.ED-33, No.12, pp.1992-2001
(1986) [23] T. Ohoka et al "A WAFER BONDED SOI STRUCTUR
E FOR INTELLIGENT POWER ICs "IEEE Proceeding of th
e 5th International Symposium on Power Semiconduct
or Devices and ICs, pp.119-123 (1993) [24] JPMILLER "A VERY HIGH VOLTAGE TECHNOLOGY
(up to 1200V) FOR VERTICAL SMART POEWR ICs "Electr
ochemical Society Extended Abstracts, vol.89-1, pp.4
03-404 (1989) [25] USP 4,399,449 (HVJT related to power devices) [26] USP 4,633,292 (HVJT related to power devices) [27] USP 4,811,075 (HVJT related to horizontal MOSFETs) [28] USP 5,258,636 (Horizontal MOSFETs) [29] USP 5,089,871 (Horizontal MOSFET HVJT related) [30] PKTMOK and CATSALAMA "Interconnect I
nduced Breakdown in HVIC's "Electrochemical Societ
y Extended Abstracts, vol.89-1, pp.437-438 (1989) [31] USP 5,043,781 (Power IC related)

【0013】[0013]

【課題を解決するための手段】前記の目的を達成するた
めに、解決手段として、高電圧電源の高電位側に主端子
の一方が接続され、負荷に主端子の他方が接続された1
個以上のパワーデバイスのゲートを駆動するための高耐
圧ICの高耐圧レベルシフト回路であって、高電圧電源
の低電位側を基準とした低電圧電源により電流を供給さ
れる低電位側低耐圧回路部分の信号を前記パワーデバイ
スの主端子のうちどちらか一方を基準とした低電圧電源
により電流が供給される高電位側低耐圧回路部分への信
号に変換するレベルシフト回路であって、高耐圧nチャ
ネルトランジスタのドレイン(コレクタ)電極に第1の
負荷手段と第1の電圧制限手段の一方の端子が接続さ
れ、第1の負荷手段と第1の電圧制限手段の他方の端子
が高電位側低耐圧回路部分の低電圧電源の高電位側に接
続され、第1の電圧発生手段が高耐圧nチャネルトラン
ジスタのソース(エミッタ)電極と低電位側低耐圧回路
部分の低電圧電源の低電位側との間に接続され、第2の
電圧制限手段が高耐圧nチャネルトランジスタのゲート
(ベース)電極と低電位側低耐圧回路部分の低電圧電源
の低電位側との間に接続され、高耐圧nチャネルトラン
ジスタのゲート(ベース)電極へ低電位側低耐圧回路部
分からの信号が入力され、高耐圧nチャネルトランジス
タのドレイン(コレクタ)電極から高電位側低耐圧回路
部分への信号が出力されることとする。そして、第2の
電圧制限手段がゲート(ベース)とドレイン(コレク
タ)とを接続したnチャネルMOSダイオードで構成さ
れることとするとよい。あるいは、高電圧電源の高電位
側に主端子の一方が接続され、負荷に主端子の他方が接
続された1個以上のパワーデバイスのゲートを駆動する
ための高耐圧ICの高耐圧レベルシフト回路であって、
前記パワーデバイスの主端子のうちどちらか一方を基準
とした低電圧電源により電流が供給される高電位側低耐
圧回路部分の信号を、前記高電圧電源の低電位側を基準
とした低電圧電源により電流を供給される低電位側低耐
圧回路部分への信号に変換するレベルシフト回路であっ
て、高耐圧pチャネルトランジスタのドレイン(コレク
タ)電極に第2の負荷手段と第3の電圧制限手段の一方
の端子が接続され、第2の負荷手段と第3の電圧制限手
段の他方の端子が低電位側低耐圧回路部分の低電圧電源
の低電位側に接続され、第2の電圧発生手段が高耐圧p
チャネルトランジスタのソース(エミッタ)電極と高電
位側低耐圧回路部分の低電圧電源の高電位側との間に接
続され、第4の電圧制限手段が高耐圧pチャネルトラン
ジスタのゲート(ベース)電極と高電位側低耐圧回路部
分の低電圧電源の高電位側との間に接続され、高耐圧p
チャネルトランジスタのゲート(ベース)電極へ高電位
側低耐圧回路部分からの信号が入力され、高耐圧pチャ
ネルトランジスタのドレイン(コレクタ)電極から高電
位側低耐圧回路部分への信号が出力されることとする。
更に、第4の電圧制限手段がゲート(ベース)とドレイ
ン(コレクタ)とを接続したpチャネルMOSダイオー
ドで構成されることとするとよい。
In order to achieve the above object, as a solution, one of the main terminals is connected to the high potential side of the high voltage power supply, and the other of the main terminals is connected to the load.
A high-voltage level shift circuit of a high-voltage IC for driving gates of at least two power devices, wherein a low-voltage side low-voltage voltage is supplied by a low-voltage power supply based on a low-potential side of a high-voltage power supply. A level shift circuit for converting a signal of a circuit portion into a signal to a high-potential-side low-withstand-voltage circuit portion to which a current is supplied from a low-voltage power supply with reference to one of the main terminals of the power device; One terminal of the first load means and one terminal of the first voltage limit means are connected to the drain (collector) electrode of the withstand voltage n-channel transistor, and the other terminals of the first load means and the first voltage limit means are connected to a high potential. The first voltage generating means is connected to the high-potential side of the low-voltage power supply of the low-voltage circuit portion of the low-voltage circuit portion and the source (emitter) electrode of the high-voltage n-channel transistor. A second voltage limiting means connected between the gate (base) electrode of the high-breakdown-voltage n-channel transistor and the low-potential side of the low-voltage power supply in the low-potential-side low-breakdown-voltage circuit portion; A signal from the low-potential-side low-withstand-voltage circuit portion is input to the gate (base) electrode of the high-withstand-voltage n-channel transistor, and a signal is output from the drain (collector) electrode of the high-withstand-voltage n-channel transistor to the high-potential-side low-withstand voltage circuit portion. Shall be done. Preferably, the second voltage limiting means comprises an n-channel MOS diode having a gate (base) and a drain (collector) connected to each other. Alternatively, a high withstand voltage level shift circuit of a high withstand voltage IC for driving the gate of one or more power devices in which one of the main terminals is connected to the high potential side of the high voltage power supply and the other of the main terminals is connected to the load And
A signal of a high-potential-side low-withstand-voltage circuit portion to which a current is supplied by a low-voltage power supply with reference to one of the main terminals of the power device is connected to a low-voltage power supply with reference to the low-potential side of the high-voltage power supply. A level shift circuit for converting a signal to a low-potential-side low-withstand-voltage circuit portion to which a current is supplied, wherein a second load means and a third voltage-limiting means are provided at a drain (collector) electrode of a high-withstand-voltage p-channel transistor. And the other terminals of the second load means and the third voltage limiting means are connected to the low potential side of the low voltage power supply of the low potential side low withstand voltage circuit portion, and the second voltage generating means Is high withstand voltage p
The fourth voltage limiting means is connected between the source (emitter) electrode of the channel transistor and the high-potential side of the low-voltage power supply in the high-potential-side low-withstand-voltage circuit portion, and the fourth voltage limiting means is connected to the gate (base) electrode of the high-withstand-voltage p-channel transistor. It is connected between the high-potential side of the low-voltage power supply and the high-voltage
A signal from the high-potential-side low-withstand-voltage circuit portion is input to the gate (base) electrode of the channel transistor, and a signal from the drain (collector) electrode of the high-withstand-voltage p-channel transistor is output to the high-potential-side low-withstand voltage circuit portion. And
Further, it is preferable that the fourth voltage limiting means is constituted by a p-channel MOS diode in which a gate (base) and a drain (collector) are connected.

【0014】また文章中で、「パワーデバイスの主端子
のうちどちらか一方を基準とした低電圧電源により電流
を供給される高電位側低耐圧回路部分」の文章中で、ど
ちらか一方とは、高電位側のパワーデバイスがnチャネ
ル素子の場合は負荷側が基準となり、pチャネル素子の
場合には電源側が基準となることを意味している。ここ
で基準となるとは、パワーデバイスのソース(エミッ
タ)電極が基準電位点(通称アース点)となることを意
味する。請求項1〜4によれば、第1もしくは第2の電
圧発生手段に流れる電流により発生する電圧が高耐圧n
チャネルもしくはpチャネルトランジスタのゲート(ベ
ース)・ソース(エミッタ)間電圧を低下させるので、
高耐圧nチャネルもしくはpチャネルランジスタに流れ
る電流が低く抑えられ、トランジスタの発熱が小さくな
るので信頼性が向上する。
[0014] In the text, "high-potential-side low-withstand-voltage circuit portion to which current is supplied by a low-voltage power supply with reference to one of the main terminals of the power device" If the power device on the high potential side is an n-channel device, the load side is the reference, and if the power device is a p-channel device, the power supply side is the reference. Here, "becoming a reference" means that the source (emitter) electrode of the power device becomes a reference potential point (commonly called a ground point). According to the first to fourth aspects, the voltage generated by the current flowing through the first or second voltage generating means has a high withstand voltage n.
Since the voltage between the gate (base) and source (emitter) of the channel or p-channel transistor is reduced,
The current flowing through the high-breakdown-voltage n-channel or p-channel transistor is suppressed low, and the heat generation of the transistor is reduced, so that the reliability is improved.

【0015】請求項2、4によれば、MOSダイオード
の電圧は通常用いられるツェナーダイオードの電圧より
さらに低いので、前記電流をさらに低く抑えることがで
き、トランジスタの発熱がさらに小さくなり、信頼性が
さらに向上する。
According to the second and fourth aspects, the voltage of the MOS diode is lower than the voltage of the normally used zener diode. Therefore, the current can be further reduced, the heat generation of the transistor is further reduced, and the reliability is reduced. Further improve.

【0016】[0016]

【発明の実施の形態】以下の図中の各符号は前記と同様
であり、説明は省略する。図1は第一参考例で、同図
(a)は平面図、同図(b)は側面図を示す。高耐圧接
合終端構造HVJTが高電位側低耐圧回路であるGDU
1〜GDU3と、高耐圧nチャネルMOSFET(HV
N)および高耐圧pチャネルMOSFET(HVP)に
それぞれ設けられている。高耐圧nチャネルMOSFE
T(HVN)および高耐圧pチャネルMOSFET(H
VP)は、ドレイン電極が高耐圧接合終端構造HVJT
のループの内側に、ソース電極とゲート電極とが高耐圧
接合終端構造HVJTのループの外側に配置されてい
る。そして、高耐圧nチャネルMOSFET(HVN)
のドレイン電極DN とGDU1、高耐圧pチャネルMO
SFET(HVP)のドレイン電極DP とLSUとがS
IN1およびSOUT1でそれぞれ接続される。このS
IN1、SOUT1は金線などのボンディングワイヤで
形成される。またGDU1〜GDU3の各高耐圧接合終
端構造HVJTの外側の端、およびHVN、HVPの各
高耐圧接合終端構造HVJTの外側の端とボンディング
ワイヤとの間隔を100μm以上離すことによって、空
間容量(浮遊容量)を従来より1桁小さくできる。また
この間隔は大きいほど空間容量を小さくできるが実用的
には5mm程度が最大で、通常1mm程度がよい。ここ
で外側の端とはGDU1〜GDU3の各高耐圧接合終端
構造HVJTおよびHVNの場合は低電位側低耐圧回路
と接する箇所、HVPの場合は高電位側低耐圧回路と接
する箇所を意味する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The reference numerals in the following drawings are the same as those described above, and the description is omitted. 1A and 1B show a first reference example. FIG. 1A shows a plan view, and FIG. 1B shows a side view. GDU in which the high-voltage junction termination structure HVJT is a high-potential-side low-voltage circuit
1 to GDU3 and a high withstand voltage n-channel MOSFET (HV
N) and a high withstand voltage p-channel MOSFET (HVP). High withstand voltage n-channel MOSFE
T (HVN) and high withstand voltage p-channel MOSFET (H
VP) means that the drain electrode has a high withstand voltage junction termination structure HVJT
, The source electrode and the gate electrode are arranged outside the loop of the high-breakdown-voltage junction termination structure HVJT. And a high-breakdown-voltage n-channel MOSFET (HVN)
Drain electrode DN and GDU1, high breakdown voltage p-channel MO
Drain electrode D P and the LSU and the S of the SFET (HVP)
They are connected at IN1 and SOUT1, respectively. This S
IN1 and SOUT1 are formed by bonding wires such as gold wires. In addition, the space between the outer end of each of the high-breakdown-voltage junction termination structures HVJT of GDU1 to GDU3 and the outside end of each of the high-breakdown-voltage junction termination structures HVJT of HVN and HVP and the bonding wire are separated by 100 μm or more, so that the space capacity (floating) is increased. Capacity) can be reduced by an order of magnitude. The larger the distance, the smaller the space capacity can be, but practically the maximum is about 5 mm, and usually about 1 mm is good. Here, the outer end means a portion in contact with the low-potential-side low-voltage circuit in the case of each of the high-voltage junction termination structures HVJT and HVN of GDU1 to GDU3, and a portion in contact with the high-potential-side low-voltage circuit in the case of HVP.

【0017】図2は第二参考例で、同図(a)は平面
図、同図(b)は側面図を示す。高耐圧接合終端構造H
VJTがGDU4〜GDU6とCUおよびLSUとで構
成される低電位側低耐圧回路、GDU1〜GDU3、高
耐圧nチャネルMOSFET(HVN)および高耐圧p
チャネルMOSFET(HVP)にそれぞれ設けられ、
高耐圧nチャネルMOSFET(HVN)とGDU1、
高耐圧pチャネルMOSFET(HVP)とLSUとが
SIN1およびSOUT1で接続される。このSIN
1、SOUT1は金線などのボンディングワイヤであ
る。またGDU1〜GDU3の各高耐圧接合終端構造H
VJTの外側の端、およびHVN、HVPの高耐圧接合
終端構造HVJTの外側の端とボンディングワイヤとは
100μm以上離すことによって、前記と同様の効果が
得られる。
2A and 2B show a second reference example. FIG. 2A is a plan view, and FIG. 2B is a side view. High withstand voltage junction termination structure H
VJT is composed of GDU4 to GDU6, CU and LSU, low potential side low withstand voltage circuit, GDU1 to GDU3, high withstand voltage n-channel MOSFET (HVN) and high withstand voltage p
Provided in each channel MOSFET (HVP),
High withstand voltage n-channel MOSFET (HVN) and GDU1,
A high-breakdown-voltage p-channel MOSFET (HVP) and LSU are connected at SIN1 and SOUT1. This SIN
1, SOUT1 is a bonding wire such as a gold wire. Also, each of the high-breakdown-voltage junction termination structures H of GDU1 to GDU3
The same effect as described above can be obtained by separating the bonding wire from the outer end of the VJT and the outer end of the HVN, HVP high-breakdown-voltage junction termination structure HVJT by at least 100 μm.

【0018】図3は第三参考例で、同図(a)は平面
図、同図(b)は側面図を示す。高耐圧接合終端構造H
VJTがチップ周辺部、GDU1〜GDU3、高耐圧n
チャネルMOSFET(HVN)および高耐圧pチャネ
ルMOSFET(HVP)にそれぞれ設けられ、高耐圧
nチャネルMOSFET(HVN)とGDU1、高耐圧
pチャネルMOSFET(HVP)とLSUとがSIN
1およびSOUT1で接続される。このSIN1、SO
UT1は金線などのボンディングワイヤである。またG
DU1〜GDU3の各高耐圧接合終端構造HVJTの外
側の端、およびHVN、HVPの高耐圧接合終端構造H
VJTの外側の端とボンディングワイヤとは100μm
以上離すことによって、前記と同様の効果が得られる。
3A and 3B show a third reference example, wherein FIG. 3A is a plan view and FIG. 3B is a side view. High withstand voltage junction termination structure H
VJT is at the chip periphery, GDU1 to GDU3, high withstand voltage n
The channel MOSFET (HVN) and the high-breakdown-voltage p-channel MOSFET (HVP) are provided respectively, and the high-breakdown-voltage n-channel MOSFET (HVN) and GDU1, and the high-breakdown-voltage p-channel MOSFET (HVP) and LSU are SIN.
1 and SOUT1. This SIN1, SO
UT1 is a bonding wire such as a gold wire. G
DU1 to GDU3, the outer end of each high-breakdown-voltage junction termination structure HVJT, and the HVN, HVP high-breakdown-voltage junction termination structure H
The outer edge of the VJT and the bonding wire are 100 μm
With the above separation, the same effect as described above can be obtained.

【0019】図4は第四参考例の平面図を示す。図7の
高耐圧ICの構成するゲート駆動ユニットICであるG
DUIC1〜GDUIC6を個別のベアチップ(裸のチ
ップのこと)で製作し、その他の構成要素であるHV
N、HVP、LSU、CUで構成される高耐圧のIC
(HV−IC)をそれらとは別のベアチップで製作し、
これらのベアチップをプリント板PCB上に配置する。
HVNのドレイン電極DNとSIN1の一端とボンディ
ングワイヤで接続され、HVPのソース電極SP 、ゲー
ト電極GP とVDDH1、SOUT1との一端とそれぞれボ
ンディングワイヤで接続される。HVNは、ドレイン電
極が高耐圧接合終端構造HVJTの内側で、ソース電極
とゲート電極が外側である。 HVPは、ドレイン電極
が高耐圧接合終端構造HVJTの外側で、ソース電極と
ゲート電極が内側である。また、この他図中の円弧はボ
ンディングワイヤでの接続を示している。このボンディ
ングワイヤと高耐圧接合終端構造HVJTとは100μ
m以上離すことで空間容量を減らす。前記のベアチップ
の代わりに、当然ながらパッケージに組み立てたものを
用いてもよい。また個別チップ化されたGDUIC1〜
GDUIC6をインテリジェントパワーモジュール(I
PM)内に組み込み、この機能を除いた高耐圧のIC
(HV−IC)が組み込まれたプリント板をIPMのケ
ース上に搭載する場合もある。
FIG. 4 is a plan view of the fourth reference example. G which is a gate drive unit IC included in the high breakdown voltage IC of FIG.
DUIC1 to GDUIC6 are manufactured by individual bare chips (naked chips), and the other components HV
High withstand voltage IC composed of N, HVP, LSU, CU
(HV-IC) is manufactured with another bare chip,
These bare chips are arranged on a printed circuit board PCB.
Is connected at one end with a bonding wire of the drain electrode D N and SIN1 of HVN, the source electrode S P output HVP, is connected at one end and the bonding wires each of the gate electrode G P and V DDH1, SOUT1. In the HVN, the drain electrode is inside the high breakdown voltage junction termination structure HVJT, and the source electrode and the gate electrode are outside. In the HVP, the drain electrode is outside the high breakdown voltage junction termination structure HVJT, and the source electrode and the gate electrode are inside. In addition, the arcs in the figures indicate connections by bonding wires. The bonding wire and the high-voltage junction termination structure HVJT are 100 μm.
m or more to reduce space capacity. Instead of the bare chip, a chip assembled in a package may of course be used. GDUIC1 to individual chip
GDUIC6 is connected to an intelligent power module (I
High-voltage IC integrated into PM) and excluding this function
(HV-IC) may be mounted on the IPM case.

【0020】図5は第一実施例で、高耐圧レベルシフト
回路図を示す。電圧発生手段であるRN1、RP1、負荷手
段であるRN2、RP2には抵抗もしくはデプレツ ションモ
ードのMOSFETなどによる定電流源を用いるのがよ
い。電圧制限手段であるZN1、ZP1はツェナーダイオー
ドを用いてもよいが、MOSダイオード(MOSFET
のソースとゲートを短絡してダイオードとして用いたも
の)を用いるほうがツェナー電圧を低く抑えられるので
優れている。電流制限手段であるRN3、RP3は抵抗で、
この場合、MOSダイオードであるZN1、ZP1に流れる
電流を制限するために付加してあるが、流れる電流を制
限する必要が無い場合は当然この抵抗は付加しなくても
良い。
FIG. 5 is a diagram showing a high voltage level shift circuit according to the first embodiment. A constant current source such as a resistor or a depletion mode MOSFET is preferably used for R N1 and R P1 as voltage generating means and R N2 and R P2 as load means. Zener diodes may be used for the voltage limiting means Z N1 and Z P1 , but MOS diodes (MOSFETs)
(Which is used as a diode with its source and gate short-circuited) is superior since the Zener voltage can be kept low. R N3 and R P3 which are current limiting means are resistors,
In this case, the resistor is added to limit the current flowing through the MOS diodes Z N1 and Z P1. However, if it is not necessary to limit the flowing current, the resistor may be omitted as a matter of course.

【0021】尚、「パワーデバイスの主端子のうちどち
らか一方を基準とした低電圧電源により電流を供給され
る高電位側低耐圧回路部分」の文章中で、どちらか一方
とは、高電位側のパワーデバイスがnチャネル素子の場
合は負荷側が基準となり、pチャネル素子の場合には電
源側が基準となることを意味している。ここで基準とな
るとは、パワーデバイスのソース(エミッタ)電極が基
準電位点(通称アース点)となることを意味する。
In the text of "the high-potential-side low-withstand-voltage circuit portion to which a current is supplied by a low-voltage power supply with reference to one of the main terminals of the power device", one of them is a high potential. When the power device on the side is an n-channel element, the load side is the reference, and when the power device is a p-channel element, the power supply side is the reference. Here, "becoming a reference" means that the source (emitter) electrode of the power device becomes a reference potential point (commonly called a ground point).

【0022】高耐圧nチャネルもしくはpチャネルトラ
ンジスタにはMOSFETが適しているが、JFET
(接合型電界効果トランジスタ)、バイポーラトランジ
スタ、IGBT(絶縁ゲート型トランジスタ)、SIT
(静電誘導型トランジスタ)などのトランジスタでもよ
い。また信号配線(SIN1、SOUT1など)には金
線を用いるがアルミ線でもよい。高耐圧接合終端構造H
VJTの信号配線との電位が大きく異なる側と、信号配
線との距離が100μm以上あると、信号配線の電位の
影響が高耐圧接合終端構造HVJTに殆ど影響を及ぼす
ことなく、また信号配線と高耐圧接合終端構造HVJT
間の放電現象も生じなくなる。
MOSFETs are suitable for high-breakdown-voltage n-channel or p-channel transistors.
(Junction field effect transistor), bipolar transistor, IGBT (insulated gate transistor), SIT
(Electrostatic induction type transistor) or the like. Gold wires are used for the signal wires (SIN1, SOUT1, etc.), but aluminum wires may be used. High withstand voltage junction termination structure H
If the distance between the VJT and the signal wiring is largely different from the signal wiring and the distance between the VJT and the signal wiring is 100 μm or more, the influence of the potential of the signal wiring hardly affects the high-breakdown-voltage junction termination structure HVJT. Withstand voltage junction termination structure HVJT
No intervening discharge phenomenon occurs.

【0023】[0023]

【発明の効果】この発明によると、信号配線による高耐
圧接合終端構造の耐圧低下の影響を小さくし、低コスト
で高性能な高耐圧ICが実現できる。さらにこれらを用
いて低コストで高性能なパワーデバイスの駆動回路を実
現できる。
According to the present invention, the effect of lowering the breakdown voltage of the high breakdown voltage junction termination structure due to the signal wiring is reduced, and a low-cost, high-performance IC with high breakdown voltage can be realized. Furthermore, a driving circuit for a high-performance power device at low cost can be realized by using these.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第一参考例で、(a)は平面図、
(b)は側面図
FIG. 1 is a first embodiment of the present invention, wherein (a) is a plan view,
(B) is a side view

【図2】この発明の第二参考例で、(a)は平面図、
(b)は側面図
2A is a plan view of a second embodiment of the present invention, FIG.
(B) is a side view

【図3】この発明の第三参考例で、(a)は平面図、
(b)は側面図
3A is a plan view of a third embodiment of the present invention, FIG.
(B) is a side view

【図4】この発明の第四参考例の平面図FIG. 4 is a plan view of a fourth embodiment of the present invention;

【図5】この発明の第一実施例の高耐圧レベルシフト回
路図
FIG. 5 is a diagram showing a high voltage level shift circuit according to the first embodiment of the present invention;

【図6】モータ制御用インバータのパワー部分を中心に
説明する回路構成図
FIG. 6 is a circuit configuration diagram mainly illustrating a power portion of a motor control inverter;

【図7】図6で用いられる高耐圧IC(HVIC)の内
部構成ユニットのブロック図
FIG. 7 is a block diagram of an internal configuration unit of a high withstand voltage IC (HVIC) used in FIG. 6;

【図8】図7のGDU1とIGBTQ1のさらに詳細な
接続図
FIG. 8 is a more detailed connection diagram of GDU1 and IGBTQ1 of FIG. 7;

【図9】図6と同一回路をインテリジェントパワーモジ
ュールと呼ばれる製品を用いて構成した構成図
FIG. 9 is a configuration diagram in which the same circuit as in FIG. 6 is configured using a product called an intelligent power module.

【図10】図9のIGBTQ1およびGDU1のまわり
の回路を詳細に示した図
FIG. 10 is a diagram showing a circuit around IGBT Q1 and GDU1 of FIG. 9 in detail;

【図11】図7に示した高耐圧IC(HVIC)のチッ
プの平面図
FIG. 11 is a plan view of the high-voltage IC (HVIC) chip shown in FIG. 7;

【符号の説明】[Explanation of symbols]

HVIC 高耐圧IC HVJT 高耐圧接合終端構造 VDD1 ドライブ電源 S ソース端子 D ドレイン端子 G ゲート端子 Q1 パワーデバイス(IGBT) Q2 パワーデバイス(IGBT) Q3 パワーデバイス(IGBT) Q4 パワーデバイス(IGBT) Q5 パワーデバイス(IGBT) Q6 パワーデバイス(IGBT) D1 パワーデバイス(ダイオード) D2 パワーデバイス(ダイオード) D3 パワーデバイス(ダイオード) D4 パワーデバイス(ダイオード) D5 パワーデバイス(ダイオード) D6 パワーデバイス(ダイオード) Mo モータ VCC 主電源 PC フォトカプラ I/O 入出力端子 CU 制御回路 LSU レベルシフト回路 GDU1 ゲート駆動回路 GDU2 ゲート駆動回路 GDU3 ゲート駆動回路 GDU4 ゲート駆動回路 GDU5 ゲート駆動回路 GDU6 ゲート駆動回路 SIN 入力ライン SOUT 出力ライン VDDC 共通電源 VDDHC 共通電源の高電位側 VDDLC 共通電源の低電位側 VDD ドライブ電源 VDDH1 ドライブ電源の高電位側 VDDH2 ドライブ電源の高電位側 VDDH3 ドライブ電源の高電位側 VDDL1 ドライブ電源の低電位側 VDDL2 ドライブ電源の低電位側 VDDL3 ドライブ電源の低電位側 OUT ゲート駆動端子 OC 電流検出端子 OT 温度検出端子 M 電流検出端子(IGBT側) Temp 温度検出端子(温度検出素子側) θ 温度検出素子 K カソード A アノード U U相 HVN 高耐圧nチャネルMOSFET HVP 高耐圧pチャネルMOSFET DN ドレイン電極 DP ドレイン電極 SP ソース電極 GP ゲート電極HVIC High voltage IC HVJT High voltage junction termination structure V DD1 Drive power supply S Source terminal D Drain terminal G Gate terminal Q1 Power device (IGBT) Q2 Power device (IGBT) Q3 Power device (IGBT) Q4 Power device (IGBT) Q5 Power device (IGBT) Q6 Power device (IGBT) D1 Power device (diode) D2 Power device (diode) D3 Power device (diode) D4 Power device (diode) D5 Power device (diode) D6 Power device (diode) Mo Motor V CC main Power supply PC Photocoupler I / O I / O terminal CU control circuit LSU Level shift circuit GDU1 Gate drive circuit GDU2 Gate drive circuit GDU3 Gate drive circuit GDU4 Over gate drive circuit GDU5 gate drive circuit GDU6 gate drive circuit SIN input line SOUT output line V DDC common power V DDHC high potential side V DDLC low potential side V DD drive power V DDH1 high potential side of the drive power of the common power of the common power V ddH 2 drive power of the high-potential side V DDH3 drive power supply of the high-potential side V DDL1 drive power supply on the low potential side V DDL2 drive power supply on the low potential side V DDL3 drive power supply on the low potential side OUT gate drive terminal OC current detection terminal OT temperature Detection terminal M Current detection terminal (IGBT side) Temp Temperature detection terminal (Temperature detection element side) θ Temperature detection element K Cathode A Anode U U-phase HVN High voltage n-channel MOSFET HVP High voltage p-channel MOSFET D N drain electrode D P drain Electrode SP source electrode GP gate electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H03K 19/018 Fターム(参考) 5F048 AB10 AC06 AC10 BH04 5J055 AX47 BX16 CX20 DX22 EX07 EY13 EZ20 EZ62 FX05 FX12 FX34 GX01 GX02 GX08 5J056 AA00 AA32 BB14 BB44 BB59 CC12 DD17 DD28 DD56 FF09 GG09 KK02 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H03K 19/018 F-term (Reference) 5F048 AB10 AC06 AC10 BH04 5J055 AX47 BX16 CX20 DX22 EX07 EY13 EZ20 EZ62 FX05 FX12 FX34 GX01 GX02 GX08 5J056 AA00 AA32 BB14 BB44 BB59 CC12 DD17 DD28 DD56 FF09 GG09 KK02

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】高電圧電源の高電位側に主端子の一方が接
続され、負荷に主端子の他方が接続された1個以上のパ
ワーデバイスのゲートを駆動するための高耐圧ICの高
耐圧レベルシフト回路であって、高電圧電源の低電位側
を基準とした低電圧電源により電流を供給される低電位
側低耐圧回路部分の信号を前記パワーデバイスの主端子
のうちどちらか一方を基準とした低電圧電源により電流
が供給される高電位側低耐圧回路部分への信号に変換す
るレベルシフト回路であって、高耐圧nチャネルトラン
ジスタのドレイン(コレクタ)電極に第1の負荷手段と
第1の電圧制限手段の一方の端子が接続され、第1の負
荷手段と第1の電圧制限手段の他方の端子が高電位側低
耐圧回路部分の低電圧電源の高電位側に接続され、第1
の電圧発生手段が高耐圧nチャネルトランジスタのソー
ス(エミッタ)電極と低電位側低耐圧回路部分の低電圧
電源の低電位側との間に接続され、第2の電圧制限手段
が高耐圧nチャネルトランジスタのゲート(ベース)電
極と低電位側低耐圧回路部分の低電圧電源の低電位側と
の間に接続され、高耐圧nチャネルトランジスタのゲー
ト(ベース)電極へ低電位側低耐圧回路部分からの信号
が入力され、高耐圧nチャネルトランジスタのドレイン
(コレクタ)電極から高電位側低耐圧回路部分への信号
が出力されることを特徴とする高耐圧ICの高耐圧レベ
ルシフト回路。
A high withstand voltage of a high withstand voltage IC for driving a gate of one or more power devices having one of main terminals connected to a high potential side of a high voltage power supply and the other of the main terminals connected to a load. A level shift circuit, wherein a signal of a low-potential-side low-withstand-voltage circuit portion supplied with current by a low-voltage power supply with reference to a low-potential side of a high-voltage power supply is referenced to one of the main terminals of the power device. A level shift circuit for converting a signal to a high-potential-side low-withstand-voltage circuit portion to which a current is supplied by a low-voltage power supply, wherein a first load means and a first load means are connected to a drain (collector) electrode of a high-withstand-voltage n-channel transistor. One terminal of the first voltage limiting means is connected, and the other terminal of the first load means and the other terminal of the first voltage limiting means are connected to the high potential side of the low voltage power supply in the high potential side low withstand voltage circuit portion. 1
Is connected between the source (emitter) electrode of the high-breakdown-voltage n-channel transistor and the low-potential side of the low-voltage power supply in the low-potential-side low-breakdown-voltage circuit portion, and the second voltage limiting means is connected to the high-breakdown-voltage n-channel transistor. It is connected between the gate (base) electrode of the transistor and the low-potential side of the low-voltage power supply in the low-potential-side low-withstand-voltage circuit portion. And a signal from the drain (collector) electrode of the high-breakdown-voltage n-channel transistor to a high-potential-side low-breakdown-voltage circuit portion is output.
【請求項2】第2の電圧制限手段がゲート(ベース)と
ドレイン(コレクタ)とを接続したnチャネルMOSダ
イオードで構成されることを特徴とする請求項1に記載
の高耐圧ICの高耐圧レベルシフト回路。
2. The high withstand voltage IC according to claim 1, wherein said second voltage limiting means comprises an n-channel MOS diode having a gate (base) and a drain (collector) connected to each other. Level shift circuit.
【請求項3】高電圧電源の高電位側に主端子の一方が接
続され、負荷に主端子の他方が接続された1個以上のパ
ワーデバイスのゲートを駆動するための高耐圧ICの高
耐圧レベルシフト回路であって、前記パワーデバイスの
主端子のうちどちらか一方を基準とした低電圧電源によ
り電流が供給される高電位側低耐圧回路部分の信号を、
前記高電圧電源の低電位側を基準とした低電圧電源によ
り電流を供給される低電位側低耐圧回路部分への信号に
変換するレベルシフト回路であって、高耐圧pチャネル
トランジスタのドレイン(コレクタ)電極に第2の負荷
手段と第3の電圧制限手段の一方の端子が接続され、第
2の負荷手段と第3の電圧制限手段の他方の端子が低電
位側低耐圧回路部分の低電圧電源の低電位側に接続さ
れ、第2の電圧発生手段が高耐圧pチャネルトランジス
タのソース(エミッタ)電極と高電位側低耐圧回路部分
の低電圧電源の高電位側との間に接続され、第4の電圧
制限手段が高耐圧pチャネルトランジスタのゲート(ベ
ース)電極と高電位側低耐圧回路部分の低電圧電源の高
電位側との間に接続され、高耐圧pチャネルトランジス
タのゲート(ベース)電極へ高電位側低耐圧回路部分か
らの信号が入力され、高耐圧pチャネルトランジスタの
ドレイン(コレクタ)電極から高電位側低耐圧回路部分
への信号が出力されることを特徴とする高耐圧レベルシ
フト回路。
3. A high withstand voltage of a high withstand voltage IC for driving a gate of one or more power devices having one of the main terminals connected to the high potential side of the high voltage power supply and the other of the main terminals connected to the load. A level shift circuit, wherein a signal of a high-potential-side low-withstand-voltage circuit portion to which a current is supplied from a low-voltage power supply based on one of the main terminals of the power device,
A level shift circuit for converting a signal to a low-potential-side low-withstand-voltage circuit portion to which a current is supplied from a low-voltage power supply with reference to a low-potential side of the high-voltage power supply, wherein a drain (collector) of a high-withstand-voltage p-channel transistor is provided. One terminal of the second load means and one terminal of the third voltage limit means is connected to the electrode, and the other terminals of the second load means and the third voltage limit means are connected to the low voltage of the low potential side low withstand voltage circuit portion. A second voltage generator connected between the source (emitter) electrode of the high-breakdown-voltage p-channel transistor and the high-potential side of the low-voltage power supply in the high-potential-side low-breakdown-voltage circuit portion; Fourth voltage limiting means is connected between the gate (base) electrode of the high-breakdown-voltage p-channel transistor and the high-potential side of the low-voltage power supply in the high-potential-side low-breakdown-voltage circuit portion. A high withstand voltage level characterized in that a signal from a high withstand voltage low withstand voltage circuit portion is input to the electrode, and a signal from the drain (collector) electrode of the high withstand voltage p-channel transistor to the high withstand voltage low withstand voltage circuit portion is output. Shift circuit.
【請求項4】第4の電圧制限手段がゲート(ベース)と
ドレイン(コレクタ)とを接続したpチャネルMOSダ
イオードで構成されることを特徴とする請求項3に記載
の高耐圧レベルシフと回路。
4. The high voltage level shifter and circuit according to claim 3, wherein the fourth voltage limiting means comprises a p-channel MOS diode having a gate (base) and a drain (collector) connected.
JP2001123762A 1995-06-28 2001-04-23 High withstand voltage level shift circuit for high withstand voltage IC Expired - Lifetime JP3384399B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001123762A JP3384399B2 (en) 1995-06-28 2001-04-23 High withstand voltage level shift circuit for high withstand voltage IC

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP16213995 1995-06-28
JP7-162139 1995-06-28
JP2001123762A JP3384399B2 (en) 1995-06-28 2001-04-23 High withstand voltage level shift circuit for high withstand voltage IC

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP25847295A Division JP3228093B2 (en) 1995-06-28 1995-10-05 High voltage IC

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