JP2002022810A - Semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus by which the oscillation frequency of a DUT can be measured in synchronization with pattern data. SOLUTION: In the semiconductor testing apparatus, a frequency counter in which the measurement of the oscillation frequency of the DUT is performed by a start signal is installed. A timer which generates start pulses at the programmed delay time in synchronization with a clock by receiving data on a test pattern is installed. A solution means which uses the start pulses as the start signal of the frequency counter is installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor test apparatus capable of measuring an oscillation frequency of a device under test in synchronization with a test pattern.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. First, a configuration example of the semiconductor test apparatus and an outline of the operation will be described. As shown in FIG. 3, the semiconductor test apparatus includes a tester processor 10, a timing generator 40, a pattern generator 50, a waveform shaper 60,
Each unit of the logical comparator 70 and the pin electronics 80 are configured. Then, the semiconductor test apparatus executes a test program to execute a device under test (hereinafter, DUT).
Test).

The tester processor 10 includes a tester bus 10
This is a processor that controls each unit connected to 0 by a test program. The tester bus 100 is a control bus that controls each unit of the semiconductor test device. Hereinafter, the operation of each unit will be described in relation to signals.

The pattern generator 50 generates logical data in synchronization with the basic clock signal output from the timing generator 40.

[0005] In the waveform shaper 60, a test pattern is generated by the logic data from the pattern generator 50 and the clock signal from the timing generator 40.

[0006] In the pin electronics 80, the test pattern is amplified to a desired voltage level by the driver 81 and output to the input pin of the DUT 90. The output signal from the output pin of the DUT 90 is
The comparator 82 compares the voltages and outputs a logical signal.

In the logical comparator 70, the DUT 9 is output at the timing of the strobe signal from the timing generator 40.
A logical output signal of 0 and an expected value from the pattern generator 50 are logically compared to perform a pass / fail determination.

Next, the types of devices whose oscillation frequency is measured by a semiconductor test apparatus will be described. (1) A device that oscillates just by supplying power to a device.
For example, MCU (Micro Control
ler Unit). (2) A device that oscillates only when the mode pin is set to some state (for example, high level). For example, a PLL (Phas
e Locked Loop) circuit and DLL (Delay Locked Lo)
op) There is an IC with a built-in circuit. (3) A device that oscillates after a clock is supplied from a semiconductor test device. For example, a PLL circuit or I
There is C. (4) A device which oscillates after inputting a clock and a certain set pattern from a semiconductor test apparatus. For example, PL
There are ICs with built-in L circuits and DLL circuits. (5) When a certain set pattern is input from a semiconductor test apparatus, a self-propelled oscillation is started and output. For example, there is an LSI with a built-in process monitor loop oscillation circuit.

In the device (1), the device power is turned on, and the frequency counter 21 is designated and started in a user's sequence program to start the frequency measurement. The devices (2) to (5) turn on the device power, start a test pattern, wait for a time until the frequency is sufficiently stabilized,
Is specified in the user's sequence program and started to measure the frequency.

Next, the DUT 90 is operated by the semiconductor test apparatus.
The operation for measuring the oscillation frequency of the device will be described with reference to FIG. 4 and the timing chart of FIG.
As shown in FIG. 4, the main parts of the logical comparator 70 include a NOR gate 12, a D latch 20, and an EXC-OR gate 19
, Frequency counter 21, start command generator 3
0.

The oscillation signal of the DUT 90 is supplied to the comparator 8
2, the voltage is compared and input to the data of the D latch 20. To measure the frequency, the frequency measurement mode (FREQ) of the NOR gate 12 input is set to high (HIGH), the clock input of the D latch 20 is set to low (LOW), and the data input is output to the frequency counter 21 through.

When performing a logical comparison in the test of the logic output pin of the DUT 90, a strobe (STRB) is input to the input of the NOR gate 12, and the logic data latched at the timing of the strobe (STRB) is output from the D latch 20. ing. Further, the EXC-OR gate 14 performs a logical comparison with the expected value (EXP) to pass / fail (PASS / FALSE).
FAIL) and outputs a fail (FAIL) signal.

In the frequency counter 21, the output signal 600 of the D-latch 20 shown in FIG.
The frequency of the reference clock (CLK) shown in FIG. 5D is counted at the timing of the start signal (START), and the DUT is counted.
90 oscillation frequencies are calculated and measured.

On the other hand, the start command generator 30 synchronizes the bus start signal (BUS-START) of the tester bus 100 shown in FIG. 5C with a clock (CLK) shown in FIG. The pulse 110 of the start command delayed by a predetermined clock shown in FIG. 5E is used as a start signal (START) for the count operation of the frequency counter 21. Here, the bus start signal (BUS-START) of the tester bus 100 is a signal giving a timing for recognizing a control signal of the tester bus.

Next, the oscillation frequency characteristic of the DUT 90 with respect to time t will be described with reference to FIG. The oscillation frequency characteristic p shown in FIG. 5A shows a case where the power supply of the DUT 90 is turned on at T1. The oscillation frequency characteristic q is
The case where the power supply of the DUT 90 is turned on at T1 and the pattern is started at T2 to oscillate inside the DUT 90 but not output to the external pin is shown. The oscillation frequency characteristic r indicates a case where the power of the DUT 90 is turned on at T1 and the DUT 90 is oscillated after the condition setting becomes effective.

When measuring the oscillation frequency of the DUT 90, the apparatus waits for a time according to the following equation (1) in which the oscillation frequency of the DUT 90 can be measured stably. Wait time = power ON of DUT 90 + offset of actual start time of pattern start + pattern execution time + α (margin time) (1) Here, the first and second terms on the right side of equation (1) are Since the oscillation frequency fluctuates due to internal factors, the waiting time is programmed by adding an α time (a margin time) at which the oscillation frequency is considered to be sufficiently stable. For example, the start signal (START) for the count operation of the frequency counter 21 is the start command pulse 110 shown in FIG. 5E, and the bus start signal (BUS-START) in FIG. The synchronization is generated with a sufficient delay after that, and is generated at a time T5 shown in FIG.

Therefore, when measuring the oscillation frequency of the DUT 90, if the setting of the waiting time takes a margin of + α too much, the throughput becomes worse, and if the margin of + α is small, the oscillation frequency becomes unstable. There were problems such as measurement. In addition, since the start command of the frequency counter 21 is executed in a plurality of steps, the test time is extended, and the command is varied depending on the speed at which the program is executed from the tester processor. Further, when oscillation is performed after the condition setting for the DUT 90 becomes effective, it is difficult to measure the transition characteristic of the excessive oscillation frequency.

[0018]

As described above, D
When measuring the oscillation frequency of the UT 90, if the setting of the waiting time takes a margin of + α too much, the throughput deteriorates, and if the margin of + α is short, measurement is performed in a state where the oscillation frequency is not stable. There was a problem. Further, when the oscillation is performed after the condition setting for the DUT 90 becomes effective, it is difficult to measure the transition characteristic of the excessive oscillation frequency. The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor test apparatus capable of measuring an oscillation frequency of a DUT in synchronization with pattern data.

[0019]

A first object of the present invention to achieve the above object is to provide a semiconductor test apparatus provided with a frequency counter for measuring an oscillation frequency of a DUT by a start signal. The semiconductor test apparatus is characterized in that a start signal of the frequency counter is generated in synchronization with the above data.

A second aspect of the present invention to achieve the above object is to provide a semiconductor test apparatus provided with a frequency counter for measuring an oscillation frequency of a DUT based on a start signal. A semiconductor test apparatus is characterized in that a timer that generates a start pulse with a programmed delay time in synchronization with a timer is provided, and the start pulse is used as a start signal of the frequency counter.

A third aspect of the present invention, which has been made to achieve the above object, is to provide a semiconductor test apparatus provided with a frequency counter for measuring the oscillation frequency of a DUT based on a start signal. An AND gate that outputs a logical product with a start signal;
A start command generating means for receiving the logical product and outputting a start command signal; and a timer for receiving the start command and synchronizing with a clock and generating a start signal of the frequency counter with a programmed delay time. The gist of the present invention is a semiconductor test apparatus characterized in that:

A fourth aspect of the present invention, which has been made to achieve the above object, is to provide a semiconductor test apparatus provided with a frequency counter for measuring the oscillation frequency of a DUT based on a start signal. An AND gate that outputs a logical product with a start signal;
First start command generation means for receiving the logical product and outputting a start command signal; and a timer for receiving the start command and synchronizing with a clock and generating a start signal of the frequency counter with a programmed delay time. A second start command generating means for receiving the bus start signal and outputting a start command signal; and receiving and selecting the output of the second start command generating means, the output of the timer and the data output of the test pattern. And a selector for selecting a signal and providing a start signal of the frequency counter.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. The configuration example of the semiconductor test apparatus and the outline of the operation have been described in the related art, and thus will not be described. Next, an operation of measuring the oscillation frequency of the DUT 90 by the semiconductor test device will be described with reference to FIGS. As shown in FIG. 1, the main parts of the logical comparator 70 include a NOR gate 12, a D latch 20, an EXC-O
The AND gate 13, the start command generator 31, the timer 32, and the selector 16 are added to the conventional configuration of the R gate 19, the frequency counter 21, and the start command generator 30. The pattern generator 50 includes the selector 15.

As shown in FIG. 1, the oscillation signal of the DUT 90 is compared with the voltage by the comparator 82 and is input to the data of the D latch 20. When measuring the frequency, the frequency measurement mode (FREQ) of the NOR gate 12 input is set to high (HIGH), the clock input of the D latch 20 is set to low (LOW), and the data input is passed through the frequency counter 2 as in the conventional case.
Output to 1.

As in the conventional case, the output signal 60 of the D-latch 20 shown in FIG.
0, that is, the reference clock (CLK) shown in FIG.
Are counted at the timing of the start signal (START), and the oscillation frequency of the DUT 90 is calculated and measured.

Next, the frequency counter 2 in the present embodiment
Three methods for generating one start signal (START) will be described.

The first method is to generate a start signal (START) for the frequency counter 21 using only the data of the test pattern signal generated from the pattern generator 50 by executing the test program. More specifically, as shown in FIG.
The terminal input is used, and the control signal data is
5 B terminal input and selected by the mode 1 signal.
(H) of the selector 16 is output,
Input to terminal.

In the second method, the start signal (STAR) of the frequency counter 21 is set at a delay time designated in advance after the condition setting for the DUT 90 becomes effective.
T). For example, a bus start signal (BUS-START) of the tester bus 100 shown in FIG.
AND of the test pattern signal generated from the pattern generator 50 shown in FIG. 2E by the AND gate 13, and the start command generating unit 31 outputs the bus of the tester bus 100 shown in FIG. Start signal (BU
S-START) and the clock (CLK) shown in FIG.
2 and the pulse 200 delayed by a predetermined clock shown in FIG. 2E is held, and the timer 32 is started (ST
ART), a signal 300 shown in FIG. Further, the timer 32 outputs a signal 310 shown in (g) of FIG. 2 at a timing when the signal 300 is delayed by the clock (CLK) specified by the test program, and
Is input to the A terminal.

The third method is the same as the conventional method for generating a start signal (START) for the frequency counter 21.
That is, in the selector 16, the output of the signal shown in FIG. 2 (i), which is synchronously generated with a sufficient delay after the bus start signal (BUS-START) in FIG. C terminal input.

Then, the input signals of A, B, and C of the selector 16 are selected by the selection signal of the mode 2 and used as a start signal (START) of the frequency counter 21. That is,
In this embodiment, the start signal (START) of the frequency counter 21 can be arbitrarily selected from three methods.

Next, the oscillation frequency characteristic of the DUT 90 with respect to time t and the start signal (STAR
The relationship with T) will be described with reference to FIG. The signal 310 shown in FIG. 2 (g) in which the A terminal is selectively output by the selector 16 can be generated in advance with a pulse delayed by an arbitrary clock by a program, so that the oscillation of the oscillation frequency characteristic r shown in FIG. DU at the timing (T2, T3, etc.) in the transient transition time when the frequency oscillates stably
The oscillation frequency of T90 can be measured. DUT in the above way
It is also possible to improve the test throughput by measuring the timing of the time when the oscillation frequency of the 90 is stabilized and measuring the timing immediately after the oscillation frequency is stabilized.

FIG. 2 in which terminal B is selectively output by selector 16
The signal 200 shown in (h) can measure the oscillation frequency of the DUT 90 at a timing (for example, T4) determined by pattern data set in advance by a program.

[0034]

The present invention is embodied in the form described above and has the following effects. That is,
When measuring the oscillation frequency of the DUT, the start signal of the frequency counter can be arbitrarily generated with the data of the pattern programmed in advance, so that the transition characteristic of the excessive oscillation frequency of the DUT can be easily measured, and the stable operation can be achieved. The oscillation frequency also has the effect that the throughput can be measured with good throughput.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a semiconductor test apparatus of the present invention.

FIG. 2 is a timing chart of the semiconductor test apparatus of the present invention.

FIG. 3 is a block diagram of a semiconductor test apparatus.

FIG. 4 is a main part circuit diagram of a conventional semiconductor test apparatus.

FIG. 5 is a timing chart of a conventional semiconductor test apparatus.

[Explanation of symbols]

 Reference Signs List 10 tester processor 12 NOR gate 13 AND gate 14 EXC-OR 15, 16 selector 20 D-latch 21 frequency counter 30, 31 start command generator 32 timer 40 timing generator 50 pattern generator 60 waveform shaper 70 logical comparator 80 pin Electronics 81 Driver 82 Comparator 90 DUT 100 Tester bus

Claims (4)

[Claims] In a semiconductor test apparatus provided with a frequency counter for measuring an oscillation frequency of a DUT by a start signal, a start signal of the frequency counter is generated in synchronization with test pattern data. Semiconductor test equipment. 2. A semiconductor test apparatus provided with a frequency counter for measuring an oscillation frequency of a DUT by a start signal, receiving a test pattern data, synchronizing with a clock, and generating a start pulse with a programmed delay time. Wherein the start pulse is used as a start signal of the frequency counter. 3. An AND gate for outputting a logical product of test pattern data and a bus start signal of a tester bus in a semiconductor test apparatus provided with a frequency counter for measuring the oscillation frequency of a DUT based on a start signal. Receiving the start command and outputting a start command signal; and a timer that receives the start command and synchronizes with a clock and generates a start signal of the frequency counter with a programmed delay time. Characteristic semiconductor test equipment. 4. An AND gate for outputting a logical product of test pattern data and a bus start signal of a tester bus in a semiconductor test apparatus provided with a frequency counter for measuring an oscillation frequency of a DUT using a start signal. First start command generation means for receiving the start command and outputting a start command signal; a timer for receiving the start command and synchronizing with a clock and generating a start signal of the frequency counter with a programmed delay time; A second start command generating means for receiving a start signal and outputting a start command signal; and receiving an output of the second start command generating means, an output of the timer, and a data output of the test pattern, and selecting with a selection signal. And a selector for giving a start signal of the frequency counter The semiconductor testing apparatus, characterized in that the provided.