JP2002016144A - Cell with upper layer wiring terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input/output terminal structure of a cell which relaxes limit of driving ability due to electromigration at the output by avoiding electrostatic breakdown of a gate oxide film at the input. SOLUTION: An LSI is provided with a multilayer metallic wiring and consists of a fundamental gate and a large-scale functional gate. Electrostatic breakdown of a gate oxide film due to connection of a long metal wiring is prevented at the input terminal. Limit of driving ability due to electromigration is relaxed at the output terminal by raising the input/output terminal of a fundamental cell and a functional cell constituting an LSI up to an upper layer metal wiring of a thick film in a vertical direction, and connecting each input/output terminal by using mainly a metal wiring of an upper layer, so that a long signal line disposed over a wide range in a chip inside such as a signal line transfer clock and a long signal line connecting large-scale functional cells constituting an LSI can be driven with high driving ability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-scale semiconductor integrated circuit (hereinafter referred to as "LSI"), and particularly to a signal line having a long wiring length such as a clock wiring or a wiring connecting large-scale function cells. The present invention relates to a structure of an input / output terminal of a basic cell or a functional cell to be connected.

[0002]

2. Description of the Related Art Input / output units of MOS transistor circuits forming cells are connected to the lowermost metal wiring in basic cells and functional cells used in conventional semi-custom LSIs, and are used as input / output terminals of the cells. Some are taken out.

The structure of the input / output terminals of a conventional basic cell (functional cell) will be described with reference to FIG. FIG. 7 (a)
FIG. 2 is a plan view showing a structure of an input / output terminal of a CMOS inverter forming an input / output unit of a conventional basic cell. FIG.
(B) is a figure which shows the XX cross section of the input / output terminal, and the YY cross section of the output terminal.

[0004] The CMOS inverter shown in FIG.
An NMOS transistor comprising an N ⁺ source region 1 and an N ⁺ drain region 2 formed on a semiconductor substrate and a polysilicon gate 3 formed via a gate insulating film (not shown); and a P ⁺ source region 1a , And a PMOS transistor comprising a P ⁺ drain region 2 a and a polysilicon gate 3.

[0005] These NMOS transistors and PMO
The drain regions 2 and 2a of the S transistor are connected to the output drain terminal 7b of the CMOS inverter formed of the lowermost metal wiring via a contact hole 6b formed in an interlayer insulating film (not shown).

A polysilicon gate 3 common to NMOS and PMOS transistors has a contact hole 8
a is connected to the input gate terminal 9a of the CMOS inverter formed of the lowermost metal wiring through the line a. N ⁺ source region 1 of NMOS transistor and P ^{+ of} PMOS transistor
Source region 1a is connected to power supply lines 5 and 5a via contact hole 4. 7B, the XX section of the input gate terminal is shown on the left side, and the Y section of the output drain terminal is shown on the right side.
The -Y section is shown.

[0007] In the design of a semi-custom LSI, the basic cell having the above terminal structure (computer) is used by using a computer without changing the terminal structure in accordance with the number of wiring layers by using a database library. Or various functional cells) can be automatically arranged and wired.

In recent years, in order to realize a larger-scale LSI, a design that uses a portion conventionally used as a wiring region as a basic cell region, that is, a transistor region, and maximizes the surface of a semiconductor substrate has become mainstream. For this reason, three or more layers of metal wirings are often used.

However, as shown in FIG. 7, a basic cell having an input / output terminal made of a lowermost metal wiring is used to
If a clock signal line connecting between basic cells and various functional cells arranged widely and everywhere in the SI is to be wired, it is inevitable that metal wiring in the same wiring layer becomes long. .

When such a long metal wiring is formed by dry processing, if the long metal wiring is connected to the input gate terminal side of the MOS transistor via a gate oxide film, the long metal wiring is in a floating state. In addition, the gate oxide film may be electrostatically damaged due to charge-up.

In order to avoid this, it is necessary to perform automatic wiring by a computer while checking restrictions on the wiring length, usually called an antenna rule, so that the wiring length does not become excessively long. As a result, the automatic wiring takes a long time. That was a problem.

This problem will be described more specifically with reference to FIG. 8 for clock wiring of an LSI. LS shown in FIG.
I denotes a clock signal input terminal 10, a basic cell 11 forming a clock signal output buffer, a long signal line 13 for transferring a clock signal to an internal circuit of the LSI, and an internal circuit of the LSI connected to the terminal thereof. Basic cells 11-1, 11-2, 11-3 forming an input buffer for the clock signal of
And a tree-structured circuit 12- forming an internal circuit of the LSI.
1, 12-2, 12-3, and the like.

These tree-structured circuits 12-1 and 12-1
-2 and 12-3 so that the propagation time of the clock signal to the tree-structured circuits 12-1 and 12-3 is as uniform as possible.
If -2 and 12-3 are arranged in a wide area inside the LSI,
The wiring length of the signal line 13 shown in FIG.
This causes electrostatic breakdown in the gate oxide film of the MOS transistor on the input terminal side such as 1-1, 11-2, and 11-3.

Next, a basic cell 11 having input / output terminals made of the lowermost metal wiring and basic cells 11-1 and 11-
A method of forming a long signal line 13 connecting between 2 and 11-3 will be described with reference to a cross-sectional view of the conventional clock signal line 13 shown in FIG.

As described above, in order to avoid the electrostatic breakdown of the gate oxide film, a certain restriction (antenna rule) is imposed on the wiring length of the metal wiring connected to the gate oxide film side of the MOS transistor. If it is considered that there is a wiring route, the basic cells 11-1, 11-2, 11-3
Of the input gate terminal 9a, that is, the lowermost metal wiring layer on the gate oxide film side of the MOS transistor is formed by using relatively short metal wirings 15a, 17a and contact holes 14a, 16a, 18a in accordance with the antenna rule. It is lifted up to the wiring 19.

The output drain terminal 7 of the basic cell 11
b, that is, the output drain terminal 7b composed of the lowermost metal wiring on the drain side of the MOS transistor includes metal wirings 15b, 17b and contact holes 14b, 16b, 1
The output drain terminal 7b and the input gate terminal 9a are connected to each other by using the metal wiring 19 of the uppermost layer.

As described above, since the automatic wiring is performed while checking the restrictions on the wiring length on the input terminal side of the basic cell, it takes a long time for the automatic wiring. Further, when connecting large-scale function cells such as RAM or ROM constituting an LSI, a long signal line is required. In this case, the connection between the input / output terminals of the large-scale function cell is also the same. Problems had arisen.

In general, circuits constituting basic cells and functional cells are as follows:
Since it is configured using the lower thin-film metal wiring having a narrow width and a small interval, the driving capability of the cell is limited due to the restriction of the current density due to electromigration. In order to increase the driving capability of the cell using the thin film metal wiring, the width of the output drain terminal of the cell and the width of the thin film metal wiring connected thereto must be widened.

However, if the width of the thin-film metal wiring or the output drain terminal is increased in order to drive a long signal line for transferring the clock of the LSI or a long signal line for connecting large-scale functional cells constituting the LSI, There is a possibility that the wiring area for general wiring, which is usually formed of a thin film metal wiring in the lower layer, is narrowed, and the wiring efficiency for general wiring is reduced.

[0020]

As described above, LS
A long signal line is required to transfer the clock signal of I and to connect a large-scale functional cell constituting the LSI. However, a long signal line is required by using the input / output terminals of the conventional basic cell and the functional cell formed of the lowermost metal wiring. If a signal line is to be connected, automatic wiring must be performed without reducing the wiring area for general wiring under the restrictions of the antenna rule, so that there is a problem that it takes a long time to design an LSI.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has an upper layer wiring terminal capable of automatic wiring in a short time without restriction of antenna rules and without reducing a wiring area for general wiring. Basic cell (or functional cell)
It is an object of the present invention to provide an LSI having the following.

[0022]

According to the present invention, there is provided a cell with an upper wiring terminal in an LSI having a multi-layer metal wiring composed of an upper metal wiring of a thick film and a lower metal wiring of a thin film. In order to be able to drive a long signal line arranged in a wide range and a long signal line connecting large-scale function cells forming an LSI with high driving capability, basic cells and function cells forming an LSI can be driven. The input / output terminals of the gate oxide film are lifted vertically to the upper metal wiring of the thick film, and the input / output terminals are connected mainly by the upper metal wiring. It is characterized in that destruction is prevented and restrictions on the driving capability due to electromigration are eased on the output terminal side.

Specifically, the cell with an upper wiring terminal of the present invention is a plurality of MOS transistors formed on a semiconductor substrate, and at least one of a basic cell and a functional cell including the plurality of MOS transistors. The cell comprises n (n is a natural number of 3 or more) metal wiring layers;
At least one of the contact holes formed in the n-1 interlayer insulating film separating the n metal wiring layers from each other and the contact holes arranged in a direction normal to the main surface of the semiconductor substrate; And an input gate terminal connecting the lowermost metal wiring and the uppermost metal wiring in the n metal wiring layers connected to the input gates of the two MOS transistors.

The cell with an upper wiring terminal of the present invention is
The n connected to an output drain of at least one MOS transistor forming the cell through the contact hole arranged in a direction normal to the main surface of the semiconductor substrate.
And an output drain terminal for connecting the lowermost metal wiring and the uppermost metal wiring in the metal wiring layer to each other.

Further, the cell with an upper wiring terminal according to the present invention
An input gate terminal connected to an input gate of the at least one MOS transistor and an output drain terminal connected to an output drain of the MOS transistor are provided.

Preferably, the input gate terminal is an input gate terminal provided in a first cell with an upper wiring terminal, and the output drain terminal is an output drain terminal provided in a second cell with an upper wiring terminal. The input gate terminal and the output drain terminal are connected to each other by the uppermost metal wiring having the same thickness. More preferably, the thickness of the uppermost metal wiring is
The thickness is larger than the thickness of the lowermost metal wiring.

Preferably, the uppermost metal wiring is made of a metal having a high electric conductivity mainly composed of Cu, Al and Au, and more preferably the uppermost metal wiring is made of Cu, Au, W or the like. Metal, Ti / Au, Ti /
Multilayer metal such as Pt / Au, Ti / Al, and AlSi;
It is one of alloys such as AlSiCu and is characterized by high electromigration resistance.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. The first embodiment of the present invention will be described with reference to FIG.
The structure of the input / output terminal of the CMOS inverter which forms the input / output unit of the basic cell with the upper wiring terminal according to the embodiment will be described. FIG. 1A is a plan view showing the structure of the input / output terminals of the basic cell with the upper layer wiring terminals. The left side of FIG. 1B is a cross-sectional view of the input terminal taken along line XX, and the right side of FIG.
It is a Y sectional view.

In the CMOS inverter shown in FIG. 1A, the polysilicon gate 3 common to the NMOS and PMOS transistors is connected to the metal wiring 9a of the first layer via the contact hole 8a shown on the left side of FIG. 1B. The metal wiring 9a of the first layer is connected to the metal wiring 15a of the second layer via the contact hole 14a, and similarly, the metal wiring 9a of the uppermost layer extends in the direction perpendicular to the surface of the semiconductor substrate to the metal wiring 19a of the nth layer. By being electrically connected to
An input gate terminal of the basic cell with the upper wiring terminal is formed.

In the first embodiment, the output drain terminal of the basic cell is connected to the drain region 2 of the NMOS transistor and the drain region 2a of the PMOS transistor.
Are formed with first-layer metal wirings 7b connected via contact holes 6b, respectively.

The basic cells with upper wiring terminals according to the first embodiment are, for example, as shown in FIG. 8, basic cells 11-1 and 11-2 which constitute an input buffer circuit of a long signal line 13 for transferring a clock. , 11-3, etc. are suitably used as input gate terminals.

More specifically, as shown in FIG. 2, for example, the input gate terminal of the basic cell 11-1 is connected to the metal wiring 19 of the n-th layer.
a, a part of each of the first to (n−1) th metal wirings is simply transferred to the first to (n−1) th metal wirings without routing.
, And is connected to a long upper-layer metal wiring 19 forming a signal line of a clock signal at the uppermost metal wiring 19a.

According to this configuration, since each basic cell is provided with the input gate terminal vertically connected to the uppermost metal wiring, only the uppermost wiring layer or a wiring layer near the uppermost wiring layer can be used without considering the antenna rule. Can be used to connect a long signal line such as a clock, and the time required for automatic wiring by a computer can be greatly reduced.

Next, the structure of the input / output terminals of the basic cell with upper wiring terminals according to the second embodiment will be described with reference to FIG. 3 (a) is a plan view thereof, the left side of FIG. 3 (b) is an XX sectional view of an input terminal, and the right side is YY of an output terminal.
And ZZ sectional view. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

In the CMOS inverter shown in FIG. 3A, the polysilicon gate 3 common to the NMOS and PMOS transistors is connected to the contact 8a shown in FIG.
Is connected to the first-layer metal wiring 9a via the gate electrode to form an input gate terminal of the basic cell.

The feature of the basic cell of the second embodiment is that the output terminal has a structure with an upper wiring terminal.
That is, in the CMOS inverter shown in FIG.
The drain region 2a of the transistor has a contact hole 6
b is connected to the first-layer metal wiring 7b through the first
As shown in FIG. 3B, the metal wiring 7b of the layer is connected to the metal wiring 15b of the second layer via the contact hole 14b, and similarly, the metal wiring 19b of the n-th layer in the uppermost layer.
The output drain terminal of the basic cell with the upper wiring terminal is electrically connected to the semiconductor substrate surface in the vertical direction.

As shown in FIG. 3B, the allowable current density is greatly reduced by using a thicker metal wiring for the n-th metal wiring 19b than for the lower metal wirings 7b and 15b. Can be improved. For this reason, the restriction on the driving capability of the basic cell due to electromigration is eased as compared with the case where the conventional thin film metal wiring is used.

More specifically, the basic cell with upper wiring terminals shown in FIG. 3B is replaced with the basic cell 1 on the output side shown at the left end of FIG.
If it is used as 1, the input terminals of the basic cells 11-1, 11-11 are raised by vertically lifting the drain terminal up to the uppermost thick metal wiring 19 b and using the thick metal wiring 19.
Since it is connected to the input gate terminals 19a such as -2, 11-3, etc., there is no possibility of disconnection due to electromigration at the output drain terminal of the basic cell 11.

In FIG. 2, the output drain terminal 19b of the basic cell 11 raised to the uppermost layer and the input gate terminal 1 of the basic cell 11-1, 11-2, 11-3, etc.
9a, the long metal wire 19 is connected to the input gate terminal. At this time, the electric charge of the long metal wire 19 is changed to C through the output drain terminal 19b of the basic cell 11.
Since the discharge is discharged to the drain regions 2 and 2a of the MOS transistor, there is no possibility that the gate oxide film is electrostatically damaged on the input side.

The connection by the upper layer wiring is not always possible only by the longest metal wiring 19 in the uppermost layer. As shown in FIG. 2, the connection by the lower layer metal wiring 21 through the contact hole 20 is required. Can be. At this time, the metal wiring 21 temporarily floats in the wiring forming step. However, if the longest metal wiring 19 in the uppermost layer is connected, the metal wiring 21 is connected through the contact holes 20 at both ends.
Is discharged to the drain regions 2 and 2a of the CMOS transistor of the basic cell 11, there is no possibility that the gate oxide film is electrostatically damaged on the input gate terminal side.

As shown in FIG. 2, if the input gate terminal or the output drain terminal of the basic cell is vertically lifted to the uppermost metal wiring, and at least the drain terminal side is connected to the thick metal wiring, the thin film can be obtained. Without reducing the general wiring area consisting of metal wiring, the input terminal side is not restricted by the antenna rules, and the output side is not restricted by the electromigration drive capability, and the long metal wiring that transfers clocks can be shortened. Automatic wiring can be done in time.

Next, the structure of the input / output terminals of the basic cell with upper wiring terminals according to the third embodiment will be described with reference to FIG. FIG. 4A is a plan view of the input terminal, and FIG.
The left side of (b) is an XX sectional view of the input terminal, and the right side is a YY and ZZ sectional view of the output terminal. In FIG. 4, the same parts as those in FIGS. 1 and 3 are denoted by the same reference numerals, and detailed description will be omitted.

The feature of the basic cell of the third embodiment resides in that both input and output terminals have a structure with upper layer wiring terminals. That is, in the CMOS inverter shown in FIG. 4A, the polysilicon gate 3 common to the NMOS and PMOS transistors is connected to the first-layer metal wiring 9a via the contact 8a shown in FIG. The one-layer metal wiring 9a is connected to the second-layer metal wiring 15a via the contact hole 14a, and similarly, the electrical wiring is electrically perpendicular to the surface of the semiconductor substrate up to the n-th metal wiring 19a in the uppermost layer. Connected to form an input gate terminal of the basic cell with the upper wiring terminal.

The drain region 2 of the NMOS transistor and the drain region 2a of the PMOS transistor are connected to a first-layer metal interconnection 7b via a contact hole 6b.
Basic cell with upper-layer wiring terminals is connected to the second-layer metal wiring 15b via the wiring layer 4b and similarly electrically connected to the n-th metal wiring 19b in the uppermost layer in the vertical direction with respect to the surface of the semiconductor substrate. Is formed.

As shown in FIG. 4B, both the input gate terminal and the output drain terminal have the uppermost thick metal wiring line 19.
a, 19b, so that by preparing such a basic cell in advance, it is possible to easily automatically wire a long signal line for transferring a clock signal using the uppermost thick metal wiring or the like. Can be. At this time, it goes without saying that the same effects as those of the first and second embodiments can be obtained.

Next, the structure of the input / output terminals of the functional cell with upper wiring terminals according to the fourth embodiment will be described with reference to FIG. Normally, a large-scale functional cell such as a RAM or a ROM other than the basic cells is simultaneously arranged in a semi-custom LSI. For example, the LSI shown in FIG.
It is composed of large-scale function cells 31 and 32 such as RAM or ROM formed on the same semiconductor chip 30 and logic blocks 33 and 34 including a cell array of basic cells and the like.

Normally, signal lines 35 connecting large-scale function cells
Becomes very long. At this time, as shown in FIG. 5 (b), contact holes 8a, 14a, etc., the first layer, the second layer, and the like are vertically provided from the polysilicon gate 3 of the MOS transistor to the input portion of the large-scale functional cell 31. A plurality of input gate terminals which are raised to the uppermost metal wiring 19a via the metal wirings 9a and 15a of the layer are prepared.

Similarly, as shown in FIG. 5 (c), contact holes 6b and 14b are vertically provided from the drain region of the MOS transistor to the output portion of the large-scale function cell 32.
And a plurality of output drain terminals raised to the uppermost metal wiring 19b through the first and second metal wirings 9b and 15b.

As shown in FIGS. 5B and 5C, the uppermost metal wirings 19a and 19b are formed by thick metal wirings, and the uppermost metal wirings forming long signal lines are used. If the large-scale function cells 31 and 32 are connected to each other, restrictions on antenna rules and electromigration are relaxed, and the burden of automatic placement and wiring by a computer is reduced.

Next, a method of connecting the input / output terminals of the basic cell with upper wiring terminals according to the fifth embodiment will be described with reference to FIG. FIG. 6 is a cross-sectional view showing another method for connecting a long signal line for transferring a signal such as a clock using the input / output terminals of the basic cell described in the first to third embodiments.

In the method of connecting the input / output terminals of the basic gate described with reference to FIG.
It has been described that not only the metal wiring 21 but also the metal wiring 21 adjacent to the lower part via the contact hole 20 is used.

However, in the connection method according to the fifth embodiment shown in FIG. 6, the uppermost metal wirings 19a, 19, which constitute the input / output terminals of the basic cell described in the first to third embodiments, are used.
A feature is that a thick-film metal wiring 23 serving as a transfer path for a clock or the like is connected from b or these lead wirings 19 through a contact hole 22.

That is, the uppermost metal wiring 19b on the output side of the basic gate 35-1 and the uppermost metal wiring on the input side of the basic gates 35-2, 35-3, 35-4 of the fifth embodiment. 19a is connected via a contact hole 22 using only a thick metal wiring 23 which is a transfer path for a clock signal or the like.

As described above, when the basic cells are automatically wired,
If the computer is instructed to connect the basic cell only with the thick metal wiring 23 serving as a transfer path for a clock signal or the like, and not connected to the lower metal wiring region,
The lower metal wiring is connected to a general signal connection wiring area 36-
1, 36-2, 36-3, etc., it is possible to efficiently utilize general metal wiring areas without narrowing them.

As described in each of the above embodiments, the long metal wiring connected to the uppermost layer or its vicinity is formed of Cu, Al, A, or A in order to enhance the driving capability on the output side of the cell.
It is desirable to be composed of a metal material having a high electric conductivity mainly composed of u. Further, since a large drive current on the output side of the cell flows through the long metal wiring connected to the uppermost layer or its vicinity, these metal wirings are made of Cu, Au,
Simple metals such as W, Ti / Au, Ti / Pt / Au, Ti
It is desirable to use a material having high electromigration resistance, such as a multilayer metal such as / Al or an alloy such as AlSi or AlSiCu.

The present invention is not limited to the above embodiment. For example, in the fifth embodiment, the connection of the input / output terminals of the basic cells has been described as an example, but the connection is not necessarily limited to the connection of the input / output terminals of the basic cells. The fifth embodiment can be similarly implemented when connecting the input / output terminals of a functional cell or a large-scale functional cell.

The structure and connection method of the basic cell with upper wiring and the functional cell of the present invention are not limited to the first to fifth embodiments, but many modifications can be derived by combining them. All of these variations are within the scope of the present invention. In addition, various modifications can be made without departing from the spirit of the present invention.

[0058]

As described above, if the basic cell and the functional cell with the upper wiring terminal of the present invention are used, the input / output terminals of the basic cell and the functional cell are connected mainly by the upper thick film metal wiring. Without reducing the thin metal wiring area for general signal lines, it is possible to avoid the electrostatic breakdown of the gate oxide film on the input gate terminal side without being restricted by the antenna rules, and to use electromigration on the output drain terminal side. It is possible to ease the limitation on the driving ability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of an input / output terminal of a basic cell according to a first embodiment, where (a) is a plan view of a CMOS inverter and an input / output terminal. (B) is a sectional view of an input / output terminal.

FIG. 2 is a diagram showing a method of connecting a basic cell with an upper wiring terminal according to the present invention.

FIG. 3 is a diagram showing the structure of input / output terminals of a basic cell according to a second embodiment, in which (a) is a plan view of a CMOS inverter and input / output terminals. (B) is a sectional view of an input / output terminal.

FIG. 4 is a diagram showing a structure of an input / output terminal of a basic cell according to a third embodiment, where (a) is a plan view of a CMOS inverter and an input / output terminal. (B) is a sectional view of an input / output terminal.

FIG. 5 is a diagram showing a configuration of a semi-custom LSI according to a fourth embodiment, in which (a) is a layout diagram showing connections of large-scale function cells. (B) is sectional drawing of an input gate terminal. (C) is a sectional view of the output drain terminal.

FIG. 6 is a diagram showing another connection method of the basic cell with the upper wiring terminal of the present invention.

FIG. 7 is a diagram showing the structure of input / output terminals of a conventional basic cell, where (a) is a plan view of a CMOS inverter and input / output terminals. (B) is a sectional view of an input / output terminal.

FIG. 8 is a diagram showing a connection method of a clock signal line of an LSI having a tree structure internal circuit.

FIG. 9 is a diagram showing a conventional connection method of basic cells.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Source region of NMOS transistor 2 ... Drain region of NMOS transistor 3 ... Polysilicon gate 4 ... Contact hole of power supply line 5, 5a ... Power supply line 6b ... Contact hole of output drain terminal 7b ... Output drain terminal 8a ... Input gate terminal 9a ... input gate terminal 10 ... clock signal input terminal 11 ... basic gate of output buffer circuit 11-1, 11-2, 11-3 ... basic gate of input buffer circuit 12-1, 12-2, 12 -3: Internal circuit of tree structure 13: Long signal line for transferring clock signal 14a, 16a, 18a: Contact hole of input gate terminal 14b, 16b, 18b: Contact hole of output drain terminal 15a, 17a: Input gate terminal side 15b, 17b ... output drain Upper metal wiring on terminal side 19, 19a, 19b Top metal wiring 20 Lower contact hole 21 Lower metal wiring 22 Upper contact hole 23 Clock signal transfer path 30 Semiconductor chip 31, 32 Large-scale function cells 33, 34: gate array 35: long signal lines 35-1, 35-2, 35-3, 35-4 ... basic cells 36-1, 36-2, 36- 3: General signal line wiring area

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 27/08 321F F-term (Reference) 5F033 HH07 HH08 HH09 HH11 HH13 HH18 HH19 KK04 MM05 MM08 MM28 UU05 VV17 WW02 XX00 XX05 5F038 AV06 BE07 CA17 CD06 CD08 CD18 EZ08 EZ20 5F048 AA08 AB01 AB02 AB04 AC03 BB05 BF00 BF01 BF02 BF07 BF15 5F064 AA02 AA04 AA06 BB07 BB13 BB15 CC10 CC12 DD25 EE02 EE08 EE23 EE32 EE33 EE34 EE35 EE41 EE54

Claims (7)

[Claims] 1. A plurality of MOSs formed on a semiconductor substrate
A transistor; and at least one of a basic cell and a functional cell including the plurality of MOS transistors, wherein the cell includes n (n is a natural number of 3 or more) metal wiring layers, and the n metal wiring layers Through a contact hole formed in an (n-1) -th interlayer insulating film that separates each other from each other; and an input gate of at least one MOS transistor forming the cell through the contact hole arranged in a direction normal to the main surface of the semiconductor substrate. And an input gate terminal for connecting the lowermost metal wiring and the uppermost metal wiring in the n metal wiring layers connected to each other. 2. A plurality of MOSs formed on a semiconductor substrate
A transistor; and at least one of a basic cell and a functional cell including the plurality of MOS transistors, wherein the cell includes n (n is a natural number of 3 or more) metal wiring layers, and the n metal wiring layers Through a contact hole formed in an (n-1) -th interlayer insulating film for isolating each other, and an output drain of at least one MOS transistor forming the cell through the contact hole arranged in a direction normal to the main surface of the semiconductor substrate. Said n connected to
And an output drain terminal for connecting the lowermost metal wiring and the uppermost metal wiring in the metal wiring layer to each other. 3. The input gate terminal according to claim 1, wherein the cell with the upper wiring terminal is connected to an input gate of at least one MOS transistor forming the cell.
3. A cell with an upper wiring terminal, comprising: the output drain terminal according to claim 2 connected to an output drain of the MOS transistor. 4. The input gate terminal is an input gate terminal of a first cell with an upper wiring terminal, and the output drain terminal is an output drain terminal of a second cell with an upper wiring terminal. The input gate terminal and the output drain terminal are connected to each other by the uppermost metal wiring having the same thickness.
4. The cell with an upper layer wiring terminal according to any one of the above-mentioned items. 5. The cell with upper wiring terminals according to claim 1, wherein the thickness of the uppermost metal wiring is larger than the thickness of the lowermost metal wiring. 6. The metal wiring of the uppermost layer is made of Cu, Al,
The cell with an upper wiring terminal according to any one of claims 1 to 5, wherein the cell is made of a metal having a high electric conductivity mainly composed of Au. 7. The metal wiring of the uppermost layer is made of Cu, Au,
Simple metals such as W, Ti / Au, Ti / Pt / Au, Ti
6. The cell with an upper wiring terminal according to claim 1, wherein the cell is one of a multilayer metal such as / Al and an alloy such as AlSi and AlSiCu and has high electromigration resistance.