JP2002009615A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that selects a low conversion coefficient for a voltage controlled oscillator, which constitutes the PLL circuit, so as to improve the stability of an oscillated frequency thereby reducing jitters in an oscillated signal. SOLUTION: A phase comparator circuit 201 compares the phase of a reference signal Sref with a phase of an oscillation signal SVCO, a charge pump 203 and a low-pass filter 206 generate a control signal VCNT in response to the comparison result, gives the control signal to a channel forming region of a PMOS transistor(TR), which is a component of each inverter of a voltage- controlled oscillator VCO 207 for controlling the oscillated frequency of the VCO, then a conversion coefficient KV of the VCO can be set lower, thereby realizing the stability of the oscillated frequency and reduction in the jitter of the oscillated signal SVCO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL in which the conversion coefficient of a PLL circuit, in particular, a voltage controlled oscillation circuit, is set low, the linearity of control characteristics is improved, and the occurrence of jitter can be suppressed.
It is related to the circuit.

[0002]

2. Description of the Related Art FIG. 5 shows a generally used PLL.
FIG. 3 is a circuit diagram illustrating a configuration example of a circuit. As shown, the PLL circuit includes a phase comparison circuit 101, a charge pump 103, a low-pass filter (LPF: low-pass filter) 104, and a voltage-controlled oscillation circuit (VCO) 105.

A phase comparison circuit 101 compares the phase of an externally input reference signal S _ref with the phase of an oscillation signal S _VCO of the _VCO 105, and according to the phase difference between these signals, an up signal S _UP or a down signal S _UP. Output _DW . The charge pump 103 receives the up signal S from the phase comparison circuit 101.
The level of the output voltage _VCH is controlled by supplying a charge current or a discharge current to a capacitive load circuit connected to the output side according to the _UP or down signal _SDW .

[0004] low-pass filter 104 is connected to the output side of the charge pump 103, it attenuates the high frequency component contained in the output voltage V _CH of the charge pump 103 outputs only the low frequency component V _CNT. Low-pass filter 10
The output signal V _CNT of 4 is supplied to VCO105 as a control voltage. The VCO 105 has an oscillation frequency controlled according to the control voltage _VCNT , and outputs an oscillation signal _SVCO .

As shown in FIG. 5, in the VCO 0105, a ring-shaped oscillation circuit is formed by four stages of inverters connected in series and a NAND gate 106. Each inverter has a power supply voltage V _DD and a ground potential GND.
And two pMOS transistors and one nMOS transistor connected in series. For example, the first-stage inverter includes pMOS transistors MP111 and MP112 and an nMOS transistor MN111 which are connected in series between the power supply voltage V _DD and the ground potential GND. Transistor M
The channel formation regions of the transistor P111 and the transistor MP112 are both connected to the power supply voltage _VDD , and the transistor MN1
Eleven channel forming regions are grounded. The control voltage V _CNT is applied to the gate of the transistor MP111, the gates of the transistors MP112 and MN111 are connected in common, the input terminal of the inverter is formed, and the output terminal of the inverter is connected to the source connection terminal of the transistors MP112 and MN111. Is formed.

The other inverters constituting VCO 105 have substantially the same configuration as the first-stage inverter described above. These inverters have input terminals connected to the output terminal of the preceding inverter, one input terminal of the NAND gate 106 connected to the output terminal of the last inverter, and the input terminal of the first inverter connected to the output terminal of the NAND gate 106. It is connected to the. VCO configured in this way
In 105, when a high-level enable signal ENB is applied to the other input terminal of the NAND gate 106, the NAND gate 106 inverts the input signal and outputs the inverted signal to the output terminal. A ring-shaped oscillation circuit is formed. The oscillation frequency of this oscillation circuit is determined by the delay time of each component inverter. Since the delay time of each inverter is controlled by the control voltage V _CNT applied to the gate of the pMOS transistor constituting each inverter, VC
Oscillation frequency F _out of the O105 is controlled by a control voltage V _CNT.

[0007] The oscillation signal of the VCO 105 is
7, and is supplied to the phase comparison circuit 101 as an oscillation signal _SVCO . Further, the oscillation signal _SVCO is supplied to the outside via the buffer 108.

In the PLL circuit having the above configuration, the reference signal _Sref and VC
The up signal S _UP or the down signal S _DW is output according to the phase difference between the O 105 and the oscillation signal S _VCO . The charge pump 103 outputs a voltage signal S _V corresponding to the up signal S _UP or the down signal S _DW , and a high-frequency component is attenuated through the low-pass filter 104, and the control voltage V includes only a predetermined low-frequency component. _CNT is output. The oscillation frequency of the VCO 105 is controlled according to the control voltage _VCNT .

[0009] By feedback control in the PLL circuit, V
Oscillation signal S _VCO of CO105 is controlled to phase synchronized with the reference signal S _ref. Immediately after the PLL circuit starts up or when the frequency of the reference signal _Sref changes, P
In the LL circuit, the frequency of the oscillation signal S _VCO is
So-called pull-in control is performed so as to follow _ref . After a lapse of a predetermined time, the oscillation signal _SVCO enters a phase-locked state with the reference signal _Sref . Usually, this state is P
It is said that the LL circuit is locked to the reference signal _Sref .

[0010]

By the way, in the above-mentioned conventional PLL circuit, when the PLL circuit reaches the locked state, even if the frequency of the reference signal _Sref is kept constant, it is affected by noise and the like. A so-called jitter occurs in which the oscillation frequency F _{out of the} VCO changes. Hereinafter, the cause of the occurrence of jitter will be described. As shown in FIG. 5, in the VCO 105, the control voltage V _CNT is pMO
Is applied to the gate of the S transistor MP 111, MP 121, MP 131 and MP141, gates of these transistors - by controlling the voltage V _gs between the source, to control the drain current I _d of the transistor. VC
The delay time of the inverters constituting the O105 varies depending on the drain current I _d. That is, the oscillation frequency of the VCO 105 is controlled by the control voltage _VCNT .

The pMOS transistors MP111 and MP1
21, when the MP131 and MP141 are saturated region operation, the current I _d flowing through the respective transistors,
It is obtained by the following equation.

[0012]

(Equation 1)

In the equation (1), V _gs is a transistor gate-source voltage, V _t is a transistor threshold voltage, λ is a channel length modulation coefficient, and V _ds is a transistor drain-source voltage. I have. The coefficient K is given by the following equation.

[0014]

(Equation 2)

[0015]

(Equation 3)

In equations (2) and (3), W is the channel width of the transistor, L is the channel length of the transistor, μ
_Represents carrier mobility, and _Cox represents gate oxide film capacity. The threshold voltage V _t of the transistor is given by the following equation.

[0017]

(Equation 4)

In equation (4), V _bs is the voltage between the substrate (substrate) and the source of the transistor, V _t0 is the threshold voltage when V _bs is 0, and γ and φ _f are constants determined by the process. It is.

From equations (1) to (4), the transistor M
P111, MP 121, when the MP131 and MP141 are saturated region operation, the current I _d flowing through the respective transistors, the gate - it can be seen that changes in proportion to the square of the voltage V _gs between the source.

On the other hand, transistors MP111 and MP12
1, MP131 and MP141 operate in the non-saturation region, the current I
_d is obtained by the following equation.

[0021]

(Equation 5)

By [0022] Equation (5), when operating in the non-saturation region, the current I _d flowing through the transistor whose gate - varies in proportion to a square of the source voltage V _gs.

As described above, the transistor MP11
1, MP 121, MP 131 and the current I _d flowing through the MP141, the gate of each transistor - source voltage, i.e., | V _CNT -V _DD | varies in accordance with an square or the square of the. The delay times of the four-stage inverters constituting the VCO 105 are the transistors MP111 and MP1 respectively.
21, since it is controlled by MP131 and MP141 output current I _d of the oscillation frequency F _out of VCO105 in response to the control voltage V _CNT, varies greatly. That is, VC
O conversion coefficient _{K V (K V = F out} / V CNT) is larger. When the control voltage V _CNT slightly fluctuates due to noise or the like, the oscillation frequency F
_out greatly fluctuates, and the jitter of the output signal of the VCO 105 increases.

The present invention has been made in view of such circumstances, and an object of the present invention is to improve the stability of the oscillation frequency by setting a low conversion coefficient of a voltage-controlled oscillation circuit constituting a PLL circuit. An object of the present invention is to provide a PLL circuit that can reduce the jitter of an oscillation signal.

[0025]

In order to achieve the above object, a PLL circuit according to the present invention comprises: a phase comparison circuit for comparing the phase of a reference signal with an oscillation signal; A charge pump that outputs a charge current or a discharge current to an output terminal, a filter that extracts a predetermined frequency component of an output signal of the charge pump, and an oscillation frequency that corresponds to the control signal using the output signal of the filter as a control signal. And an oscillation circuit that oscillates at the same time and outputs the oscillation signal. The oscillation circuit includes an inverter including a transistor to which the control signal is applied to a channel formation region.

In the present invention, preferably, the inverter has a first conductivity type transistor and a second conductivity type transistor connected between the first power supply voltage and the second power supply voltage. The control signal is applied to a channel formation region of the first conductivity type transistor.

In the present invention, preferably, the inverter has a first conductivity type transistor and a second conductivity type transistor connected between the first power supply voltage and the second power supply voltage. The control signal is applied to a channel formation region of the second conductivity type transistor.

In the present invention, preferably, the inverter includes a first transistor of a first conductivity type, a second transistor connected in series between a first power supply voltage and a second power supply voltage. The transistor has a first conductivity type transistor and a second conductivity type transistor, and the control signal is applied to a channel formation region of the first first conductivity type transistor.

Further, in the present invention, preferably, a correction signal for reducing the fluctuation amount of the oscillation frequency of the oscillation circuit is generated according to the operating condition, and the correction signal is applied to the gate of the first first conductivity type transistor. And a correction circuit for performing the correction.

In the present invention, preferably, the inverter includes a first conductivity type transistor and a first second conductivity type transistor connected in series between a first power supply voltage and a second power supply voltage. A transistor having a transistor and a second second conductivity type transistor, wherein the control signal is applied to a channel formation region of the second second conductivity type transistor.

Further, in the present invention, preferably, a correction signal for reducing the fluctuation amount of the oscillation frequency of the oscillation circuit is generated according to the operating condition, and the correction signal is applied to the gate of the second second conductivity type transistor. And a correction circuit for performing the correction.

Further, the present invention preferably has an initial voltage generating circuit for generating the control signal having a predetermined level in an initial state after the start of operation.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a PLL circuit according to the present invention. As illustrated, the PLL circuit of the present embodiment includes a phase comparison circuit 201, a charge pump 203, an initial voltage generation circuit 204, a variation correction circuit 205, a low-pass filter (LPF: low-pass filter) 206, and a voltage-controlled oscillation circuit ( (VCO) 207.

The phase comparison circuit 201 compares the phases of the oscillation signal S _VCO of the reference signal S _ref and VCO207 inputted from the outside, in accordance with the phase difference of these signals, and outputs a phase error signal S _P . The charge pump 203 in response to the phase error signal S _P output from the phase comparator circuit 201, with respect to the capacitive load circuit connected to the output side, by supplying the charge current or discharge current, the output voltage V _CH Control the level of In the PLL circuit of the present embodiment, the phase comparison circuit 201 and the charge pump 203
Operate at different power supply voltages. For example, the phase comparator circuit 201 operates with a power supply voltage V _DDL, the charge pump 203 is operated at a higher than V _DDL supply voltage V _DDH. For example, the power supply voltage V _DDL is 1.8 V and the power supply voltage V
_DDH is set to 3.3V, respectively.

For this reason, as shown in FIG.
The 03, level shift circuit 202 is provided, pMOS transistors M in response to the phase error signal S _P which is output from the phase comparator circuit 201, constitute a charge Ponpo
An up signal S _UP and a down signal S _DW to be applied to P251 and the gate of the nMOS transistor MN251 are generated.
For example, in accordance with the phase error signal S _P, a low level, for example, when the up signal S _UP and a down signal S _DW of the ground potential GND level is generated, the transistor MP251 is turned on, the transistor MN251 is cut off, the charge A charge current is output from the pump 203. on the other hand,
In accordance with the phase error signal S _P, the high level, for example, when the power supply voltage V _DDH level of the up signal S _UP and a down signal S _DW is generated, the transistor MP251 is cut off, the transistors MN251 is conductive, the charge pump The discharge is drawn into the output terminal of the circuit 203. Since the capacitive load is connected to the output terminal of the charge pump 203, the output voltage V _CH of the charge pump 203 changes according to the charge current and the discharge current output from the charge pump 203.

The low-pass filter 206 is connected to the output side of the charge pump 203, attenuates high-frequency components contained in the output voltage V _CH of the charge pump 203, and outputs only low-frequency components V _CNT . Low-pass filter 20
The output signal V _CNT 6 is supplied to VCO207 as a control voltage. VCO207 the oscillation frequency according to the control voltage V _CNT is controlled, and outputs an oscillation signal S _VCO.

The initial voltage generating circuit 204 generates a control voltage _VCNT when the PLL circuit is in the initial state,
7 In the initial state, the charge pump 20
3 cannot output a sufficient level of voltage _VCH . For this reason, the control voltage V _CNT output from the low-pass filter 206 does not reach a level necessary for the VCO 207 to oscillate normally. For this reason, in the initial stage after the start of the circuit, the control voltage _VCNT of a predetermined level is generated by the initial voltage generation circuit 204 and supplied to the VCO 207, whereby the VCO 207 can be started quickly, and the rising of the PLL circuit can be started. You can save time.

The VCO 207 is constituted by an odd number of stages of inverting circuits connected in a ring. As shown, in the present embodiment, the VCO 207 includes a four-stage inverter and a NAND gate 208 connected in series.
It is constituted by. PMO inverter, which are connected between the respective power supply voltage V _DDL ground potential GND
It is composed of an S transistor and an nMOS transistor. For example, the first-stage inverter has a power supply voltage V
PMOS transistor MP212 and nMOS transistor MN211 connected between _DDL and ground potential GND
It is constituted by. The connection point between the gates of these transistors forms the input terminal of the inverter, and the connection point between the drains forms the output terminal of the inverter.
One input terminal of the NAND gate 208 is connected to the output terminal of the fourth-stage inverter, and its output terminal is connected to the input terminal of the first-stage inverter. Note that NAND
An enable signal ENB is input to the other input terminal of the gate 208.
Is input, when the enable signal ENB is at a high level, the NAND gate 208 operates as an inverter, and the VCO 207 is in an operating state. Conversely, when the enable signal ENB is at a low level, the NAND gate 2
08 is held at a high level, and the VCO 207
Does not oscillate.

Transistor MP constituting VCO 207
The control voltage V _CNT output by the low-pass filter 206 is input to the channel forming regions of 212, MP222, MP232, and MP242. That is, the control voltage V
_CNT is a transistor MP212, MP222, MP23
2 and MP242 are supplied as substrate bias voltages.
Therefore, the threshold voltage of each transistor is controlled according to the level of the control voltage V _CNT , and the delay time of each inverter is controlled accordingly.
The oscillation frequency of 207 is controlled according to the control voltage _VCNT .

Hereinafter, the operation of the PLL circuit of this embodiment will be described. After the circuit is started, a control voltage V _CNT of a predetermined level is generated by the initial voltage generation circuit 204 and supplied to the VCO 207. At this time, since the enable signal ENB is held at a high level, V
CO207 oscillates at a frequency set by the control voltage V _CNT, the oscillation signal is amplified by the buffer 209 is shaped and outputted to the phase comparator 201 as the oscillation signal S _VCO. The oscillation signal S _VCO is output as an oscillation signal S _out via the buffer 210.

In the phase comparison circuit 201, the reference signal S
_ref and the phase of the oscillation signal S _VCO are compared, the phase difference signal S _P is the charge pump 2 according to the phase difference between these signals
03 is output. In the charge pump 203, by the level shift circuit 202, the up signal S _UP and a down signal S _DW is generated according to the phase difference signal S _P, the charge current or discharge current is generated in accordance with these of, the charge pump 203 The output voltage V _CH is controlled.

The low-pass filter 206 removes high-frequency components contained in the output voltage V _CH of the charge pump 203, and controls the control voltage V including only signals in the low-frequency region.
_CNT is output to VCO 207. In the VCO 207, transistors MP212 and M
The control voltage _VCNT is input to the channel formation regions of P222, MP232, and MP242. In response, VC
The delay time of the inverter constituting O207 is controlled by the control voltage V
_Since the control is performed according to the _CNT , the oscillation frequency of the VCO 207 is controlled according to the control voltage _VCNT .

In the above-described PLL circuit, the VCO 20
By feeding back the 7 oscillating signal V _VCO of the phase comparator circuit 201, the oscillation signal V _VCO is the reference signal S
Control is performed so as to synchronize with _ref . As a result, the oscillation signal V _VCO is maintained at the same frequency as the reference signal _Sref .

In the VCO 207, the control voltage V _CNT is used as a back bias (substrate bias) voltage as the transistors MP212, MP222, MP232 and MP24.
Therefore, the threshold voltages of these transistors are controlled according to the control voltage V _CNT , and the current flowing through the transistors is controlled. As a result, the oscillation frequency of VCO 207 is controlled.

According to the above equations (1) and (4), the transistors MP212, MP222, MP232 and M
If P242 is operated in the saturation region, the drain current I _d of the transistor changes in proportion to a square of the back bias voltage V _bs. On the other hand, according to equations (4) and (5),
Transistors MP212, MP222, if MP232 and MP242 are operated in unsaturated, Oh drain current I _d of the transistor, the back bias voltage V _bs 1 /
It changes in proportion to the square. That is, since the oscillation frequency of the VCO 207 changes in proportion to the first or half power of the back bias voltage V _bs , the oscillation frequency F _out is lower than that of the VCO 105 of the conventional PLL circuit shown in FIG. The voltage _Vbs changes in proportion to the first power or 1/2 power, the conversion coefficient K _V (F _out / V _CNT ) of the VCO becomes smaller than that of the conventional VCO, and the stability of the oscillation frequency of the VCO improves.

When the control voltage V _CNT for controlling the oscillation frequency of the VCO 207 becomes lower than the power supply voltage V _{DDL of the} VCO 207, the transistors MP212, MP222, MP23
The parasitic diodes between the substrate and the source and between the substrate and the drain of the MP 242 are biased in the forward direction, and the electric charge accumulated in the low-pass filter 206 is discharged, so that the output of the charge pump 203 can be integrated normally. Disappears. Therefore, the control voltage V _{CNT is changed} to V
It is necessary to set the power supply voltage V _{DDL of the} CO 207 higher than the power supply voltage V _{DDL of} the charge pump 203.
_DDH is set higher than power supply voltage V _{DDL of} VCO 207.

Since the conversion coefficient K _{V of the} VCO 207 is set low, the lock range of the PLL circuit becomes narrower than that of the conventional PLL circuit. In the PLL circuit of the present embodiment, the lock range is the control voltage V _{CNT and} the power supply voltage V
_DDL is set to a frequency equal to or higher than _DDL.
The control voltage V set to be equal to or higher than the power supply voltage V _{DDL of} O207
_{When the CNT} is generated and the VCO 207 oscillates and the feedback of the PLL circuit functions normally, the operation of the initial voltage generation circuit 204 stops, and the control voltage V _CNT is controlled by the phase comparison circuit 201, the charge pump 203 and the low-pass filter 206. Controlled.

[0048] As described above, according to the present embodiment, the PLL circuit, the phase comparison circuit 201 outputs the phase difference signal S _P corresponding to the phase difference between the oscillation signal S _VCO of the reference signal S _ref and VCO207 In response, the charge pump 203 and the low-pass filter 206 generate a control voltage V _CNT according to the phase difference, and the transistors MP 212, MP 222, and MP 23 forming the VCO 207 are generated.
2 and the channel formation region of MP242, and VCO
And controls the oscillation frequency of 207, can be set lower conversion factor K _V of VCO207, it can improve the stability of the oscillation frequency of VCO207, can reduce the jitter of the oscillation signal S _VCO.

In the VCO 207 shown in FIG. 1, a control voltage V _CNT set higher than the power supply voltage V _DDL is applied to a channel forming region of pMOS transistors constituting an inverter to control the currents of these transistors. Controls the oscillation frequency of the VCO 207, but the present embodiment is not limited to this. For example,
Using a charge pump and a low-pass filter, a control voltage at a level lower than the ground potential GND, that is, a negative control voltage is generated and applied to the channel forming region of the nMOS transistor forming the inverter, thereby controlling the oscillation frequency of the VCO 207. Thus, the same effect can be obtained.

Second Embodiment FIG. 2 is a circuit diagram showing a second embodiment of the PLL circuit according to the present invention. As shown in FIG.
The circuit is different from the PLL circuit of the first embodiment shown in FIG.
In O207a, the configuration of the inverter is changed. The other parts, for example, the phase comparison circuit 201, the charge pump 203, and the low-pass filter 206 have substantially the same configuration as the respective partial circuits of the first embodiment.
In FIG. 2, the same components are denoted by the same reference numerals. Hereinafter, the configuration and operation of the PLL circuit of the present embodiment will be described focusing on the differences between the PLL circuits of the present embodiment and the first embodiment.

In the PLL circuit of this embodiment, the VCO
PMOS transistor MP212 constituting the 207a of the inverter, MP222, between the MP232 and MP242 source side and the power supply voltage V _DDL of, pMOS, respectively
The transistors MP211, MP221, MP231, and MP241 are connected. Transistor MP21
1, the control voltage V _CNT generated by the initial voltage generation circuit 204 or the low-pass filter 206 is applied to the channel forming regions of MP221, MP231, and MP241, and the correction voltage V _C generated by the variation correction circuit 205 is applied to the gate. Is done. Note that the transistors MP212, MP222, MP23 constituting the inverter
2 and the power supply voltage V _{DDL of the} VCO 207 is applied to the channel formation region of the MP 242.

The variation correction circuit 205 adjusts the correction voltage V _C according to the variation in process, operating temperature, and power supply voltage.
Is generated and supplied to the VCO 207. As mentioned above,
The correction voltage V _C is transistor MP211, MP22
1, MP231 and so is applied to the gate of MP241, according to the correction voltage V _C, the gate of each transistor - the source voltage V _gs is controlled, since the current flowing through the transistor I _d is controlled, as a result , the oscillation frequency F _out of the PLL circuit is controlled according to the corrected voltage V _C. That is, in the variation correction circuit 205, the PL,
By adjusting the level of the correction voltage V _{C in} a direction to suppress the change in the oscillation frequency F _out of the L circuit, it is possible to suppress the change in the oscillation frequency due to the change in the operating condition and the operating environment of the PLL circuit. , The stability of the oscillation frequency F _out of the PLL circuit can be improved, and the lock range can be maintained within a certain range.

As described above, according to the present embodiment, the reference signal _Sref and the VC are controlled by the phase comparison circuit 201, the charge pump 203, and the low-pass filter 206.
Transistors MP211, MP221, and MP231 which generate a control voltage V _CNT corresponding to the phase difference from the oscillation signal S _{VCO of} O207a and supply an operation current to the inverter of VCO 207a as a back bias voltage of the transistor.
And the output current of these transistors by controlling the output current of these transistors,
7a can be controlled to be low, and the stability of the oscillation frequency can be improved. Further, the correction voltage V _C generated by the variation correction circuit 205 is applied to the transistors MP211 and MP211.
By applying the voltage to the gates of MP221, MP231, and MP241, it is possible to suppress the effects of variations in process, operating temperature, and power supply voltage, stabilize the oscillation frequency of the PLL circuit, and maintain the lock range within a desired range. it can.

In the second embodiment described above, VC
O207a has an oscillation frequency of pM
PMOS connected to the source side of the OS transistor
The control voltage V applied to the channel formation regions of the transistors MP211, MP221, MP231, and MP241
_Although controlled by the _CNT , the present embodiment is not limited to this.
Instead of 211, MP221, MP231 and MP241, an nMOS transistor MN forming an inverter
By connecting nMOS transistors between the source sides of the transistors 211, MN221, MN231, and MN241 and the ground potential GND, and applying a negative control voltage lower than the ground potential GND to the channel formation region of these nMOS transistors, the VCO It is also possible to control the oscillation frequency of.

Further, in the above-described embodiment of the present invention,
Although a ring oscillation circuit configured by an inverter was used as the VCO, the present invention is not limited to a ring oscillation circuit including an inverter. For example, a differential ring oscillation circuit, a multivibrator oscillation circuit, and the like may be used. The present invention can be applied to an oscillation circuit, and the same effect as the above-described embodiment of the present invention can be obtained.

FIGS. 3 and 4 are graphs comparing the VCO control characteristics of the PLL circuit of the present embodiment and the conventional PLL circuit shown in FIG. As shown in FIG.
VCO of L circuit, since the converted form K _V is controlled to be low, relative to the change of the control voltage V _CNT, the amount of change in the oscillation frequency is reduced. Further, it can be seen that the linearity of the control characteristics is improved as compared with the VCO of the conventional PLL circuit.

[0057]

As described above, according to the PLL circuit of the present invention, the control voltage generated by the phase comparator, the charge pump and the low-pass filter is used as the back bias voltage to form the channel of the MOS transistor constituting the VCO. is applied to the region, by controlling the oscillation frequency of the VCO, it can be controlled lower transform coefficient K _V of VCO, as well as improving the linearity of the control characteristic of the VCO, thereby improving the stability of the oscillation frequency. Further, even if the control voltage changes due to the influence of noise or the like, there is an advantage that the fluctuation amount of the oscillation frequency of the VCO can be suppressed low, and the jitter of the oscillation signal can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a PLL circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the PLL circuit according to the present invention.

FIG. 3 is a graph showing an example of a control characteristic of a VCO constituting a PLL circuit of the present invention, as compared with a conventional PLL circuit.

FIG. 4 is a graph showing another example of the control characteristics of the VCO constituting the PLL circuit of the present invention, as compared with the conventional PLL circuit.

FIG. 5 is a circuit diagram illustrating a configuration example of a conventional PLL circuit.

[Description of Signs] 101: phase comparison circuit, 103: charge pump, 10
4 Low-pass filter, 105 VCO, 201 Phase comparison circuit, 202 Level shift circuit, 203 Charge pump, 204 Initial voltage generation circuit, 205 Variation correction circuit, 206 Low-pass filter, 207, 20
7a: VCO, V _DD , V _DDL , V _DDH ... power supply voltage, GN
D: ground potential.

Claims (12)

[Claims] A phase comparison circuit for comparing a phase of a reference signal with an oscillation signal; a charge pump for outputting a charge current or a discharge current to an output terminal according to a comparison result of the phase comparison circuit; A filter that extracts a predetermined frequency component of the output signal of the above, and an oscillation circuit that oscillates at an oscillation frequency according to the control signal using the output signal of the filter as a control signal and outputs the oscillation signal, The oscillation circuit is a PLL circuit including an inverter including a transistor to which the control signal is applied to a channel formation region. 2. The inverter according to claim 1, wherein said inverter has a first conductivity type transistor and a second conductivity type transistor connected between a first power supply voltage and a second power supply voltage. 2. The PLL circuit according to claim 1, wherein the control signal is applied to a channel formation region. 3. The PLL circuit according to claim 2, wherein said control signal is held higher than said first power supply voltage. 4. An inverter having a first conductivity type transistor and a second conductivity type transistor connected between a first power supply voltage and a second power supply voltage. 2. The PLL circuit according to claim 1, wherein the control signal is applied to a channel formation region. 5. The PLL circuit according to claim 4, wherein said control signal is kept lower than said second power supply voltage. 6. The inverter according to claim 1, wherein the first and second conductive transistors are connected in series between a first power supply voltage and a second power supply voltage. 2. The PLL circuit according to claim 1, further comprising a type transistor, wherein the control signal is applied to a channel forming region of the first first conductivity type transistor. 3. 7. A method for generating a correction signal for reducing a fluctuation amount of an oscillation frequency of said oscillation circuit according to an operation condition,
7. The PLL circuit according to claim 6, further comprising a correction circuit for applying a voltage to the gate of the first conductivity type transistor. 8. The PLL circuit according to claim 6, wherein said control signal is kept higher than said first power supply voltage. 9. The transistor according to claim 1, wherein the first conductive type transistor, the first second conductive type transistor, and the second second conductive type transistor are connected in series between a first power supply voltage and a second power supply voltage. 2. The PLL circuit according to claim 1, further comprising a type transistor, wherein the control signal is applied to a channel formation region of the second second conductivity type transistor. 3. 10. A correction circuit for generating a correction signal for reducing the fluctuation amount of the oscillation frequency of the oscillation circuit in accordance with an operation condition and applying the correction signal to a gate of the second second conductivity type transistor. The PLL circuit as described in the above. 11. The PLL circuit according to claim 9, wherein said control signal is kept lower than said second power supply voltage. 12. The PLL circuit according to claim 1, further comprising an initial voltage generating circuit for generating said control signal having a predetermined level in an initial state after the start of operation.