JP2002009259A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device capable of securing a desired capacitor capacitance while reducing a global step without complicating a manufacturing process, and a method for manufacturing the same. SOLUTION: An insulating film 70 is formed on a substrate having a memory cell region and a peripheral circuit region, and an opening 74 reaching the substrate is formed in the insulating film 70 in the memory cell region.
An adhesion layer 78 is formed on the inner wall and the bottom of the substrate, a storage electrode 80 is formed in the opening 74 in which the adhesion layer 78 is formed, and the adhesion layer 78 and the insulating film are formed so that the insulating film 70 in the peripheral circuit region remains. The insulating film 70 in the memory cell region is selectively removed by etching the insulating film 70 in the horizontal direction with respect to the surface of the substrate from the interface with the insulating film 70.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a semiconductor device having a DRAM type memory element and a method of manufacturing the same.

[0002]

2. Description of the Related Art A DRAM is a semiconductor memory device that can be constituted by one transistor and one capacitor, and various structures and manufacturing methods for manufacturing a high-density and highly integrated semiconductor memory device have been studied. . In particular, since the structure of a capacitor in a DRAM greatly affects high integration, it is important how to secure a desired storage capacity without hindering high integration of the device.

In order to achieve high integration, it is essential to reduce the area of a memory cell, and it is necessary to reduce the area in which a capacitor is formed. Therefore, it has been proposed to increase the surface area of the capacitor in the height direction by adopting a columnar or cylindrical capacitor structure and to secure a desired storage capacity without increasing the area of the region where the capacitor is formed. . On the other hand, when the height of the capacitor increases, a step between the peripheral circuit region and the memory cell region, that is, a so-called global step becomes prominent, so that fine lithography becomes difficult due to the problem of the depth of focus, or the reliability of the wiring is reduced. There is a problem such as that is damaged.

In such a background, there has been proposed a semiconductor device capable of reducing a global step while adopting a columnar or cylindrical capacitor structure and a method of manufacturing the same. Hereinafter, a conventional method of manufacturing a semiconductor device for reducing a global step will be described with reference to FIGS.

First, an ordinary M is placed on a silicon substrate 100.
A memory cell transistor having a gate electrode 102 and source / drain diffusion layers 104 and 106 and a transistor for a peripheral circuit having a gate electrode 108 and source / drain diffusion layers 110 are formed in the same manner as the method for manufacturing the OS transistor.

Next, a bit line 114 electrically connected to the source / drain diffusion layer 104 via the plug 112 and a source / drain diffusion layer are formed on the interlayer insulating film 118 covering the memory cell transistor and the transistor for the peripheral circuit. A wiring layer 116 electrically connected to 110 is formed. Since the bit line 114 does not appear in the illustrated cross section, the bit line 114 is shown by a dotted line.

Next, the bit line 114 and the wiring layer 116
An interlayer insulating film 120 is formed on the interlayer insulating film 118 on which
To form

Next, a plug 124 electrically connected to the source / drain diffusion layer 106 via the plug 122 is buried in the interlayer insulating films 120 and 118 (FIG. 30).
(A)).

Next, an etching stopper film 126 made of, for example, a silicon nitride film, an interlayer insulating film 128 made of, for example, a silicon oxide film, and an amorphous silicon Hard mask 130 made of a film
Is formed (FIG. 30B).

Next, the hard mask 130 and the interlayer insulating film 1 are formed by ordinary lithography and etching techniques.
28, pattern the etching stopper film 126,
An opening 132 reaching the plug 124 is formed (FIG. 31).
(A)).

Next, the whole surface is formed by, for example, a CVD method.
For example, Ru (ruthenium) film or SRO (SrRuO ₃ )
A conductive film 134 made of a film or the like and an inner protective film 136 made of, for example, a silicon oxide film or a resist are deposited (FIG. 31B).

Next, the conductive film 1 is removed by, eg, CMP or dry etching until the interlayer insulating film 128 is exposed.
34, the surfaces of the inner protective film 136 and the hard mask 130 are uniformly retreated. Thus, a cylindrical storage electrode 138 made of the conductive film 134 is formed in the opening 132 (FIG. 32A).

Next, a photoresist film 140 which covers the peripheral circuit region and exposes the memory cell region is formed by a usual lithography technique.

Next, using the photoresist film 140 as a mask and the etching stopper film 126 as a stopper,
The interlayer insulating film 128 and the inner protective film 136 are isotropically etched to selectively remove the interlayer insulating film 128 and the inner protective film 136 in the memory cell region. Thereby, the inner surface and the outer surface of the storage electrode 138 are exposed (FIG. 32).
(B)).

Next, on the entire surface, for example, by a CVD method,
For example, a dielectric film made of, for example, Ta ₂ O ₅ or a BST film is deposited, and a capacitor dielectric film 142 made of these dielectric films and covering the storage electrode 138 is formed.

Next, on the entire surface, for example, by a CVD method,
For example, a conductive film made of a Ru film or an SRO film is deposited and patterned, and a capacitor dielectric film 1 made of this conductive film is formed.
Plate electrode 144 covering storage electrode 138 via 42
Is formed (FIG. 33A).

Thus, a capacitor having the storage electrode 138, the capacitor dielectric film 142, and the plate electrode 144 and electrically connected to the source / drain diffusion layer 106 of the memory cell transistor is formed.

Next, on the entire surface, for example, by a CVD method,
For example, a silicon oxide film is deposited, and an interlayer insulating film 146 made of the silicon oxide film is formed.

Next, a wiring layer 148 connected to the wiring layer 116 is formed as needed (FIG. 33B).

Thus, a DRAM in which a memory cell is constituted by one transistor and one capacitor has been manufactured.

As described above, in the method of manufacturing the semiconductor device shown in FIGS. 30 to 33, the storage electrode 138 having almost the same height as the interlayer insulating film 128 is formed by utilizing the opening 132 formed in the interlayer insulating film 128. Is formed, and the interlayer insulating film 128 in the peripheral circuit region is left as it is, so that global steps between the memory cell region and the peripheral circuit region can be greatly reduced. Therefore, even when a wiring layer is formed on the interlayer insulating film 146, fine lithography is easy and the reliability of the wiring can be improved.

[0022]

However, in the above-described conventional method for manufacturing a semiconductor device, a photoresist film 140 covering the peripheral circuit region is formed in the process of selectively removing the interlayer insulating film 128 in the memory cell region. Lithography process is required for
As a result, an increase in manufacturing costs cannot be avoided.

An object of the present invention is to provide a semiconductor device capable of securing a desired capacitor capacity while reducing a global step without complicating a manufacturing process, and a method of manufacturing the same.

[0024]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a conductive film is deposited in an opening formed in an interlayer insulating film and a storage electrode is formed by the conductive film. After formation, the main feature is to selectively remove the interlayer insulating film in the memory cell region by etching the interlayer insulating film horizontally from the interface between the storage electrode and the interlayer insulating film with respect to the surface of the substrate. I have.

Hereinafter, the principle of the present invention will be described with reference to FIG. 1 by taking as an example a case where a storage electrode 80 electrically connected to the plug 62 is formed on a base structure in which the plug 62 is embedded in the interlayer insulating film 58. It will be described using FIG.

First, an etching stopper film 68 and an interlayer insulating film 70 are formed on the interlayer insulating film 58 in which the plug 62 is embedded.

Next, an opening 74 reaching the etching stopper film 68 is formed in the interlayer insulating film 70 in a region where the storage electrode 80 is to be formed (FIG. 1A).

Next, a selective removal film 76 is formed on the side wall of the opening 74 (FIG. 1B). The selective removal film 7
6 is made of a material that can be selectively removed from the interlayer insulating film 70, the etching stopper film 68, the adhesion layer 78 formed later, and the storage electrode 80.

Next, an adhesion layer 78 and a storage electrode 80 are formed along the inner wall and bottom of the opening 74. Thus,
A cylindrical storage electrode 80 is formed (FIG. 1C).
Note that the storage electrode 80 may be formed so as to bury the inside of the opening 74, and may be a columnar storage electrode 80.

Next, the selective removal film 76 is replaced with the interlayer insulating film 7.
0, the etching stopper film 68, the adhesion layer 78, and the storage electrode 80 are selectively removed to form a gap 84 between the adhesion layer 78 and the interlayer insulating film 70 (FIG. 1D).

Next, the interlayer insulating film 70 is wet-etched using the etching stopper film 68 as a stopper.
Is etched.

At this time, the etching solution permeates into the gap 84, and the interlayer insulating film 70 also extends in the horizontal direction with respect to the substrate surface.
Etching proceeds. Further, the interlayer insulating film 70 formed in the memory cell region exists in a region much smaller than the peripheral circuit region. Therefore, the interlayer insulating film 70 in the memory cell region can be selectively removed while suppressing a decrease in the thickness of the interlayer insulating film 70 in the peripheral circuit region.

Therefore, according to the present invention, prior to the etching of the interlayer insulating film 70, the photoresist film covering the peripheral circuit region is formed by forming the gap 84 in the side wall portion of the interlayer insulating film 70. In addition, the interlayer insulating film 70 in the memory cell region can be selectively removed.

The adhesion layer 7 made of a material having excellent adhesion to the interlayer insulating film 58 and the etching stopper film 68.
When the storage electrode 80 is provided in contact with the storage electrode 80, even when the storage electrode 80 has poor adhesion to the interlayer insulating film 58 and the etching stopper film 68, the etching solution is used for wet etching the interlayer insulating film 70. Can be prevented from penetrating into a layer below the etching stopper film 68 and damaging the memory cell transistor and the like.

Further, since the interlayer insulating film 70 in the memory cell region is removed in this manner, the semiconductor device according to the present invention has a configuration in which the side wall of the interlayer insulating film 70 in the peripheral circuit region is It has the feature of including a portion reflecting the outer peripheral shape.

Instead of forming the selective removal film 76, a film having low adhesion to the interlayer insulating film 70 (low adhesion layer) may be formed. When the low adhesion layer is formed instead of the selective removal film 76, the etching solution permeates between the interlayer insulation film 70 and the low adhesion layer without forming the gap 84 in the side wall portion of the interlayer insulation film 70. The same effect as described above can be obtained. Further, on the side wall portion of the interlayer insulating film 70,
Perform a predetermined surface treatment so that the etchant soaks,
A low adhesion layer may be formed on the side wall of the interlayer insulating film 70.

As the selective removal film 76, an interlayer insulating film 70
Is a silicon oxide film, for example, an amorphous silicon film, a polycrystalline silicon film, an Al ₂ O ₃ (alumina) film,
Al (aluminum) film, Al / Cu film, Ti (titanium) film, W (tungsten) film, BPSG (Boro-Phosp)
ho-Silicate Glass) film, Cu (copper) film, C (carbon)
A film, an organic film, a silicon nitride film, a deposition film for forming the opening 74, or the like can be used.

In the selective etching of the selective removal film 76, for example, an aqueous solution containing diluted hydrofluoric acid and nitric acid is used in the case of a polycrystalline silicon film, boiled sulfuric acid is used in the case of an Al ₂ O ₃ film or a W film. In the case of a film, an Al / Cu film or a Ti film, for example, hydrochloric acid is used. In the case of a C film, CO ₂ heat treatment or O ₂ plasma treatment at 400 ° C. is used. In the case of a silicon nitride film, for example, boiling phosphoric acid can be used.

As the low adhesion layer, for example, a Ru (ruthenium) film, a W (tungsten) film, or the like can be used.

As a method of forming a low-adhesion layer by performing a surface modification treatment on a side wall portion of an interlayer insulating film, for example,
A treatment in which the surface is exposed to a gas atmosphere of 400 to 500 ° C. containing phosphorus or boron, a treatment in which an organic substance is attached by dipping in an alcohol solution, a fluorine treatment, or the like can be applied.

The storage electrode 80 may also serve as the plug 62 or may be supported by a structure for preventing the interlayer insulating film 70 from peeling off during etching.

That is, an object of the present invention is to provide a substrate including a first region and a second region in contact with the first region, a substrate formed on the substrate, and a connection hole formed in the first region. A first insulating film, an adhesion layer formed on the substrate in at least the connection hole, a storage electrode formed on the adhesion layer, and protruding above the first insulation film; A dielectric film formed thereon, a plate electrode covering the storage electrode with the dielectric film interposed therebetween, and a storage electrode formed on the first insulating film in the second region and having a side wall shape of the storage electrode. And a second insulating film including a portion reflecting the outer peripheral shape of the side wall of the semiconductor device.

Further, the object is to provide a first region and the first region.
Forming a first insulating film on a substrate including a second region in contact with the region, and forming an opening reaching the substrate in the first insulating film in the first region. Forming an adhesion layer on the inner wall and bottom of the opening; forming a storage electrode in the opening where the adhesion layer is formed; and forming the first insulating film in the second region. Etching the first insulating film in a horizontal direction with respect to the surface of the substrate from an interface between the adhesion layer and the first insulating film so as to remain; and forming a dielectric film covering the storage electrode. The method is also achieved by a method of manufacturing a semiconductor device, comprising a step of forming and a step of forming a plate electrode that covers the storage electrode via the dielectric film.

[0044]

[First Embodiment] A semiconductor device according to a first embodiment of the present invention and a method for fabricating the same will be described with reference to FIGS.

FIG. 2 is a sectional view and a plan view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 3 to 9 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. In addition, FIG.
Is a schematic cross-sectional view of the semiconductor device according to the present embodiment, and the right side of the drawing shows a cross section of the peripheral circuit region and the left side of the drawing shows a cross section of the memory cell region. FIG. 2 (b)
2A is a plan view of the memory cell region of the semiconductor device according to the present embodiment. FIG. 2A is a cross-sectional view of the memory cell region taken along the line AA ′ of FIG. Is represented.

An element isolation film 12 for defining an element region is formed on a silicon substrate 10. A gate electrode 20 and source / drain diffusion layers 26, 2
8 and a gate electrode 2
2 and a transistor for a peripheral circuit having a source / drain diffusion layer 30. The gate electrode 20
As shown in FIG. 2B, it also functions as a conductive film also serving as a word line. Interlayer insulating films 32 and 46 are formed on the silicon substrate 10 on which the memory cell transistors and the transistors for peripheral circuits are formed. On the interlayer insulating film 46, the source / drain diffusion layer 26 is
Are formed, and a wiring layer 56 connected to the source / drain diffusion layer 30 is formed. As shown in FIG. 2B, a plurality of bit lines 54 are formed extending in a direction intersecting with the word lines. An interlayer insulating film 58 is formed on the interlayer insulating film 46 on which the bit lines 54 and the wiring layers 56 are formed. On the interlayer insulating film 58,
A cylindrical storage electrode 80 connected to the source / drain diffusion layer 28 via the adhesion layer 78, the plug 62 and the plug 42 is formed. A plate electrode 88 is formed on the storage electrode 80 via a capacitor dielectric film 86. On the interlayer insulating film 58 in the peripheral circuit region, an etching stopper film 64, an interlayer insulating film 66, an etching stopper film 68, interlayer insulating films 70 and 90, and a plug 92 connected to the wiring layer 56 are formed.

Thus, a DRAM having a memory cell composed of one transistor and one capacitor is constructed.

As shown in FIG. 2, in the semiconductor device according to the present embodiment, the height of the storage electrode 80 is substantially equal to the height of the interlayer insulating film 70, and the global level between the memory cell region and the peripheral circuit region is increased. The step is reduced. Therefore, even when a wiring layer is formed on the interlayer insulating film 90, fine lithography is easy and the reliability of the wiring can be improved.

The structural feature of the semiconductor device shown in FIG. 2 is that the shape of the side wall of the interlayer insulating film 70 in the peripheral circuit region is
There is also a point including a portion reflecting the outer peripheral shape of the side wall of the storage electrode 80. This feature is attributed to the method of manufacturing a semiconductor device according to the present invention, and will be described later in detail.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3 and 5 to 9, the right side of each drawing shows a process sectional view of the peripheral circuit region, and the left side of each drawing is AA ′ in FIG. 2B.
4 shows a process cross-sectional view along a line cross section. FIG.
2B is a process sectional view taken along the line BB 'in FIG. 2B.

First, an element isolation film 12 is formed on the main surface of the semiconductor substrate 10 by, for example, STI (Shallow Trench Isolation).

Next, gate insulating films 14 and 16 made of a silicon oxide film are formed on the plurality of device regions defined by the device isolation film 12 by, for example, a thermal oxidation method. The gate insulating film 14 is a gate insulating film of a memory cell transistor, and the gate insulating film 16 is a gate insulating film of a transistor for a peripheral circuit.

Next, the entire surface is formed by, for example, a CVD method.
For example, after a polycrystalline silicon film and a silicon nitride film are sequentially deposited, the laminated film is patterned to form gate electrodes 20 and 22 made of a polycrystalline silicon film whose upper surface is covered with the silicon nitride film 18. Here, the gate electrode 2
0 is the gate electrode of the memory cell transistor, and the gate electrode 22 is the gate electrode of the peripheral circuit transistor. Note that the gate electrodes 20 and 22 are not limited to the polycrystalline silicon film, but may employ a polycide structure, a polymetal structure, a metal film, or the like.

Next, ion implantation is performed using the gate electrodes 20 and 22 as masks to form source / drain diffusion layers 26 and 28 in the silicon substrate 10 on both sides of the gate electrode 20. L in
A DD region or an extension region is formed.

Next, the entire surface is formed, for example, by the CVD method.
For example, etch back after depositing a silicon nitride film,
On the side walls of the gate electrodes 20, 22 and the silicon nitride film 18, a sidewall insulating film 24 made of a silicon nitride film is formed.

Next, ion implantation is performed using the gate electrode 22 and the sidewall insulating film 24 as a mask to form source / drain diffusion layers 30 in the silicon substrate 10 on both sides of the gate electrode 22.

Thus, a memory cell transistor having the gate electrode 20 and the source / drain diffusion layers 26 and 28 formed in the silicon substrate 10 on both sides thereof is formed in the memory cell region, and the gate electrode 20 is formed in the peripheral circuit region. Electrode 2
2 and a peripheral circuit transistor having source / drain diffusion layers 30 formed in the silicon substrate 10 on both sides thereof are formed (FIGS. 3A and 4A).

Next, after depositing, for example, a silicon oxide film on the entire surface by, eg, CVD, the surface is polished by CMP (Chemical Mechanical Polishing) until the silicon nitride film 18 is exposed.
An interlayer insulating film 32 made of a silicon oxide film having a planarized surface is formed.

Next, a through hole 34 reaching the source / drain diffusion layer 26 and a source / drain diffusion layer 26 are formed in the interlayer insulating film 32 by ordinary lithography and etching techniques.
A contact hole 36 reaching the drain diffusion layer 28;
Through hole 38 reaching source / drain diffusion layer 30
Are formed in a self-aligned manner with respect to the gate electrodes 20 and 22 and the sidewall insulating film 24 (FIGS. 3B and 4).
(B)).

Next, plugs 40, 4 are formed in contact holes 34, 36, 38 opened in interlayer insulating film 32.
2 and 44 are respectively embedded (FIGS. 3C and 4
(C)). For example, a polycrystalline silicon film is deposited by a CVD method and etched back to leave the polycrystalline silicon film only in the contact holes 34, 36, and 38, and then doped into the polycrystalline silicon film by an ion implantation method. The plugs 40, 42, and 44 made of doped polysilicon are formed with low resistance.

Next, the entire surface is formed by, for example, a CVD method.
For example, a silicon oxide film having a thickness of 50 to 100 nm is deposited, and an interlayer insulating film 46 made of the silicon oxide film is formed.

Next, a contact hole 48 reaching the plug 40 and a contact hole 50 reaching the plug 44 are formed by ordinary lithography and etching techniques.
Are formed on the interlayer insulating film 46 (FIG. 3D, FIG.
(D)). The cross section shown in FIG.
Are not shown, but are shown by dotted lines in the following drawings to clarify the positional relationship with other components.

Next, T is formed on the entire surface by, for example, CVD.
An iN (titanium nitride) film, a W (tungsten) film, and a silicon nitride film are sequentially deposited and patterned, and a bit whose upper surface is covered with the silicon nitride film 52 and connected to the source / drain diffusion layer 26 via the plug 40 is formed. A line 54 and a wiring layer 56 whose upper surface is covered with the silicon nitride film 52 and connected to the source / drain diffusion layer 30 through the plug 44
(FIGS. 3E and 4E). Note that FIG.
Although the bit line 54 does not appear in the cross section shown in (e), it is represented by a dotted line in the following drawings to clarify the positional relationship with other components.

Next, a silicon nitride film is deposited on the entire surface by, eg, CVD, and then etched back to form a bit line 5.
4 and a side wall insulating film (not shown) is formed on the side wall of the silicon nitride film 52.

Next, the entire surface is formed by, for example, the CVD method.
For example, a silicon oxide film having a thickness of 500 nm is deposited and CM
The surface is polished by the P method until the silicon nitride film 52 is exposed, and an interlayer insulating film 58 made of a silicon oxide film having a flattened surface is formed.

Next, a contact hole 60 reaching the plug 42 is formed in the interlayer insulating films 58 and 46 by ordinary lithography and etching techniques (FIG. 5).
(A)). The contact hole 60 can be opened in a self-aligned manner with respect to the silicon nitride film 52 formed on the bit line 54 and the sidewall insulating film (not shown) formed on the side wall of the bit line 54.

Next, plugs 62 are buried in the contact holes 60 opened in the interlayer insulating films 46 and 58 (FIG. 5B). For example, by the CVD method, for example, Ti
After sequentially depositing a (titanium) film, a TiN film and a W film,
The plug 62 is formed by leaving the W film, the TiN film, and the Ti film in the contact hole 50 by the MP method or the etch-back method.

Next, on the interlayer insulating film 58, for example, CV
By a method D, for example, a silicon nitride film having a thickness of about 40 nm is deposited, and an etching stopper film 64 made of the silicon nitride film is formed.

Next, on the etching stopper film 64,
For example, a silicon oxide film having a thickness of, for example, 100 nm is deposited by a CVD method, and an interlayer insulating film 66 made of the silicon oxide film is formed.

Next, on the interlayer insulating film 66, for example, CV
By a method D, for example, a silicon nitride film having a thickness of about 40 nm is formed, and an etching stopper film 68 made of the silicon nitride film is formed.

Next, on the etching stopper film 68,
For example, a silicon oxide film having a thickness of, for example, 700 nm is deposited by a CVD method, and an interlayer insulating film 70 made of the silicon oxide film is formed.

Next, on the interlayer insulating film 70, for example, CV
By method D, for example, an amorphous silicon film having a thickness of 50 nm is deposited, and a hard mask 72 made of the amorphous silicon film is formed (FIG. 5C).

It should be noted that the hard mask 72 takes into consideration a case where a photoresist film alone cannot provide sufficient masking properties when etching the thick interlayer insulating film 70.
When the photoresist film has sufficient resistance, it is not always necessary to form the photoresist film. Also, the etching stopper film 64
The interlayer insulating film 66 is for preventing the storage electrode from peeling off when the interlayer insulating film 70 in the memory cell region is selectively removed in a later step. Therefore, when there is no possibility that the storage electrode is peeled off, the etching stopper film 6
The etching stopper film 68, the interlayer insulating film 70, and the hard mask 72 may be deposited directly on the interlayer insulating film 58 without forming the interlayer insulating film 4 and the interlayer insulating film 66.

Next, the hard mask 72 and the interlayer insulating film 7 are formed by the usual lithography and etching techniques.
0 is patterned to form an opening 74 reaching the etching stopper film 68 (FIG. 6A). Opening 74
Are opened in a region where the storage electrode 80 is to be formed.

Next, the entire surface is formed by, for example, the CVD method.
For example, an amorphous silicon film having a thickness of about 5 nm is deposited and etched back, and a selective removal film 76 made of the amorphous silicon film is formed on the side wall of the opening 74.

Incidentally, the selective removal film 76 is formed of the interlayer insulating film 7.
0, etching stopper film 68, adhesion layer 7 to be formed later
The material may be any material that can be selectively removed from the storage electrode 8 and the storage electrode 80, and is not necessarily an amorphous silicon film. For example, a polycrystalline silicon film, a Ti film, an Al film,
A W film, a BPSG film, a Cu film, a C film, a deposition film for forming the opening 74, or the like can be used.

Next, using the hard mask 72 as a mask, the interlayer insulating film 70, the etching stopper film 68, the interlayer insulating film 66, and the etching stopper film 64 are anisotropically etched to expose the plugs 62 in the openings 74 (FIG. 9). 6
(B)).

Next, the whole surface is formed by, for example, the CVD method.
For example, a TiN film having a thickness of 5 to 10 nm and a thickness of, for example, 30
and a Ru film with a thickness of nm. Incidentally, the Ru film is used as the storage electrode 8.
0, and the TiN film is composed of the storage electrode 80 and the plug 6
2 or storage electrode 80 and etching stopper films 64 and 6
8 is a film that serves as an adhesion film 78 for improving the adhesion between the film 8 and the interlayer insulating film 66.

The conductive film for forming the storage electrode 80 is appropriately selected according to the compatibility with the capacitor dielectric film 86 to be formed later. For example, the capacitor dielectric film 86
When a dielectric film such as Ta ₂ O ₅ is used, Ru (ruthenium), RuOx
(Ruthenium oxide), W (tungsten), WN (tungsten nitride), or the like can be used. When a dielectric film such as BST (BaSrTiOx) or ST (SrTiOx) is used as the capacitor dielectric 86, the plate electrode 62 may be made of Pt (platinum), R
u, RuOx, W, SRO (SrRuO ₃ ) and the like can be used. When a dielectric film such as an ON (SiO ₂ / SiN) film is used as the capacitor dielectric film 86, doped polysilicon or the like can be used as the plate electrode 62. Further, when a dielectric film such as PZT is used as the capacitor dielectric film 86,
Pt or the like can be used as the plate electrode 62. In addition, TiOx (titanium oxide), SiN (silicon nitride), SiON (silicon nitride oxide), Al ₂ O
Even when a dielectric film such as ₃ (alumina) or SBT (SrBiTiOx) is used, it may be appropriately selected according to the compatibility with these dielectric films.

The conductive film for forming the adhesion layer 78 is a material having excellent adhesion between the storage electrode 80 and the plug 62 or between the storage electrode 80 and the etching stopper films 64 and 68 and the interlayer insulating film 66. . For example, when Ru (ruthenium), Pt (platinum), W (tungsten), SRO (SrRuO ₃ ), or the like is used as the storage electrode 80, TiN (titanium nitride) or WN
(Tungsten nitride) or the like can be used. In the present embodiment, a Ru film is assumed as the storage electrode 80, and the adhesion layer 78 is formed of a TiN film. It is desirable that the compatibility between the adhesion layer 78 and the capacitor dielectric film be good. However, even if the compatibility between these films is poor, deterioration of the capacitor characteristics can be prevented by means described later.

Next, for example, an SOG film is deposited on the entire surface by, eg, spin coating. The SOG film functions as an inner protective film that protects a region inside the storage electrode when the storage electrode 80 and the adhesion layer 78 are formed by polishing in a later step. For example, instead of the SOG film, a photoresist film is used. May be applied.

Next, the SOG film, the Ru film, the Ti film, and the Ti film are removed by, eg, CMP until the interlayer insulating film 70 is exposed on the surface.
The N film and the hard mask 72 are removed flat, and an adhesion layer 78 made of a TiN film formed in the opening 74 and a storage electrode 80 made of a Ru film formed in the opening 74.
And the opening 7 in which the adhesion layer 78 and the storage electrode 80 are formed.
Then, an inner protective film 82 made of an SOG film buried in the substrate 4 is formed (FIG. 7A). Thus, the storage electrode 8 having a height substantially equal to the height of the interlayer insulating film 70 in the peripheral circuit region
0 can be formed.

Next, the selective removal film 76 is replaced with the interlayer insulating film 7.
0, the etching stopper film 68, the adhesion layer 78, and the storage electrode 80 are selectively removed to form a gap 84 between the interlayer insulating film 70 and the adhesion layer 78 (FIG. 7B). For example, by performing wet etching with an aqueous solution containing hydrofluoric acid and nitric acid, the selective removal film 76 made of an amorphous silicon film can be selectively removed.

Next, the interlayer insulating film 70 and the inner protective film 82 in the memory cell region are etched by wet etching using, for example, a hydrofluoric acid aqueous solution, using the etching stopper film 68 as a stopper (FIG. 8A). On this occasion,
The etchant enters the gap 84, and the etching proceeds in the horizontal direction with respect to the substrate surface. Further, the interlayer insulating film 70 formed in the memory cell region exists in a region extremely narrower than its thickness. Therefore, the interlayer insulating film 70 in the memory cell region can be selectively removed while suppressing a decrease in the thickness of the interlayer insulating film 70 in the peripheral circuit region. For example, in the case of a device of the 0.13 μm rule, the interlayer insulating film 70 in the memory cell region can be removed while reducing the thickness of the interlayer insulating film 70 in the peripheral circuit region to about 50 nm.

Since the inner protective film 82 made of the SOG film has a higher etching rate than a silicon oxide film or the like deposited by the CVD method, it is completely removed at the same time as the etching of the interlayer insulating film 70.

Although there is a contact surface between the etching stopper film 68 and the adhesion layer 78 below the gap 84, the adhesion of these films is extremely excellent, and the etching liquid enters the lower layer of the etching stopper film 68. This does not damage the underlying structure such as the memory cell transistor.

The shape of the side wall of the interlayer insulating film 70 thus etched includes a portion reflecting the outer peripheral shape of the side wall of the storage electrode 80. That is, since the etching of the interlayer insulating film 70 proceeds isotropically from the side wall portion of the storage electrode 80, the shape of the etching surface of the interlayer insulating film 70 reflects the arrangement of the storage electrode 80 and the like. As a result, the shape of the side wall of the interlayer insulating film 70 near the boundary between the peripheral circuit region and the memory cell region also includes a portion reflecting the shape of the storage electrode 80.

Next, the adhesion layer 78 is selectively etched with respect to the storage electrode 80, the etching stopper film 68, and the interlayer insulating films 70 and 66 using, for example, an aqueous solution containing sulfuric acid and hydrogen peroxide (FIG. 8B). )). This etching is performed by using an adhesion layer 78 and a capacitor dielectric film 86 to be formed later.
Consider the case of poor compatibility, at least,
The adhesion layer 78 is etched until a gap is formed between the storage electrode 80 and the etching stopper film 68 and the interlayer insulating film 66. In the case where the contact between the adhesion layer 78 and the capacitor dielectric film 86 does not cause deterioration of the characteristics of the capacitor, the adhesion layer 78 does not necessarily need to be etched. A technique for preventing deterioration of the capacitor characteristics due to compatibility between the adhesion layer and the capacitor dielectric film is described in detail in Japanese Patent Application No. 10-315370 by the same applicant.

Next, the entire surface is formed, for example, by the CVD method.
For example, a Ta ₂ O ₅ film or a BST film having a thickness of 10 to 30 nm is deposited, and a capacitor dielectric film 86 made of Ta ₂ O ₅ or BST is formed.

Next, the entire surface is formed by, for example, the CVD method.
For example, after depositing a Ru film having a thickness of 50 to 300 nm, this Ru film is patterned by a usual lithography technique and etching technique to form a plate electrode 88 made of the Ru film (FIG. 9A). The plate electrode 8
The material constituting 8 is appropriately selected according to the compatibility with the capacitor dielectric film 86, similarly to the storage electrode 80.

Next, the entire surface is formed, for example, by the CVD method.
For example, a silicon oxide film having a thickness of 150 nm is deposited, and an interlayer insulating film 90 made of the silicon oxide film is formed.

Next, if necessary, a wiring layer (not shown) connected to the plate electrode 88 is formed on the interlayer insulating film 90.
Alternatively, a wiring layer (not shown) connected to the wiring layer 56 via the plug 92 is formed.

Thus, a DRAM comprising one transistor and one capacitor can be manufactured.

As described above, according to the present embodiment, the interlayer insulating film 70 in the memory cell region is etched by using the gap 84 formed on the side wall of the interlayer insulating film 70. The interlayer insulating film 70 in the memory cell region can be selectively removed. Thereby, the global step between the memory cell region and the peripheral circuit region can be reduced without significantly increasing the manufacturing cost. Therefore, even when a wiring layer is formed on interlayer insulating film 90, Fine lithography is easy, and the reliability of wiring can be improved.

In the above embodiment, since the interlayer insulating film 70 in the memory cell region is removed while the interlayer insulating film 70 in the peripheral circuit region is exposed on the surface, the thickness of the interlayer insulating film 70 in the peripheral circuit region is reduced. Although it cannot be avoided, for example, by applying the following process, the interlayer insulating film 70
Film reduction can be suppressed.

That is, first, in the step of forming the storage electrode 80 and the adhesion layer 78 in the opening 74 in a self-aligned manner shown in FIG.
2 remain without being removed (FIG. 10A).

Next, the selective removal film 76 is replaced with the interlayer insulating film 7.
0, the etching stopper film 68, the adhesion layer 78, and the storage electrode 80 are selectively removed to form a gap 84 between the interlayer insulating film 70 and the adhesion layer 78 (FIG. 10B).
Although the hard mask 72 is also etched in this etching, by forming the hard mask 72 to a sufficiently large thickness (for example, 100 nm), the hard mask 72 remains on the interlayer insulating film 70 even after the selective removal film 76 is removed. The mask 72 can be left. In addition, the selective removal film 7
6 and the hard mask 72 may be made of materials having different etching characteristics.

Next, the interlayer insulating film 70 in the memory cell region is selectively removed in the same manner as in the step shown in FIG. 8A (FIG. 11A). At this time, since the hard mask 72 remains on the interlayer insulating film 70 in the peripheral circuit region,
The thickness of the interlayer insulating film 70 does not decrease.

Next, by removing the hard mask 72, a structure similar to the structure shown in FIG. 8A can be formed (FIG. 11B).

In the above embodiment, the case where the interlayer insulating film 70 in the memory cell region is completely removed has been described. However, it is not necessary to remove all the interlayer insulating film 70 in the memory cell region. That is, the reason why the interlayer insulating film 70 in the memory cell region is removed is to allow the outer surface of the storage electrode 80 to be exposed and the plate electrode to be embedded.
The object can be achieved without removing all the interlayer insulating films 70.

Therefore, as shown in the plan view of FIG. 12, for example, the etching of the interlayer insulating film 70 is stopped in a state where the interlayer insulating film 70 in the form of a star remains between the four storage electrodes 80. Alternatively, the pillars of the interlayer insulating film 70 may remain along the word line direction (FIG. 12A) (FIG. 12B), or the interlayer insulating film 70 may extend along the bit line direction. May be left (FIG. 12C), or the columns of the interlayer insulating film 70 may be left in a matrix (FIG. 12D). The shape of the pillars of the remaining interlayer insulating film 70 thus includes a portion reflecting the shape of the storage electrode 80.

After forming the opening 74, a predetermined surface treatment is performed on the side wall portion of the interlayer insulating film 70 so that the etching solution permeates the side wall portion of the interlayer insulating film 70 instead of forming the selective removal film 76. This may be performed to form a low adhesion layer. For example, 400 to 400 including phosphorus and boron
A low-adhesion layer can be formed on the side wall of the interlayer insulating film 70 by, for example, a process of exposing the surface to a gas atmosphere at 500 ° C. or a process of immersing the surface in an alcohol solution to attach an organic substance.

[Second Embodiment] The semiconductor device and the method for fabricating the same according to a second embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first embodiment and the method for fabricating the same shown in FIGS. 2 to 11 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 13 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 14 to 16 are process sectional views showing the method for fabricating the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

As shown in FIG. 12, the semiconductor device according to the present embodiment is basically the same as the semiconductor device according to the first embodiment. The main feature of this embodiment is that the plate electrode 88 is formed in a self-aligned manner with respect to the interlayer insulating film 70.
It does not extend above zero. By forming the plate electrode 88 in a self-aligned manner, the first
The lithography step can be reduced by one step as compared with the method of manufacturing the semiconductor device according to the embodiment, and the manufacturing cost can be reduced.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, in the same manner as in the method for fabricating the semiconductor device according to the first embodiment shown in FIGS. 3A to 7A,
Adhesion layer 78 made of TiN film formed in opening 74
Then, a storage electrode 80 made of a Ru film formed in the opening 74 and an inner protective film 82 embedded in the opening 74 in which the adhesion layer 78 and the storage electrode 80 are formed are formed.

Next, the surfaces of the storage electrode 80, the adhesion layer 78, and the inner protective film 82 are etched, and these surfaces are recessed from the surface of the interlayer insulating film 70. For example, the storage electrode 8
0, the surface of the adhesion layer 78 and the surface of the inner protective film 82 are retracted, for example, by about 200 nm from the surface of the interlayer insulating film 70 (FIG. 14A).

Next, the selective removal film 76 is replaced with the interlayer insulating film 7.
0, the etching stopper film 68, the adhesion layer 78, and the storage electrode 80 are selectively removed to form a gap 84 between the interlayer insulating film 70 and the adhesion layer 78 (FIG. 14B).

Next, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment, the interlayer insulating film 70 and the inner protective film 82 are etched by, for example, wet etching using a hydrofluoric acid aqueous solution using the etching stopper film 68 as a stopper. Then, the interlayer insulating film 70 in the memory cell region is selectively removed while suppressing the film thickness of the interlayer insulating film 70 in the peripheral circuit region (FIG. 15A).

Next, the adhesion layer 78 is selectively etched with respect to the storage electrode 80, the etching stopper film 68, and the interlayer insulating films 70 and 66 (FIG. 16B).

Next, the entire surface is formed by, for example, the CVD method.
For example, a Ta ₂ O ₅ film or a BST film having a thickness of 10 to 30 nm is deposited, and a capacitor dielectric film 86 made of these films is formed.

Next, the entire surface is formed, for example, by the CVD method.
For example, a Ru film 87 having a thickness of 50 to 300 nm is deposited.

Next, the entire surface is formed, for example, by the CVD method.
For example, a silicon oxide film having a thickness of 150 nm is deposited, and an interlayer insulating film 89 made of a silicon oxide film is formed (FIG. 16).
(A)).

Next, the interlayer insulating film 8 is removed by, eg, CMP until at least the surface of the interlayer insulating film 70 is exposed.
9. The Ru film 87 and the capacitor dielectric film 86 are removed flat. As a result, the Ru film 87 in the peripheral circuit region is completely removed, and the Ru film 87, that is, the plate electrode 88 is selectively formed in the memory cell region. Therefore, when forming the plate electrode 88, it is not necessary to pattern the Ru film 87 through a lithography step, and the number of lithography steps can be reduced by one compared with the method of manufacturing the semiconductor device according to the first embodiment.

Next, the entire surface is formed, for example, by the CVD method.
For example, a silicon oxide film having a thickness of 150 nm is deposited, and an interlayer insulating film 90 made of the silicon oxide film is formed.

Next, if necessary, a wiring layer (not shown) connected to the plate electrode 88 is formed on the interlayer insulating film 90.
Alternatively, a wiring layer (not shown) connected to the wiring layer 56 via the plug 92 is formed.

Thus, a DRAM including one transistor and one capacitor can be manufactured.

As described above, according to the present embodiment, since the plate electrode 88 is formed in the memory cell region by self-alignment, the lithography process for forming the plate electrode 88 can be reduced.

In the above embodiment, after forming the Ru film 87 and the interlayer insulating film 89, the interlayer insulating film 89 and the Ru film 87 are removed by the CMP method, and the upper surface is covered with the interlayer insulating film 89 in the memory cell region. Although the plate electrode 88 made of the separated Ru film 87 is formed, the interlayer insulating film 89 in the memory cell region may be completely removed so that the plate electrode 88 is exposed on the entire surface of the memory cell region. Further, the interlayer insulating film 89 is not necessarily required to be formed.

[Third Embodiment] The semiconductor device and the method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first and second embodiments and the method of manufacturing the same shown in FIGS. 2 to 16 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 17 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 18 to 21 are process sectional views showing the method for fabricating the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

As shown in FIG. 17, the semiconductor device according to the present embodiment is basically the same as the semiconductor device according to the first embodiment. The main feature of the semiconductor device according to the present embodiment is that the storage electrode 80 is electrically connected to the source / drain diffusion layer 28 via the plug 42 and the plug 62 like the semiconductor devices according to the first and second embodiments. Instead, they may be electrically connected to the source / drain diffusion layers 28 only through the plugs 42. By configuring the semiconductor device in this manner, steps for forming the plug 62 can be reduced. Further, since the storage electrode 80 is supported by the interlayer insulating films 46 and 58, the storage electrode 80 is not easily peeled off even when the interlayer insulating film 70 is etched, and a structure for preventing the storage electrode 80 from peeling (the etching stopper film 64 and the interlayer insulating film). 66) does not need to be formed separately. Therefore, also from this point, the manufacturing process can be simplified.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, the memory cell transistor, the transistor for the peripheral circuit, the bit line 54, and the wiring layer 56 are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 3A to 4E. Etc. are formed.

Next, the entire surface is formed, for example, by the CVD method.
For example, a silicon oxide film having a thickness of 500 nm is deposited, and an interlayer insulating film 58 made of the silicon oxide film is formed.

Next, on the interlayer insulating film 58, for example, CV
By a method D, for example, a silicon nitride film having a thickness of about 40 nm is formed, and an etching stopper film 68 made of the silicon nitride film is formed.

Next, the etching stopper film 68 in a region where a contact hole for connecting the storage electrode 80 to the plug 42 is formed is removed by ordinary lithography and etching.

Next, on the patterned etching stopper film 68, for example, the film thickness of 7
A 00 nm silicon oxide film is deposited, and an interlayer insulating film 70 made of the silicon oxide film is formed.

Next, on the interlayer insulating film 70, for example, CV
An amorphous silicon film having a thickness of, for example, 50 nm is deposited by the method D, and a hard mask 72 made of the amorphous silicon film is formed (FIG. 18A).

Next, the hard mask 72 and the interlayer insulating film 7 are formed by ordinary lithography and etching.
0 is patterned to form an opening 74 reaching the etching stopper film 68 (FIG. 18B).

Next, the entire surface is formed, for example, by the CVD method.
For example, an amorphous silicon film having a thickness of about 5 nm is deposited and etched back to form a selective removal film 76 made of an amorphous silicon film on the side wall of the opening 74.
(A)).

Next, the interlayer insulating films 58 and 46 are etched using the hard mask 72 and the etching stopper film 68 as masks to expose the plugs 42 in the openings 74 (FIG. 19B).

Then, the adhesion layer 78, the storage electrode 80, and the inner protective film 82 are formed in the opening 74 in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. It is formed (20 (a)).

Next, for example, FIGS. 7B and 8A
As in the method for fabricating the semiconductor device according to the first embodiment, the selective removal film 76 is removed, and the interlayer insulating film 70 in the memory cell region is selectively removed (FIG. 20B). The etching stopper film 68 and the adhesion layer 7 are formed below the gap 84 formed by removing the selective removal film 76.
Although there is a contact surface with the etching stopper film 68, the adhesion of these films is extremely excellent.
Does not enter the lower layer and damage the interlayer insulating films 58, 46 and the like.

Next, the adhesion layer 78 is selectively etched with respect to the storage electrode 80, the etching stopper film 68, and the interlayer insulating film 70 (FIG. 21A). This etching is performed by using an adhesion layer 78 and a capacitor dielectric film 86 to be formed later.
Consider the case of poor compatibility, at least,
The adhesion layer 78 is etched until a gap is formed between the etching stopper film 68 and the storage electrode 80. If the contact between the adhesion layer 78 and the capacitor dielectric film 86 does not cause the deterioration of the characteristics of the capacitor, the adhesion layer 78
Need not necessarily be etched.

Next, for example, FIGS. 9A and 9B
In the same manner as in the method for fabricating the semiconductor device according to the first embodiment shown in FIG.
A plug 92, a wiring layer (not shown) connected to the plate electrode 88, a wiring layer (not shown) connected to the wiring layer 56 via the plug 92, and the like are formed (FIG. 21B).

Thus, a DRAM comprising one transistor and one capacitor can be manufactured.

As described above, according to the present embodiment, since the storage electrode 80 also serves as the lower plug, the manufacturing process can be further simplified.

In the above embodiment, the case where the plug 62 of the semiconductor device according to the first embodiment also serves as the storage electrode 80 is described. However, the plug 62 of the semiconductor device according to the second embodiment also serves as the storage electrode 80. You may.

[Fourth Embodiment] The semiconductor device and the method for fabricating the same according to a fourth embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first to third embodiments and the method for fabricating the same shown in FIGS. 2 to 21 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 22 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 23 to 25 are process sectional views showing the method for fabricating the semiconductor device according to the present embodiment.

In the first to third embodiments, the selective removal film 7
The interlayer insulating film 70 in the memory cell region was selectively etched using the gap 84 formed by removing the layer 6.
By applying a film (a low-adhesion layer) into which an etchant easily permeates instead of the selective removal film 76, the interlayer insulating film 70 in the memory cell region can be selectively etched without removing this film. It is. In the present embodiment, a semiconductor device using such a film and a manufacturing method thereof will be described.

First, the semiconductor device according to the present embodiment will be explained with reference to FIG.

In the semiconductor device according to the present embodiment, as shown in FIG. 22, a low-adhesion layer 94 is formed on the outer wall of the storage electrode 80 via an adhesion layer 78, and the low-adhesion layer 94 is It is characterized in that it forms part of the electrode surface. This difference from the semiconductor device shown in FIG. 2 is that the low adhesion layer 94 is used instead of the selective removal film 76, and unlike the selective removal film 76 that is removed during the process, the final difference is obtained. Even in a simple structure, the low adhesion layer 94 remains.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, the etching stopper film 68 penetrates the interlayer insulating film 70 in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 3A to 6A.
Is formed (FIG. 23A).

Next, on the entire surface, for example, by the CVD method,
For example, a Ti film having a thickness of 10 nm is deposited and etched back, and a low adhesion layer 94 made of a Ti film is formed on the side wall of the opening 74.
Is formed (FIG. 23B). Note that, in this specification, the low adhesion layer 94 refers to a film having poor adhesion between the interlayer insulating film 70 and an etchant that easily permeates an interface between the interlayer insulating film 70 and the low adhesion layer 94. Shall be. For example, in addition to the Ti film, a material such as a Ru film or a W film may be used as a material for the etchant to easily permeate into the interface with the interlayer insulating film 70 made of a silicon oxide film. Can be used.
Further, the low adhesion layer 94 is finally formed on the capacitor dielectric film 8.
6, it is necessary to apply a conductive film having good compatibility with the capacitor dielectric film 86.

Next, using the hard mask 72 as a mask, the interlayer insulating film 70, the etching stopper film 68, the interlayer insulating film 66, and the etching stopper film 64 are anisotropically etched to expose the plug 62 in the opening 74.

Then, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. 7A, for example, the adhesion layer 78 made of a TiN film formed in the opening 74 and the inside of the opening 74 are formed. Storage electrode consisting of Ru film formed and 8
0, opening 7 in which adhesion layer 78 and storage electrode 80 are formed
4 and an inner protective film 82 buried inside (FIG. 2)
4 (a)).

Next, the interlayer insulating film 70 and the inner protective film 82 are etched by, for example, wet etching using an aqueous solution of hydrofluoric acid using the etching stopper film 68 as a stopper. At this time, the etching solution permeates into the interface between the low adhesion layer 94 and the interlayer insulating film 70, and the etching proceeds in the horizontal direction with respect to the substrate surface. Further, the interlayer insulating film 70 formed in the memory cell region exists in a region much smaller than the peripheral circuit region. Therefore,
The interlayer insulating film 70 in the memory cell region can be selectively removed while suppressing a decrease in the thickness of the interlayer insulating film 70 in the peripheral circuit region (FIG. 24B).

Next, the adhesion layer 78 is selectively etched with respect to the storage electrode 80, the etching stopper film 68, the interlayer insulating film 70, and the low adhesion layer 94 (FIG. 25).
(A)). This etching is performed in consideration of the case where the adhesion layer 78 and the capacitor dielectric film 86 to be formed later are incompatible. For example, the etching is performed between the storage electrode 80 near the upper portion of the storage electrode 80 and the low adhesion layer 94. The adhesion layer 78 is etched until a gap of about 10 to 50 nm is formed. In the case where the contact between the adhesion layer 78 and the capacitor dielectric film 86 does not cause deterioration of the characteristics of the capacitor, the adhesion layer 78 does not necessarily need to be etched.

Next, for example, FIGS. 9A and 9B
In the same manner as in the method for fabricating the semiconductor device according to the first embodiment shown in FIG.
A wiring layer (not shown) connected to the plug 92 and the plate electrode 88, a wiring layer (not shown) connected to the wiring layer 56 via the plug 92, and the like are formed (FIG. 25B).

Thus, a DRAM comprising one transistor and one capacitor can be manufactured.

As described above, according to the present embodiment, since the interlayer insulating film 70 in the memory cell region is etched by using the low adhesion layer 94 formed on the side wall of the interlayer insulating film 70, a lithography process is performed. Thus, the interlayer insulating film 70 in the memory cell region can be selectively removed.
Thereby, the global step between the memory cell region and the peripheral circuit region can be reduced without significantly increasing the manufacturing cost. Therefore, even when a wiring layer is formed on interlayer insulating film 90, Fine lithography is easy, and the reliability of wiring can be improved.

In the above embodiment, the case where the low adhesion layer 94 is used in place of the selective removal film 76 in the semiconductor device according to the first embodiment has been described. However, in the semiconductor device according to the second and third embodiments, Can be similarly applied.

[Fifth Embodiment] The semiconductor device and the method for fabricating the same according to a fifth embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first to fourth embodiments and the method for fabricating the same shown in FIGS. 2 to 25 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

First, the semiconductor device according to the present embodiment will be explained with reference to FIG.

As shown in FIG. 26, the basic structure of the semiconductor device according to the present embodiment is the same as that of the semiconductor device according to the first embodiment shown in FIG. The semiconductor device according to the present embodiment is characterized mainly in that the structure of the capacitor is not a cylinder but a column.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, in the same manner as in the method for fabricating the semiconductor device according to the first embodiment shown in FIGS. 3A to 6B, for example, the interlayer insulating film 70, the etching stopper film 68, the interlayer insulating film 66, and An opening 74 that penetrates through the etching stopper film 64 and exposes the plug 62, a selective removal film 76, and the like are formed (FIG. 27A).

Next, the entire surface is formed, for example, by the CVD method.
For example, a TiN film having a thickness of 10 nm and a
Is deposited. The Ru film is a film that becomes the storage electrode 80, and the TiN film is an adhesion for enhancing the adhesion between the storage electrode 80 and the plug 62 or between the storage electrode 80 and the etching stopper films 64 and 68 and the interlayer insulating film 66. This is a film to be the film 78.

Next, the Ru film, the TiN film, and the hard mask 72 are flatly removed by, eg, CMP until the interlayer insulating film 70 is exposed on the surface, and is made of the TiN film formed in the opening 74. The adhesion layer 78 and the opening 74
A columnar storage electrode 80 made of a Ru film embedded therein is formed (FIG. 27B).

Next, the selective removal film 76 is replaced with the interlayer insulating film 7.
0, the etching stopper film 68, the adhesion layer 78, and the storage electrode 80 are selectively removed to form a gap 84 between the interlayer insulating film 70 and the adhesion layer 78 (FIG. 28A).

Next, the interlayer insulating film 70 in the memory cell region is selectively removed, for example, in the same manner as in the method for fabricating the semiconductor device according to the first embodiment shown in FIG. 8A (FIG. 28).
(B)).

Next, the adhesion layer 78 is selectively etched with respect to the storage electrode 80, the etching stopper film 68, and the interlayer insulating films 70 and 66 (FIG. 29B).

Next, for example, FIGS. 9A and 9B
In the same manner as in the method for fabricating the semiconductor device according to the first embodiment shown in FIG.
A wiring layer (not shown) connected to the plug 92 and the plate electrode 88, a wiring layer (not shown) connected to the wiring layer 56 via the plug 92, and the like are formed (FIG. 29B).

In this way, a DRAM comprising one transistor and one capacitor can be manufactured.

As described above, according to the present embodiment, even in the semiconductor device having the columnar storage electrode 80, the global step between the memory cell region and the peripheral circuit region can be reduced without greatly increasing the manufacturing cost. Can be eased. Therefore, even when a wiring layer is formed on the interlayer insulating film 90, fine lithography is easy,
In addition, the reliability of the wiring can be improved.

In the above embodiment, the example in which the columnar capacitor is applied to the semiconductor device according to the first embodiment and the method for manufacturing the same has been described. However, the same applies to the semiconductor device according to the first to fourth embodiments and the method for manufacturing the same. Then, a columnar capacitor can be applied.

[Modified Embodiment] The present invention is not limited to the above-described embodiment, and various modifications can be made.

For example, in the above embodiment, the description has been given as a DRAM capacitor. However, the present invention is not limited to a DRAM, but is applied to a semiconductor integrated circuit device requiring a large number of capacitors. By applying the present invention to a ferroelectric memory (FeRAM) having a configuration similar to that described above, a highly integrated FeRAM can be manufactured.

In the above embodiment, a COB (Capacitor Over Bit L) in which a capacitor is arranged above the bit line is provided.
ine) The case where the present invention is applied to the structure is shown.
The present invention relates to a capacitor and an interlayer insulating film in a peripheral circuit region, and has no direct relation to a position of a bit line. Therefore, the present invention can be similarly applied to a CUB (Capacitor Under Bit Line) structure in which a bit line is arranged above a capacitor.

As described in detail above, the features of the semiconductor device and the method of manufacturing the same according to the present invention are summarized as follows.

(Supplementary Note 1) A substrate including a first region and a second region in contact with the first region, and a substrate formed on the substrate and having a connection hole formed in the first region. An insulating film, an adhesion layer formed on the substrate in at least the connection hole, a storage electrode formed on the adhesion layer and protruding above the first insulating film, and A formed dielectric film, a plate electrode covering the storage electrode with the dielectric film interposed therebetween, and a side wall formed on the first insulating film in the second region and having a side wall shape of the storage electrode And a second insulating film including a portion reflecting the outer peripheral shape of the semiconductor device.

[0179] The "substrate" in this specification includes not only a semiconductor substrate such as a silicon substrate but also a semiconductor substrate on which transistors, wiring layers, insulating films, and the like are formed.

(Supplementary Note 2) In the semiconductor device according to Supplementary Note 1, the insulating film is formed of the same insulating layer as the second insulating film, and is formed on the first insulating film in the first region. And a third insulating film including a portion whose side wall shape reflects the outer peripheral shape of the side wall of the storage electrode.

(Supplementary Note 3) A substrate including a first region and a second region in contact with the first region, a first insulating film formed on the second region, A storage electrode formed in the region and protruding above the substrate, an adhesion layer formed on at least a side wall of the storage electrode, and an adhesion layer formed on the side wall of the storage electrode via the adhesion layer, and A low adhesion layer having lower adhesiveness than the adhesion layer, a dielectric film covering the storage electrode via the adhesion layer and the low adhesion layer, the adhesion layer, the low adhesion layer, and the dielectric film. And a plate electrode that covers the storage electrode through the storage electrode, and wherein the first insulating film includes a portion whose side wall shape reflects the outer peripheral shape of the side wall of the storage electrode.

(Supplementary Note 4) The semiconductor device according to supplementary note 3, wherein the insulating film is formed of the same insulating layer as the first insulating film, and is formed on the substrate in the first region, A semiconductor device further comprising a second insulating film including a portion whose side wall shape reflects the outer peripheral shape of the side wall of the storage electrode.

(Supplementary Note 5) A step of forming a first insulating film on a substrate including a first region and a second region in contact with the first region, and forming the first insulating film in the first region. Forming an opening reaching the substrate in the insulating film, forming an adhesion layer on the inner wall and bottom of the opening, and forming a storage electrode in the opening where the adhesion layer is formed. And a step of moving the first insulating film horizontally with respect to the surface of the substrate from an interface between the adhesion layer and the first insulating film so that the first insulating film in the second region remains. A semiconductor device comprising: a step of etching in a direction; a step of forming a dielectric film covering the storage electrode; and a step of forming a plate electrode covering the storage electrode via the dielectric film. Production method.

(Supplementary Note 6) In the method of manufacturing a semiconductor device according to Supplementary Note 5, between the step of forming the opening and the step of forming the adhesion layer, a selective removal film is formed on an inner wall of the opening. A step of selecting the selective removal film with respect to the first insulating film, the adhesion layer, and the storage electrode between the step of forming the storage electrode and the step of etching the first insulating film. And forming a gap between the first insulating film and the adhesion layer. In the step of etching the first insulating film, the infiltration of an etching solution into the gap is performed. A method of manufacturing the semiconductor device, wherein the first insulating film is etched in a horizontal direction with respect to a surface of the substrate by using the first insulating film.

(Supplementary Note 7) In the method of manufacturing a semiconductor device according to Supplementary Note 5, between the step of forming the opening and the step of forming the adhesion layer, the first insulating film is provided on an inner wall of the opening. Forming a low-adhesion layer having lower adhesion to a film than the adhesion layer; and etching the first insulating film, wherein the low-adhesion layer and the first
A method of manufacturing a semiconductor device, characterized in that the first insulating film is etched in a horizontal direction with respect to the surface of the substrate by utilizing the penetration of an etchant at an interface with the insulating film.

(Supplementary Note 8) In the method of manufacturing a semiconductor device according to any one of Supplementary Notes 5 to 7, the step of etching the first insulating film includes the step of etching the first insulating film in the second region. A method of manufacturing a semiconductor device, wherein the method is performed in a state where the semiconductor device is exposed.

(Supplementary Note 9) In the method of manufacturing a semiconductor device according to any one of Supplementary Notes 5 to 7, in the step of forming the opening, a hard mask formed on the first insulating film is used as a mask. The step of forming the opening by etching the first insulating film and etching the first insulating film is performed in a state where the first insulating film is covered with the hard mask. A method for manufacturing a semiconductor device.

(Supplementary Note 10) Any one of Supplementary Notes 5 to 9
In the method of manufacturing a semiconductor device according to the above item, before the step of forming the first insulating film, the first insulating film is formed on the substrate.
The method further comprises the step of forming a second insulating film having a different etching characteristic from the insulating film and having good adhesion to the adhesion layer. In the step of etching the first insulation film, 2. A method for manufacturing a semiconductor device, wherein an insulating film is used to prevent an etchant from permeating into the substrate.

[0189]

As described above, according to the present invention, in a method of manufacturing a semiconductor device in which a conductive film is deposited in an opening formed in an insulating film and a storage electrode is formed by using the conductive film, the storage electrode is formed in the opening. A selective removal film is formed on the inner wall of the opening before forming the conductive film to be formed, and after the storage electrode is formed, the selective removal film is selectively removed, and the selective removal film is removed. Since the insulating film in the memory cell region is selectively removed from the gap, the interlayer insulating film in the memory cell region can be selectively removed without going through a lithography step. Thereby, the global step between the memory cell region and the peripheral circuit region can be reduced without significantly increasing the manufacturing cost. Therefore, even when a wiring layer is formed on an interlayer insulating film, fine lithography is easy, and the reliability of the wiring can be improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating the principle of a semiconductor device and a method of manufacturing the same according to the present invention.

FIGS. 2A and 2B are a schematic sectional view and a plan view, respectively, showing the structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a process sectional view (part 4) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a process sectional view (part 5) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a process sectional view (part 6) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a process sectional view (part 7) showing the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 10 is a process sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the modification of the first embodiment of the present invention.

FIG. 11 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the modification of the first embodiment of the present invention.

FIG. 12 is a plan view showing a semiconductor device and a method of manufacturing the same according to another modification of the first embodiment of the present invention.

FIG. 13 is a schematic sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 14 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a schematic sectional view illustrating the structure of a semiconductor device according to a third embodiment of the present invention;

FIG. 18 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the third embodiment of the present invention.

FIG. 20 is a process cross-sectional view (part 3) illustrating the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 21 is a process sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 22 is a schematic sectional view illustrating the structure of a semiconductor device according to a fourth embodiment;

FIG. 23 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the fourth embodiment of the present invention;

FIG. 24 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the fourth embodiment of the present invention.

FIG. 25 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the fourth embodiment of the present invention.

FIG. 26 is a schematic sectional view showing the structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 27 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the fifth embodiment of the present invention.

FIG. 28 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the fifth embodiment of the present invention.

FIG. 29 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the fifth embodiment of the present invention;

FIG. 30 is a process sectional view (part 1) illustrating the conventional method for manufacturing a semiconductor device.

FIG. 31 is a process sectional view (part 2) for illustrating the conventional method of manufacturing a semiconductor device.

FIG. 32 is a process sectional view (part 3) for illustrating the conventional method of manufacturing a semiconductor device.

FIG. 33 is a process sectional view (part 4) for illustrating the conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Element isolation film 14, 16 ... Gate insulating film 18 ... Silicon nitride film 20, 22 ... Gate electrode 24 ... Side wall insulating film 26, 28, 30 ... Source / drain diffusion layer 32 ... Interlayer insulating film 34 .. 36, 38 contact holes 40, 42, 44 plug 46 interlayer insulating film 48, 50 contact hole 52 silicon nitride film 54 bit line 56 wiring layer 58 interlayer insulating film 60 contact hole 62 plug 64 ... Etching stopper film 66 ... Interlayer insulating film 68 ... Etching stopper film 70 ... Interlayer insulating film 72 ... Hard mask 74 ... Opening 76 ... Selective removal film 78 ... Adhesive layer 80 ... Storage electrode 82 ... Inner protective film 84 ... Gap 86 ... Capacitor dielectric film 87 ... Ru film 88 ... Plate electrodes 89, 90 ... Interlayer insulating film 92 ... Lug 94 ... Low adhesion layer 100 ... Silicon substrate 102,108 ... Gate electrode 104,106,110 ... Source / drain diffusion layer 112 ... Plug 114 ... Bit line 116 ... Wiring layer 118,120 ... Interlayer insulating film 122,124 ... Plug 126 Etch stopper film 128 Interlayer insulating film 130 Hard mask 132 Opening 134 Conductive film 136 Inner protective film 138 Storage electrode 140 Photoresist film 142 Capacitor dielectric film 144 Plate electrode 146 Interlayer Insulating film 148 ... Wiring layer

Claims (5)

[Claims] A substrate including a first region and a second region in contact with the first region; a first region formed on the substrate and having a connection hole formed in the first region. An insulating film, an adhesion layer formed at least on the substrate in the connection hole, a storage electrode formed on the adhesion layer, protruding above the first insulating film, and formed on the storage electrode. A dielectric film, a plate electrode covering the storage electrode via the dielectric film, and a sidewall formed on the first insulating film in the second region, wherein a shape of the sidewall is an outer periphery of a sidewall of the storage electrode. And a second insulating film including a portion reflecting the shape. 2. a step of forming a first insulating film on a substrate including a first region and a second region in contact with the first region; and forming the first insulating film in the first region. Forming an opening reaching the substrate in the film; forming an adhesion layer on the inner wall and the bottom of the opening; and forming a storage electrode in the opening where the adhesion layer is formed. In order to leave the first insulating film in the second region,
A step of etching the first insulating film in a horizontal direction with respect to a surface of the substrate from an interface between the adhesion layer and the first insulating film; and a step of forming a dielectric film covering the storage electrode. Forming a plate electrode that covers the storage electrode through the dielectric film. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a selective removal film is formed on an inner wall of the opening between the step of forming the opening and the step of forming the adhesion layer. Between the step of forming the storage electrode and the step of etching the first insulating film,
Forming a gap between the first insulating film and the adhesion layer by selectively removing the insulating film, the adhesion layer, and the storage electrode, and forming the first insulation film. And etching the first insulating film in a horizontal direction with respect to the surface of the substrate by utilizing the penetration of an etchant into the gap. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the first insulating film is provided on an inner wall of the opening between the step of forming the opening and the step of forming the adhesion layer. Forming a low-adhesion layer having lower adhesion to the first adhesion film than the adhesion layer, wherein the step of etching the first insulating film includes an interface between the low-adhesion layer and the first insulation film. And etching the first insulating film in the horizontal direction with respect to the surface of the substrate by utilizing the penetration of the etching solution in the method. 5. The method for manufacturing a semiconductor device according to claim 2, wherein the step of etching the first insulating film includes the step of etching the first insulating film in the second region. A method for manufacturing a semiconductor device, wherein the method is performed in an exposed state.