JP2001345282A - Method of manufacturing nitride-based iii group compound semiconductor and nitride-based iii group compound semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride-based III group compound semiconductor in which through dislocation density is suppressed. SOLUTION: A first nitride-based III group compound semiconductor layer 31 is etched to form islands in a spotty pattern, a stripe pattern, or a lattice pattern to form steps, wherein the bottom parts are so formed as to expose the substrate by removing a part of the substrate. A second nitride-based III group compound semiconductor layer 32 can be grown even to an upper region above the steps by epitaxially growing in horizontal directions by utilizing the upper face and the side faces of each upper part of the steps for the nuclei. The upper region of the second compound semiconductor layer 32 epitaxially grown in horizontal directions can be a region where propagation of the through dislocations possessed by the first compound semiconductor layer 31 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for producing a group III nitride compound semiconductor. In particular, the present invention relates to a method for manufacturing a group III nitride compound semiconductor using lateral epitaxial growth (ELO). In addition, the group III nitride-based compound semiconductor is, for example, a binary system such as AlN, GaN, and InN, Al _{x
Ga 1-x N, Al x} In 1-x N, Ga x In 1-x N ( both 0 <x <1) 3-way systems, such _{as, Al x Ga y In 1-} xy N (0 <x <1, 0 <y <1, 0
<X + y <1) General formula Al _x Ga _y In _1-xy N including the quaternary system
(0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). In the present specification, unless otherwise specified, a group III nitride-based compound semiconductor is simply referred to as a group III nitride-based compound semiconductor doped with an impurity for changing the conductivity type to p-type or n-type.
The expression also includes a group I nitride-based compound semiconductor.

[Prior art]

[0002] In the case of a light emitting device, for example, a group III nitride-based compound semiconductor is a direct transition type semiconductor having an emission spectrum ranging from ultraviolet to red over a wide range.
(LED) and laser diodes (LD). In addition, since its band gap is wide, stable operation can be expected at a higher temperature than elements using other semiconductors. Therefore, application to transistors such as FETs has been actively developed. In addition, because arsenic (As) is not the main component, development of various semiconductor devices in general is expected from an environmental point of view. In this group III nitride compound semiconductor, sapphire is usually used as a substrate and is formed thereon.

[0003]

However, when a group III nitride compound semiconductor is formed on a sapphire substrate, dislocation occurs due to a misfit in the lattice constant between sapphire and the group III nitride compound semiconductor. There is a problem that the element characteristics are not good. The dislocation due to the misfit is a threading dislocation penetrating the semiconductor layer in the vertical direction (perpendicular to the substrate surface), and a problem that a dislocation of about 10 ⁹ cm ⁻² propagates in the group III nitride compound semiconductor. There is. This propagates each group III nitride compound semiconductor layer having a different composition to the uppermost layer. As a result, for example, in the case of a light emitting element, there is a problem that the element characteristics such as the threshold current of the LD and the element life of the LD and the LED are not improved. Also,
Other semiconductor devices have only been low in mobility (mobility) because electrons are scattered by defects. These were the same when other substrates were used.

[0004] This will be described with reference to the schematic diagram of FIG.
FIG. 9 shows a substrate 91 and a buffer layer 9 formed thereon.
2 and a group III nitride-based compound semiconductor layer 93 formed thereon. The substrate 91 is sapphire or the like, and the buffer layer 92 is aluminum nitride.
(AlN) is conventionally used. Aluminum nitride (Al
The buffer layer 92 of (N) is provided for the purpose of alleviating the misfit between the sapphire substrate 91 and the group III nitride compound semiconductor layer 93, but the occurrence of dislocations cannot be reduced to zero. . This dislocation generation point 900
From there, threading dislocations 901 propagate in the vertical direction (perpendicular to the substrate surface), and penetrate through the buffer layer 92 and the group III nitride compound semiconductor layer 93 as well. In this manner, when various desired group III nitride compound semiconductors are laminated on the layer above the group III nitride compound semiconductor layer 93 to form a semiconductor device, the surface of the group III nitride compound semiconductor layer 93 is formed. From the reached dislocation 902, the threading dislocation further propagates in the semiconductor device in the vertical direction. As described above, in the related art, when forming a group III nitride-based compound semiconductor layer,
There is a problem that propagation of dislocations cannot be prevented.

In recent years, in order to prevent threading dislocations,
Techniques using lateral growth have been developed. This is a sapphire substrate, or a silicon oxide having a partially striped window formed on a group III nitride compound semiconductor layer, a mask made of tungstate, etc. is formed, and the semiconductor in the window is used as a nucleus. It is to grow laterally on the mask. Further, a growth method called a Pendio ELO in which a lateral growth portion is formed so as to float on a substrate has been developed. However, in the case of ELO using a mask,
Since the upper surface of the mask is located higher than the window portion of the semiconductor layer which is a nucleus for crystal growth, crystal growth is performed once in the vertical direction with the semiconductor in the window portion as a nucleus, and then horizontally on the mask so as to go around the mask. It grows in the direction. For this reason,
There is a problem in that dislocations and distortions are often generated at the corners of the mask, and threading dislocations generated in these portions suppress a decrease in threading dislocations. Also in the Pendio ELO, a mask is formed on the upper surface of the layer serving as a nucleus for crystal growth.
There is a problem that threading dislocations are similarly generated at the corners.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to produce a group III nitride compound semiconductor in which the generation of threading dislocations is suppressed.
In particular, it is to improve the drawbacks of ELO growth using a mask.

[0007]

Means for Solving the Problems To solve the above problems, the invention according to claim 1 is directed to a method of manufacturing a group III nitride compound semiconductor on a substrate by epitaxially growing a group III nitride compound semiconductor. , At least one layer of a group III nitride compound semiconductor,
A step of forming a base layer to be a group III nitride compound semiconductor on the substrate, and etching the base layer and at least a part of the substrate surface into an island state such as a dot, a stripe, or a lattice, A step of providing a step between the upper stage where the base layer is formed on the substrate surface and the lower stage where the base layer is not formed, which is a concave part of the substrate surface; and a dot, stripe or lattice shape formed by etching. A step of epitaxially growing a second group III nitride-based compound semiconductor in vertical and horizontal directions using the upper surface and side surfaces of the upper step of the island-like base layer as nuclei. In this specification, the term “base layer” refers to a single-layer group III nitride-based compound semiconductor layer and a group III nitride-based compound semiconductor layer having at least one layer.
It is used to represent multiple layers including layers collectively. Also,
Here, the island state conceptually refers to the state of the upper stage of the step formed by etching, and does not necessarily mean a region where each is separated, but forms an entire stripe on the wafer or a lattice. For example, the upper part of the step may be continuous in an extremely wide range. Further, the side surface of the step does not necessarily mean that the side surface is perpendicular to the substrate surface and the surface of the group III nitride compound semiconductor, but may be an oblique surface. The same applies to the following claims unless otherwise specified.

The invention according to claim 2 is characterized in that substantially the entire side surface of the step is a {11-20} plane.

[0009] The invention according to claim 3 is the first II.
It is characterized in that the group I nitride compound semiconductor and the second group III nitride compound semiconductor have the same composition. Here, the same composition means that a difference in the degree of doping (a difference of less than 1% in molar ratio) is neglected.

[0010] The invention described in claim 4 is the first invention.
A group III nitride compound semiconductor layer produced by the method for producing a group III nitride compound semiconductor according to any one of claims 3 to 3, wherein the group III nitride compound semiconductor layer is formed on a laterally epitaxially grown portion. Group III nitride compound semiconductor device.

The invention described in claim 5 is the first invention.
A group III nitride compound semiconductor layer manufactured by the method of manufacturing a group III nitride compound semiconductor according to any one of claims 3 to 3, wherein a different group III nitride compound A group III nitride compound semiconductor light emitting device obtained by laminating compound semiconductor layers.

The invention according to claim 6 is the first invention.
In addition to the method of manufacturing a group III nitride compound semiconductor according to any one of claims 3 to 3, by removing substantially all but the upper layer of the portion epitaxially grown laterally,
A method for manufacturing a group III nitride compound semiconductor substrate, comprising obtaining a group III nitride compound semiconductor substrate.

[0013]

Functions and effects of the present invention The outline of the method for producing a group III nitride compound semiconductor of the present invention will be described with reference to FIG. Although FIG. 1 shows a diagram having a substrate 1 and a buffer layer 2 to assist the explanation and understanding of the dependent claims, the present invention relates to a group III nitride compound semiconductor having threading dislocations in the vertical direction. The purpose of the present invention is to obtain a group III nitride compound semiconductor layer having a region in which threading dislocations in the vertical direction are reduced, and the buffer layer 2 is not an essential element of the present invention. Hereinafter, as shown in FIG. 1A, a first group III nitride-based material having threading dislocations in the vertical direction (perpendicular to the substrate surface) formed on the surface of the substrate 1 via the buffer layer 2 An example in which the present invention is applied using the compound semiconductor layer 31 will be used to explain a main part of the effects of the present invention. Note that the buffer layer 2 and the first group III nitride-based compound semiconductor layer 31 form a base layer.

As shown in FIG. 1B, the base layer and the substrate 1 are etched and cut into an island state such as a dot, a stripe, or a lattice to provide a step. The lower part of the step is a concave portion of the substrate 1. Here, as shown in FIG. 1C, the second group III nitride-based compound semiconductor 32 is vertically formed with a base layer composed of the buffer layer 2 and the first group III nitride-based compound semiconductor layer 31 as a nucleus. And laterally epitaxial growth. Thus,
A gap is formed between the upper surface 31a and the side surface 31b of the upper part of the step as a nucleus, and the second group III nitride compound semiconductor 32 is epitaxially grown in the vertical and horizontal directions to fill the step and fill the step. Can be formed and grown upward. At this time, the upper part of the portion where the second group III nitride-based compound semiconductor 32 has been laterally epitaxially grown is the first group III nitride-based compound semiconductor layer 3.
Propagation of threading dislocations of the semiconductor device 1 is suppressed, and a region where threading dislocations are reduced can be formed in the buried step portion. Thus, the lateral growth is immediately realized with the side surface 31b of the step as a nucleus. That is,
In ELO using a conventional mask, the mask is thicker by the thickness of the mask than a portion serving as a nucleus for crystal growth. As a result, crystal growth first grows vertically to compensate for the thickness of this mask, and then wraps around the top surface of the mask,
Will grow laterally. As a result, the crystal is distorted due to the wraparound at the corner of the mask, which causes dislocation. In the present invention, first, the second group III nitride compound semiconductor layer 32 grows from above in the lateral direction above the concave portion of the substrate 1 instead of the wraparound growth on the mask, so that no strain is applied to the crystal. No dislocations are generated. A gap may be formed between the concave portion of the substrate 1 and the second group III nitride compound semiconductor layer 32 for growth. Therefore, there is no distortion from the concave portion of the substrate 1. Therefore, it is possible to obtain higher quality crystals. In addition, a conventional ELO that grows around a mask
In the growth, the layers grown from the nuclei on both sides merge at the center, and it is known that the crystal axes on both sides are slightly tilted at this time. The occurrence of this tilt can be prevented by forming a gap between the concave portion of the substrate 1 and the second group III nitride compound semiconductor layer 32. Thereby, a higher quality lateral growth layer can be obtained as compared with the related art.

The above-mentioned rapid lateral epitaxial growth can be easily realized when the side surface of the step of the group III nitride compound semiconductor layer 31 is a {11-20} plane (claim 2). At this time, for example, at least the upper part of the growth surface during the lateral epitaxial growth can be kept as the {11-20} plane. If the first group III nitride compound semiconductor and the second group III nitride compound semiconductor have the same composition, rapid lateral epitaxial growth can be easily realized (claim 3).

By the above-described method, a second group III nitride compound semiconductor 32 in which threading dislocations propagating from the first group III nitride compound semiconductor layer 31 are suppressed can be formed. Although FIG. 1 shows an example in which a step having a side surface perpendicular to the substrate surface is formed, the present invention is not limited to this, and the side surface of the step may be an oblique surface.

By forming an element above the laterally epitaxially grown portion of the group III nitride compound semiconductor layer obtained in the above step, a semiconductor element having a layer with few defects and high mobility is obtained. (Claim 4).

By forming a light emitting element above the laterally epitaxially grown portion of the group III nitride compound semiconductor layer obtained in the above step, the life of the element or the LD
(Light emitting element) with an improved threshold value (claim 5).

Further, by separating only the upper layer of the laterally epitaxially grown portion of the group III nitride compound semiconductor layer obtained in the above step from other layers, a crystal in which crystal defects such as dislocations are significantly suppressed is obtained. A group III nitride-based compound semiconductor having good properties can be obtained (claim 6). In addition, "substantially all removal" indicates that the present invention is included in the present invention even if it includes a part in which threading dislocation remains partly from the viewpoint of simplicity in production.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically shows an example of an embodiment of a method for producing a group III nitride compound semiconductor according to the present invention. A buffer layer 2 and a first group III nitride compound semiconductor layer 31 are formed on a substrate 1 and used as a base layer (FIG. 1A). The base layer and the substrate 1 are etched to form a step (FIG. 1B). Next, a second group III nitride compound semiconductor layer 32 is laterally epitaxially grown (FIG. 1C). FIG. 1C assumes that the lateral epitaxial growth surface is, for example, a {11-20} surface, but the present invention is not limited to the growth surface.
In the lateral growth step of FIG. 1C, by optimizing the growth temperature and pressure and the III / V ratio of the supplied material, the lateral growth can be made much faster than the vertical growth. Thus, by setting the lateral epitaxial growth conditions so that the lateral growth with the base layer formed on the upper surface of the step as a nucleus unites above the concave portion on the surface of the etched substrate 1, the etched substrate is set. A region in which threading dislocation is suppressed is formed in the second group III nitride-based compound semiconductor 32 above the concave portion on one surface (FIG. 1 (d)).

The embodiment of the present invention can be selected from the following.

When a group III nitride compound semiconductor is sequentially formed on a substrate, sapphire, silicon (Si), silicon carbide (SiC), spinel (MgAl ₂ O ₄ ), Zn
O, MgO or other inorganic crystal substrates, III-V group compound semiconductors such as gallium phosphide or gallium arsenide, or group III nitride compound semiconductors such as gallium nitride (GaN) can be used.

As a method for forming the group III nitride compound semiconductor layer, metal organic chemical vapor deposition (MOCVD or MOVPE) is preferable, but molecular beam vapor deposition (MBE), halide vapor deposition (Halide VPE). ), Liquid phase epitaxy (LPE) or the like may be used, and each layer may be formed by a different growth method.

For example, when laminating a group III nitride compound semiconductor on a sapphire substrate, in order to form it with good crystallinity,
It is preferable to form a buffer layer to correct lattice mismatch with the sapphire substrate. When using another substrate, it is desirable to provide a buffer layer. As the buffer layer, a group III nitride compound semiconductor Al _x Ga formed at a low temperature is used.
_y In _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), more preferably Al _x Ga _1-x N (0 ≦ x ≦ 1). This buffer layer may be a single layer or a multilayer having different compositions and the like. The buffer layer may be formed at a low temperature of 380 to 420 ° C.
It may be formed by a VD method. Alternatively, a buffer layer made of AlN can be formed by a reactive sputtering method using a high-purity metal aluminum and a nitrogen gas as raw materials using a DC magnetron sputtering apparatus. Similarly general formula _{Al x Ga y In 1-xy} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1, the composition ratio is optional) can form a buffer layer. Further, a vapor deposition method, an ion plating method, a laser ablation method, and an ECR method can be used. The buffer layer formed by physical vapor deposition is desirably formed at 200 to 600 ° C.
More preferably, the temperature is 300 to 500 ° C, and more preferably,
350-450 ° C. When a physical vapor deposition method such as these sputtering methods is used, the thickness of the buffer layer is 100 to 3
000Å is desirable. More preferably, it is 100 to 400 °, most preferably 100 to 300 °. As the multilayer, for example, a layer composed of Al _x Ga _1-x N (0 ≦ x ≦ 1) and GaN
There is a method in which layers are alternately formed, and layers having the same composition are alternately formed at a formation temperature of, for example, 600 ° C. or lower and 1000 ° C. or higher. Of course, these may be combined, and the multilayer is composed of three or more group III nitride-based compound semiconductors Al _x Ga _y In
_1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) may be stacked. Generally, the buffer layer is amorphous and the intermediate layer is single crystal. A plurality of cycles may be formed with the buffer layer and the intermediate layer as one cycle, and the repetition may be an arbitrary cycle. The more repetitions, the better the crystallinity.

In the buffer layer and upper group III nitride compound semiconductor, part of the group III element composition can be replaced with boron (B) or thallium (Tl), or the composition of nitrogen (N) can be reduced. Parts are phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi)
The present invention can be substantially applied even if it is replaced by. Further, these elements may be doped to such an extent that they cannot be displayed in composition. For example, a group III nitride-based compound semiconductor having no indium (In) or arsenic (As) in the composition of Al _x Ga _1-x N (0
≦ x ≦ 1), by doping aluminum (Al), indium (In) having a larger atomic radius than gallium (Ga), or arsenic (As) having a larger atomic radius than nitrogen (N), a nitrogen atom The crystal distortion may be improved by compensating for the expansion strain of the crystal due to the loss of the crystal with the compression strain. In this case, the acceptor impurity is III
A p-type crystal can also be obtained by as-grown since it easily enters the position of the group atom. By improving the crystallinity in this way, threading dislocations can be further reduced to about 100 to 1000 times in accordance with the present invention. In the case of a base layer in which the buffer layer and the group III nitride compound semiconductor layer are formed in two or more periods, when each group III nitride compound semiconductor layer is doped with an element having a larger atomic radius than the main constituent element, good. In the case where the light emitting device is configured as a light emitting device, a binary system of a group III nitride-based compound semiconductor,
Alternatively, it is desirable to use a ternary system.

When forming an n-type group III nitride compound semiconductor layer, Si, Ge, Se, Te,
A group IV element or a group VI element such as C can be added. Examples of p-type impurities include Zn, Mg, Be, Ca, Sr, and Ba.
A Group IV element or a Group IV element can be added. These may be doped with plural or n-type impurities and p-type impurities in the same layer.

As the lateral epitaxial growth, it is preferable that the growth surface is perpendicular to the substrate, but it is also possible to grow the crystal while keeping the facet surface oblique to the substrate.

In the lateral epitaxial growth, it is more preferable that at least the upper part of the lateral epitaxial growth surface and the substrate surface are perpendicular to each other, and it is more preferable that all of them are {11-20} planes of a group III nitride compound semiconductor. Is more desirable.

When the crystal axis direction of the group III nitride-based compound semiconductor layer laminated on the substrate can be predicted, the a-plane ({11-20} plane) or the m-plane (｛ It is useful to perform masking or etching in a stripe shape so as to be perpendicular to the (1-100 ° plane). The stripes and the mask may be arbitrarily designed in an island shape, a lattice shape, or the like. The lateral epitaxial growth surface may be a growth surface that is perpendicular to the substrate surface or a growth surface that is oblique to the substrate surface. To make the (11-20) plane the lateral epitaxial growth plane as the a-plane of the group III nitride compound semiconductor layer, for example, the longitudinal direction of the stripe is the m plane of the group III nitride compound semiconductor layer (1-100). ) Perpendicular to the plane. For example, when the substrate is the a-plane or the c-plane of sapphire, in both cases, the m-plane of sapphire is formed thereon.
Since it usually coincides with the a-plane of the group I nitride-based compound semiconductor layer, etching is performed accordingly. Also in the case of a point-like, lattice-like, or other island-like shape, it is preferable that each surface forming the contour (side wall) is a {11-20} plane.

The etching mask is made of polycrystalline silicon or polycrystalline silicon.
Polycrystalline semiconductors such as crystalline nitride semiconductors, silicon oxide (SiO_x),
Silicon nitride (SiN_x), Titanium oxide (TiO_X), Zirconium oxide
(ZrO _X), Oxides, nitrides, titanium (Ti), tungsten
High melting point metal such as (W)
Can be. These film forming methods include vapor deposition, sputtering, CV
Any method other than the vapor phase growth method such as D can be used.

When performing etching, reactive ion etching (RIE) is desirable, but any etching method can be used.

It has a region where the above threading dislocation is suppressed.
Semiconductor elements such as FETs and light-emitting elements can be formed over the entire group III nitride-based compound semiconductor or over a region where threading dislocations are suppressed. In the case of a light-emitting element, the light-emitting layer may have a homo-structure, a hetero-structure, or a double-hetero structure in addition to a multiple quantum well structure (MQW) and a single quantum well structure (SQW). May be formed.

The above-described group III nitride compound semiconductor having a region in which threading dislocation is suppressed is removed by removing, for example, a substrate 1, a buffer layer 2, and a portion where a step is formed in which a step is formed by etching to prevent threading dislocation. And a group III nitride-based compound semiconductor substrate. A group III nitride compound semiconductor element can be formed thereon, or can be used as a substrate for forming a larger group III nitride compound semiconductor crystal. The removal method is optional in addition to the mechanochemical polishing.

Hereinafter, a description will be given based on specific embodiments of the present invention. Although a light-emitting device will be described as an example, the present invention is not limited to the following example, and discloses a method of manufacturing a group III nitride compound semiconductor applicable to any device.

The group III nitride compound semiconductor of the present invention is:
It was manufactured by vapor phase growth by metal organic compound vapor phase epitaxy (hereinafter referred to as “MOVPE”). The gases used were ammonia (NH ₃ ), carrier gas (H ₂ or N ₂ ), trimethylgallium (Ga (CH ₃ ) ₃ , hereinafter referred to as “TMG”) and trimethylaluminum (Al (CH ₃ ) ₃ , Hereinafter, referred to as “TMA”, trimethylindium (In (CH ₃ ) ₃ , hereinafter referred to as “TMI”), cyclopentadienyl magnesium (Mg (C
₅ H _{5) 2,} which is hereinafter referred to as "Cp ₂ Mg").

[First Embodiment] In this embodiment, as shown in FIG.
Buffer layer 2 and group III nitride compound semiconductor layer 31
Used as basal layer. Organic cleaning and heat treatment
A-plane as a main surface, and a single crystal sapphire substrate 1
Temperature to 400 ° C_Two10L / min, NH _Three5L / mi
n, supply TMA at 20 μmol / min for about 3 minutes
The buffer layer 2 was formed to a thickness of about 40 nm. Next, sapphire
A) Keep the temperature of the substrate 1 at 1000 ° C_Two20L / min, like this
And a buffer layer 2 made of AlN having a thickness of about 40 nm
A base layer composed of a 1.5 μm GaN layer 31 was formed (see FIG. 1).
(A)).

Next, reactive ion etching (R
IE) and the buffer layer 2 and the GaN layer 31 having a thickness of about 1.5 μm
And the sapphire substrate 1 with a width of 10 μm
m, an interval of 10 μm, and a depth of 1.7 μm were formed in stripes. As a result, the upper stage having a width of 10 μm and the lower stage (bottom) of the concave portion of the sapphire substrate 1 having a depth of 0.2 μm were alternately formed (FIG. 1B). At this time, the side surface on which a step having a depth of 1.5 μm was formed was the {11-20} surface of the GaN layer 31. Then, maintaining the temperature of the sapphire substrate 1 to 1150 ° C., the H ₂ 20
L / min, NH ₃ at 10 L / min, TMG at 5 μmol / min, GaN
The layer 32 was formed by lateral epitaxial growth (FIG. 1C). With the base layer formed on the upper surface of the step as a nucleus, the upper part of the lower part of the step, which is the concave part of the sapphire substrate 1, was covered by lateral epitaxial growth, and the surface became flat (FIG. 1 (d)). Thereafter, the H ₂ 20L / mi
n and NH ₃ were introduced at 10 L / min and TMG at 300 μmol / min to grow the GaN layer 32, and the GaN layer 32 was made 3 μm thick. In the portion of the GaN layer 32 formed above the recess having a depth of 0.2 μm of the sapphire substrate 1, threading dislocations were significantly suppressed as compared with the portion formed above the upper surface of the step.

Second Embodiment In this embodiment, a buffer layer and a single crystal group III nitride compound semiconductor layer as shown in FIG. 2 are used as one cycle, and a layer formed in multiple cycles is used as a base layer. The temperature was lowered to 400 ° C., H ₂ was 10 L / min, NH ₃ was 5 L / min, and TMA was 20 μmol on the single crystal sapphire substrate 1 with the a-plane cleaned by organic cleaning and heat treatment as the main surface.
The first AlN layer 211 was formed to a thickness of about 40 nm by supplying at about / min for about 3 minutes. Next, the temperature of the sapphire substrate 1 is set to 1000 ° C.
Held in, 300 [mu] mol of H ₂ 20L / min, the NH ₃ 10L / min, and TMG
/ min to form a GaN layer 212 having a thickness of about 0.3 μm. Next, the temperature was lowered to 400 ° C., and H ₂ was reduced to 10 L / min, NH
₃ at 5 L / min and TMA at 20 μmol / min for about 3 minutes
The AlN layer 213 was formed to a thickness of about 40 nm. Further, the temperature of the sapphire substrate 1 is maintained at 1000 ° C., H ₂ is 20 L / min, NH ₃
Was introduced at 10 L / min and TMG at 300 μmol / min.
Was formed. Thus, the first film having a thickness of about 40 nm
AlN layer 211, GaN layer 212 with a thickness of about 0.3 μm,
A base layer 20 composed of a second AlN layer 213 having a thickness of nm and a GaN layer 31 having a thickness of about 1.5 μm was formed (FIG. 2A).

Next, similarly to the first embodiment, a step was formed by RIE (FIG. 2B). The depth of the concave portion of the sapphire substrate 1 was 0.2 μm. Next, the temperature of the sapphire substrate 1 was maintained at 1150 ° C., H ₂ was 20 L / min, NH ₃ was 10 L / min, T
MG was introduced at a rate of 5 μmol / min, and a GaN layer 32 was formed by lateral epitaxial growth (FIG. 2C). With the base layer 20 formed on the upper surface of the step as a nucleus in this manner, the lower upper portion of the step, which is a concave portion of the sapphire substrate 1, was covered by lateral epitaxial growth, and the surface became flat (FIG. 2).
(D)). Thereafter, the H ₂ 20L / min, the NH ₃ 10L / min, T
Introducing MG at 300 μmol / min, growing the GaN layer 32,
Layer 32 was 3 μm thick. In the portion of the GaN layer 32 formed above the recess having a depth of 0.2 μm of the sapphire substrate 1, threading dislocations were significantly suppressed as compared with the portion formed above the upper surface of the step.

[Third Embodiment] The third embodiment is formed in the same manner as the first embodiment.
The laser diode shown in FIG.
An LD (LD) 100 was formed. However, the shape of the GaN layer 32
During formation, silane (SiH _Four) To introduce GaN layer 32
The layer was made of n-type GaN doped with con (Si). In addition,
For simplicity, a sapphire substrate 1 having a concave
GaN layer 31 and GaN layer at the same height
32 together with wafer 1000, and other Ga
The N layer 32 is described as a GaN layer 103.

A wafer layer 1000 comprising an sapphire substrate having a recess, a buffer layer made of AlN, a GaN layer 31 and an n-type GaN layer 32 at the same height as the GaN layer 31 and the n-type GaN layer 1
03, an n-cladding layer 104 made of silicon (Si) doped Al _0.08 Ga _0.92 N, an n guide layer 105 made of silicon (Si) doped GaN, a light emitting layer 106 having an MQW structure, and a magnesium (Mg) doped GaN P guide layer 107,
A p-cladding layer 108 made of magnesium (Mg) -doped Al _0.08 Ga _0.92 N and a p-contact layer 109 made of magnesium (Mg) -doped GaN were formed. Next, an electrode 110A made of gold (Au) is formed on the p-contact layer 109 by two steps of Ga.
An electrode 1 made of aluminum (Al) is partially etched until a total of three stages of the GaN layer 103 including the N layer and the n-type GaN layer are exposed.
10B was formed. The laser diode (LD) formed in this way has remarkably improved device life and luminous efficiency.

Fourth Embodiment A light emitting diode (LED) as shown in FIG. 4 is formed on a wafer formed in the same manner as in the third embodiment.
200 was formed as follows. In order to simplify the drawing, a sapphire substrate 1 having a concave portion and a buffer layer 2,
The GaN layer 31 and the GaN layer 32 at the same height as those are described as a wafer 2000, and the other GaN layers 32 are
Described as aN layer 203.

On a wafer 2000 composed of a sapphire substrate, a buffer layer composed of AlN, a GaN layer 31 and a GaN layer 32 at the same height as the above, and an n-type GaN layer 203, a silicon (Si) -doped Al _0.08 Ga _0.92 N N cladding layer 2 made of
04, light emitting layer 205, magnesium (Mg) doped Al _0.08
P-cladding layer 206 made of Ga _0.92 N, magnesium (M
g) A p-contact layer 207 made of doped GaN was formed. Next, an electrode 208A made of gold (Au) is partially etched on the p-contact layer 207 until a two-stage GaN layer 203 of a GaN layer and an n-type GaN layer is exposed to form an electrode 208B made of aluminum (Al). Formed. The light emitting diode (LED) formed in this way has significantly improved element life and luminous efficiency.

Fifth Embodiment In this embodiment, a silicon (Si) substrate is used as a substrate. n-type silicon (Si) substrate 301
At a temperature 1150 ° C. above the H ₂ 10L / min, the NH ₃ 10L / min, and TMG
0.86pp 100μmol / min, the TMA 10 .mu.mol / min, with H ₂ gas
supply silane (SiH ₄ ) diluted to 0.2 μmol / min,
A layer 3021 made of silicon (Si) doped Al _0.15 Ga _0.85 N with a thickness of 1.5 μm was formed (FIG. 5A). Next, by using a hard bake resist mask, selective dry etching using reactive ion etching (RIE) was performed to form a stripe having a width of 10 μm, an interval of 10 μm, and a depth of 1.7 μm. As a result, the upper part of the width of 10 μm and the depth
The lower part (bottom part) of the concave part of the silicon substrate 3 of 0.2 μm was formed alternately (FIG. 5B). At this time, the side surface on which the step having a depth of 1.5 μm was formed was the {11-20} plane of the n-Al _0.15 Ga _0.85 N layer 3021. Next, the temperature of the silicon substrate 301 was maintained at 1150 ° C., H ₂ was 20 L / min, NH ₃ was 10 L / min, and TMG was
The 5 [mu] mol / min, TMA and 0.5μmol / min, H ₂ silane diluted by gas (SiH ₄₎ was supplied with 0.01μmol / min, the silicon substrate stepped in the upper and side surfaces of n-Al _0.15 Ga _0.85 N The layers were grown vertically and horizontally (FIG. 5 (c)). Thus over the substrate recess is covered mainly by lateral epitaxial growth of the upper surface core, after the surface has a flat, H ₂
10 L / min, NH ₃ 10 L / min, TMG 100 μmol / min, TMA 1
0μmol / min, silane diluted with H ₂ gas (SiH ₄₎ 0.
Supply at 2 μmol / min, grow n-Al _0.15 Ga _0.85 N layer, 3
The thickness was set to μm (FIG. 5 (d)). Hereinafter, the silicon substrate 301 having the concave portion and the n-Al _0.15 Ga _0.85 N layer 302 are collectively referred to as a wafer 3000.

As described above, the wafer 3000 (the silicon substrate 301 having the concave portion and the n-Al _0.15 Ga
_0.85 N layer 302), an n guide layer 303 made of silicon (Si) doped GaN, a light emitting layer 304 having an MQW structure, a p guide layer 305 made of magnesium (Mg) doped GaN, a magnesium (Mg) doped Al _0.08 A p-cladding layer 306 made of Ga _0.92 N and a p-contact layer 307 made of magnesium (Mg) -doped GaN were formed. Next, an electrode 308A made of gold (Au) is formed on the p-contact layer 307, and an electrode 308B made of aluminum (Al) is formed on the back surface of the silicon substrate 301.
Was formed. The laser diode (LD) 300 of FIG. 6 formed in this manner has significantly improved device life and luminous efficiency.

Sixth Embodiment In this embodiment, a silicon (Si) substrate was used as a substrate. The n-Al _0.15 Ga _0.85 N layer 30 formed on the silicon substrate 301 having the concave portion according to the fifth embodiment.
2, a wafer 400 of a silicon substrate 401 having a concave portion and an n-Al _0.15 Ga _0.85 N layer 402 formed thereon.
0, light emitting layer 403, magnesium (Mg) -doped
A p-cladding layer 404 made of Al _0.15 Ga _0.85 N was formed. Next, an electrode 4 made of gold (Au) is formed on the p-cladding layer 404.
05A, aluminum (Al)
Was formed. The light emitting diode (LED) 400 of FIG. 7 formed in this manner has significantly improved element life and luminous efficiency.

[Modification of Etching] FIG. 8 shows an example in which an upper step of an island is formed by three sets of {11-20} planes. FIG. 8A also shows the outer periphery formed by three sets of {11-20} planes, but this is a simplified schematic diagram for understanding, and is actually an island-shaped step. The upper stage may form tens of millions per wafer. In FIG. 8A, the bottom B of the step has three times the area of the top of the island-shaped step. In FIG. 8B, the bottom B of the step has an area eight times that of the top of the island-shaped step.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a group III nitride compound semiconductor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of a group III nitride compound semiconductor according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing the structure of a group III nitride compound semiconductor light emitting device according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a group III nitride compound semiconductor light emitting device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of a group III nitride compound semiconductor according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a structure of a group III nitride compound semiconductor light emitting device according to a fifth embodiment of the present invention.

FIG. 7 is a sectional view showing a structure of a group III nitride compound semiconductor light emitting device according to a sixth embodiment of the present invention.

FIG. 8 is a schematic view showing another example of etching the first group III nitride compound semiconductor.

FIG. 9 is a cross-sectional view showing threading dislocations propagating through a group III nitride compound semiconductor.

[Explanation of symbols]

 1, 101, 201, 301, 401 Substrate 2, 102, 202 Buffer layer 20 Base layer 21 First buffer layer forming base layer 22 Intermediate layer forming base layer 23 Second buffer layer forming base layer 31 1 group III nitride compound semiconductor (layer) 32 second group III nitride compound semiconductor (layer) 103, 203 n-GaN layer 104, 204, 302, 402 n-AlGaN cladding layer 105, 303 n- GaN guide layers 106, 205, 304, 403 Emitting layers 107, 305 p-GaN guide layers 108, 206, 306, 404 p-AlGaN cladding layers 109, 207, 307 p-GaN layers 110A, 208A, 308A, 405A p-electrodes 110B, 208B, 308B, 405B n-electrode

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshio Hiramatsu 1 Ochiai Nagahata, Kasuga-cho, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyoda Gosei Co., Ltd. Toyoda Gosei Co., Ltd.

Claims (6)

[Claims] 1. A method for producing a group III nitride compound semiconductor on a substrate, wherein the group III nitride compound semiconductor is obtained by epitaxial growth, the method comprising: forming at least one layer of a group III nitride compound semiconductor; Forming a base layer to be a group III nitride compound semiconductor on the substrate; etching the base layer and at least a portion of the substrate surface to form an island state such as a dot, stripe, or lattice Providing a step between the upper layer where the base layer is formed on the substrate surface and the lower step which is a concave portion of the substrate surface where the base layer is not formed; and a dot-like or stripe formed by the etching. Vertically and laterally epitaxially growing a second group III nitride-based compound semiconductor with the upper surface and side surfaces of the upper step of the base layer in an island state such as a lattice shape or a lattice shape as nuclei. And a method for producing a group III nitride compound semiconductor. 2. The side surface of the step is substantially entirely 11-2.
The method for producing a group III nitride-based compound semiconductor according to claim 1, wherein the plane is a 0 ° plane. 3. The semiconductor device according to claim 1, wherein the first group III nitride compound semiconductor and the second group III nitride compound semiconductor have the same composition.
A method for producing a group I nitride compound semiconductor. 4. A portion of the III-nitride compound semiconductor layer produced by the method for producing a III-nitride compound semiconductor according to claim 1, wherein the portion of the III-nitride compound semiconductor layer is laterally epitaxially grown. A group III nitride compound semiconductor device formed in an upper layer. 5. A portion of the group III nitride-based compound semiconductor layer produced by the method for producing a group III nitride-based compound semiconductor according to claim 1, wherein the portion of the group III nitride-based compound semiconductor layer is laterally epitaxially grown. A group III nitride compound semiconductor light-emitting device obtained by laminating different group III nitride compound semiconductor layers on an upper layer. 6. In addition to the method of manufacturing a group III nitride-based compound semiconductor according to any one of claims 1 to 3, by removing substantially all but the upper layer of the laterally epitaxially grown portion. A method for producing a group III nitride compound semiconductor substrate, comprising obtaining the group III nitride compound semiconductor substrate.