JP2001339070A - Tft array and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of PEPs, improve throughput, and reduce the cost by simultaneously implanting impurities into a capacity region and each region of the source and drain of each N-type and P-type TFT, by utilizing features that an original impurity conductivity-type stays even if an opposing impurity is implanted into an already implanted impurity region in the manufacturing process of a TFT array. SOLUTION: A polysilicon layer 2 is patterned to a P-channel TFT region 11, an N-channel TFT region 12, and a capacity region 10 on a glass substrate 1, a gate oxide film 3 is formed on it, resist is patterned to all of the P-channel TFT region 11 and on the gate region of the N-channel TFT region 12, P6 is subjected to ion doping with the resist as a mask, the resist is removed, then gate metal is patterned to the gate part of the P-channel TFT region 11, the channel region of the N-channel TFT region 12, and the capacity region 10 for generation, an opposing impurity B7 is ion-doped with the gate metal as a mask to manufacture the TFT array, thus eliminating a PEP process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a TFT array, and more particularly to a TFT including a light-transmitting non-single-crystal silicon layer such as polysilicon or amorphous silicon.
The present invention relates to an array manufacturing process.

[0002]

2. Description of the Related Art In recent years, a high-definition LCD and a driving circuit integrated type LCD in which peripheral circuits for driving the LCD are formed on the same substrate.
In order to manufacture semiconductor devices, a technique for integrating elements on a transparent insulating substrate such as glass or quartz using light-transmitting polysilicon (polycrystalline silicon) as a channel layer has been studied.

In particular, a TFT having a CMOS structure utilizing both P-type and N-type conduction channels tends to be used as a driving circuit of an LCD in order to reduce power consumption.

[0004] In addition, reducing the number of external peripheral elements and integrating the elements on an array substrate is a key point from the viewpoint of cost reduction.

However, when an analog circuit is integrated, it is necessary to form a capacitance region in the analog circuit separately from the auxiliary capacitance region conventionally used for each pixel.
In this case, it is important that the capacitance is not changed by the applied voltage. In general, a polysilicon having a structure in which impurities are implanted at a high concentration is used.

However, when implanting high-concentration impurities, it is necessary to selectively implant necessary impurities into the capacitor region before forming a gate metal serving as an electrode in the TFT region or the capacitor region. PEP step is required.

[0007]

As described above, in a polysilicon TFT array in which peripheral circuits are integrated, in addition to the N-type TFT and the P-type TFT, a capacitor region requiring stable electric characteristics is required. In the manufacturing process,
Prior to forming the gate metal, it is necessary to selectively implant high-concentration impurities, so that at least one PEP step as a pre-process for impurity implantation into the capacitance region is increased at least once, leading to a decrease in throughput and an increase in cost. There was a problem.

The present invention solves the above-mentioned problems of the prior art, and in the process of manufacturing a TFT array, even if a subsequent impurity is implanted into an already implanted impurity region, the original impurity region remains unchanged. Taking advantage of the feature that the impurity conductivity is maintained, the PEP is simultaneously implanted into the capacitor region and the source and drain regions of the N-type and P-type TFTs.
It is an object of the present invention to provide a method for manufacturing a TFT array, in which the number can be reduced, the throughput can be improved, and the cost can be reduced.

[0009]

In order to achieve the above object, the present invention provides a first TFT region, a second TFT region,
A first process of forming non-single-crystal silicon in a capacitor region and forming a gate oxide film on each region, and a first TFT
A second process of forming a resist over the entire region, which is to be a channel of the second TFT region, and a third process of doping a first impurity using the resist as a mask.
Removing the resist, and removing the first TF
A fourth process of forming a gate on the gate portion of the T region, the gate portion of the second TFT region, and the capacitor region; and a second process of a conductivity type opposed to the first impurity using the gate as a mask. And a fifth process for doping impurities.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. FIG. 1 is a graph showing T in Embodiment 1 of the present invention.
FIG. 4 is a process explanatory diagram of a method of manufacturing an FT array, particularly a capacitor region and an N-channel / P-channel coplanar TFT
FIG. 3 is a cross-sectional view of a device in a manufacturing step of FIG.

First, as shown in FIG. 1A, an a-Si (amorphous silicon) layer serving as an active region is formed on a glass substrate 1 and excimer laser annealing is performed.
This a-Si layer is polycrystallized to form a polysilicon layer 2.

Subsequently, through a first PEP process, a P-channel TFT region 11 and an N-channel TFT region 1 are formed.
2. Pattern the capacitance region 10;

Next, a gate oxide film 3 is formed on the whole, and a resist 5 is covered thereon. Subsequently, the resist 5 is patterned through a second PEP process. The resist 5 covers the entire P-channel TFT region 11 and the channel region of the N-channel TFT region 12.

Next, using the resist 5 as a mask, PH
P (phosphorus) 6 as an impurity is implanted by ion doping with a mixed gas of ₃ / H ₂ .

As a result, the polysilicon layer 2 in the source and drain regions of the N-channel TFT region 12 and the entire region of the capacitor region 10 becomes an N-type doped with a large amount of P.

Subsequently, after the resist 5 is peeled off, FIG.
As shown in (B), a metal layer serving as a gate metal is formed on the whole and patterned by a third PEP to form a gate region of the P-channel TFT region 11 and an N-channel TF.
The gate metal 4 is formed in the gate region of the T region 12 and the capacitance region 10.

Next, using the gate metal 4 as a mask, B
_By ion doping with a mixed gas of ₂ H ₆ / H ₂ , P
B (boron) 7, which is an impurity opposite to 6, is implanted.

As a result, the polysilicon layer 2 in the source and drain regions of the P-channel TFT region 11 becomes a P-type doped with a large amount of B, and the N-channel TFT region 12
Of the source, drain and capacitor regions 10 which do not correspond to the gate metal 4 are N-type. That is,
The source / drain region and the capacitance region 10 of the N-channel TFT region 12 are already N-type, and conditions are set so that even if an impurity B7 corresponding thereto is added, the original N-type impurity conductivity type is maintained. Set.

Subsequently, as shown in FIG. 1C, a P-channel TFT region 11, an N-channel TFT region 12,
An interlayer film 8 is formed on each element of the capacitance region 10, and a fourth film is formed at a position corresponding to the source region and the drain region of the P-channel TFT region 11 and the N-channel TFT region 12 and at an appropriate position of the capacitance region 10. The contact hole 13 is formed by patterning with PEP, the signal line 9 is formed and patterned, and a TFT array is completed by forming a passivation film.

According to the above-described method, it is possible to make the gate metal processing in a total of three PEP steps. The implantation of P6 in the first ion doping is
Compensation is performed by implanting B7 in the second ion doping, but ion doping conditions are selected so that the N-type properties do not change. This condition is specifically as follows.

The amount of B in polysilicon <the amount of P in polysilicon X (1/2)
In the case of 2, if the gate metal is processed wider than the resist 5, a so-called gate overlap structure is obtained.

Embodiment 2 FIG. FIG. 2 is a graph showing T in Embodiment 2 of the present invention.
FIG. 4 is a process explanatory diagram of a method of manufacturing an FT array, particularly a capacitor region and an N-channel / P-channel coplanar TFT
FIG. 3 is a cross-sectional view of a device in a manufacturing step of FIG.

First, as shown in FIG. 2A, an a-Si layer serving as an active region is formed on a glass substrate 1, and the a-Si layer is polycrystallized by excimer laser annealing. The polysilicon layer 2 is used.

Subsequently, through a first PEP process, a P-channel TFT region 11 and an N-channel TFT region 1 are formed.
2. Pattern the capacitance region 10;

Next, a gate oxide film 3 is formed on the entire surface, and a resist 5 is covered thereon. Subsequently, the resist 5 is patterned through a second PEP process. As a result of this patterning, the entire P channel TFT region 11 and the channel region of the N channel TFT region 12 are masked.

Next, using the resist 5 as a mask, PH
Injecting P6 as an impurity by ion doping by mixed gas of _{3 /} H _2.

As a result, the entire polysilicon layer 2 of the source / drain region of the N-channel TFT region 12 and the capacitance region 10 becomes N-type.

Subsequently, after the resist 5 is peeled off, FIG.
As shown in (B), a metal layer serving as a gate metal is formed on the whole and patterned by a third PEP to form a gate region of the P-channel TFT region 11 and an N-channel TF.
A gate metal 4 is formed in each of the gate region and the capacitance region 10 in the T region 12.

Next, using the gate metal 4 as a mask,
Ion doping with a mixed gas of ₂ H ₆ / H ₂ ,
The impurity B7 opposite to the impurity 6 is implanted.

As a result, the polysilicon layer 2 of the source / drain region of the P-channel TFT region 11 becomes P-type, and the source / drain region of the N-channel TFT region 12 and the portion not corresponding to the gate metal 4 of the capacitance region 10. Remain N-type. That is, N channel T
Source / drain region and capacitance region 1 of FT region 12
0 is already N-type, and the impurity B
Even if 7 is added, the condition is set such that the original N-type impurity conductivity type remains unchanged.

Subsequently, as shown in FIG. 1C, a P-channel TFT region 11, an N-channel TFT region 12,
An interlayer film 8 is formed on each element in the capacitance region 10.

Subsequently, the positions of the P-channel TFT region 11 corresponding to the source and drain regions and the N-channel TF
A contact hole 13 is formed by patterning with a fourth PEP at a position corresponding to the source and drain regions of the T region 12 and at a proper position of the capacitance region 10.

Next, P is added to the opening of the contact hole 13.
P is implanted by ion doping with a mixed gas of H ₃ / H ₂ . This is performed to reduce the contact resistance of the N-type TFT.

Finally, as shown in FIG. 1D, the signal line 9 is formed and patterned, and a passivation film is formed to complete the TFT array.

By the method described above, up to a total of three PEP steps can be made up to gate metal processing. The implantation of P6 in the first ion doping is
Compensation is performed by implanting B7 in the second ion doping, but ion doping conditions are selected so that the N-type properties do not change. This condition is specifically as follows.

The amount of B in polysilicon <the amount of P in polysilicon X (1/2) The N channel TFT region 1
In the case of 2, if a gate metal is processed wider than the resist 5, a so-called gate overlap structure is obtained.

In the first and second embodiments,
The case where P6 is implanted in the first ion doping and B7 is implanted in the second ion doping is exemplified.
B7 may be ion-doped the second time, and P6 may be ion-doped the second time. In this case, in the second patterning of the resist 5 by the PEP process, the channel region of the P-channel TFT region 11 and the N-channel TFT
The entire area 12 is masked.

When the implantation order of the impurity ion doping is reversed, the capacitance region 10 becomes P-type, and the P-channel TFT region 11 can have a gate overlap structure.

In the above embodiment, the case where polysilicon is used as the non-single-crystal silicon is exemplified. However, it goes without saying that the present invention can be similarly applied to amorphous silicon as well as polysilicon.

[0041]

As described above, in the method of manufacturing a TFT array according to the present invention, the P-type TFT, the N-type TFT, and the polysilicon layer in each of the capacitor regions are formed (first PEP).
To form a resist serving as a mask for ion-doping P or B in these regions (second PEP), and to form a gate in each region and ion-dope B or P in each region. (3rd PEP) In order to form a gate metal to be used as a mask, up to the gate is formed by three PEPs, so that the PEP process can be reduced, the throughput is improved, and the This has the effect of realizing cost reduction.

[Brief description of the drawings]

FIG. 1 is a process explanatory diagram illustrating a method for manufacturing a TFT array according to a first embodiment of the present invention.

FIG. 2 is a process diagram illustrating a method for manufacturing a TFT array according to a second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 glass substrate 2 polysilicon layer 3 gate oxide film 4 gate metal 5 resist 6 P 7 B 8 interlayer film 9 signal line 10 capacitance region 11 P-channel TFT region 12 N-channel TFT region 13 contact hole

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[Procedure amendment]

[Submission date] August 28, 2001 (2001.8.2
8)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Patent application title: TFT array and method of manufacturing the same

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/06 H01L 27/06 102A 21/8238 27/08 321Z 27/092 29/78 616V 27/08 331 616L 21/336 F term (reference) 2H092 GA59 GA60 JA24 JA25 JA34 JA37 JA46 JB56 JB62 KA04 KA05 KA10 KB25 MA13 MA15 MA18 MA27 MA30 MA37 MA41 NA25 NA27 NA29 5C094 AA22 AA43 AA44 AA48 AA53 BA03 BA01 DB01 DA01 FA03 FB02 FB12 FB14 FB15 FB20 GB10 5F048 AA09 AB10 AC03 AC10 BA16 BB09 BC06 BE08 BG05 5F110 AA16 BB02 BB04 CC02 DD02 GG02 GG13 GG15 HJ01 HJ04 HJ12 NN02 NN72 PP03 QQ10

Claims (5)

[Claims] 1. A first process in which non-single-crystal silicon is formed in a first TFT region, a second TFT region, and a capacitance region, and a gate oxide film is formed on each region; A second process of forming a resist on the entire region and a region serving as a channel of the second TFT region, a third process of doping a first impurity using the resist as a mask, and removing the resist. A fourth process of forming a gate on the gate portion of the first TFT region, a gate portion of the second TFT region, and the capacitor region; and opposing the first impurity using the gate as a mask. And a fifth process of doping a second impurity of a conductivity type. 2. The method according to claim 1, wherein said first TFT is a P-channel, said second TFT is an N-channel, said first impurity is P, and said second impurity is B. . 3. The method of manufacturing a TFT array according to claim 1, wherein said first TFT is an N channel, said second TFT is a P channel, said first impurity is B, and said second impurity is P. . 4. An interlayer film is formed after the fifth process,
A sixth process of forming contact holes at positions respectively corresponding to the source and drain portions of the first TFT region, the source and drain portions of the second TFT region, and a part of the capacitance region; And a seventh process of doping the non-single-crystal silicon of each region with a third impurity through the process.
Array manufacturing method. 5. The method according to claim 5, wherein said third impurity is the same as said first impurity.