JP2001332638A - Manufacturing method of semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve operation speed by providing a source/drain region and a trench isolation structure formed by self-alignment and restraining increase of source/drain resistance. SOLUTION: The method comprises a process for forming a cell gate 104 on a semiconductor substrate 101; a process for forming sidewall 106 in a side wall of a cell gate, forming a trench groove 107 in the semiconductor substrate 101 by self-alignment by using the sidewall 106, forming a thermal oxide film 108 in an inner surface thereof, and further forming a trench isolation structure by filling up the trench groove 107 with an oxide film 109; and a process for removing the sidewall 106 and forming a source/drain region by implantation of impurities to a semiconductor substrate in the removed region. As a result it is possible to prevent the thickness of the thermal oxide film 108 in an inner wall of a trench groove from increasing abnormally in a region in contact with a source/drain region, thus reducing the width size of a source/drain region and to prevent source/drain resistance from increasing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a flash memory which requires high integration, and more particularly to a method of manufacturing a semiconductor memory device having a trench element isolation structure for element isolation.

[0002]

2. Description of the Related Art In a flash memory as one of semiconductor memory devices, it is one of the important elements to form a cell structure and an element isolation structure having a high dimensional accuracy. For this reason, a trench element isolation structure that can be made finer than a LOCOS element isolation structure is employed as an element isolation structure. In order to manufacture this trench element isolation structure, for example, Japanese Unexamined Patent Application Publication No. 10-289990 discloses that a semiconductor substrate is etched using a photoresist mask to form a trench, and an insulating isolation material is buried in the trench. A technique for forming a trench element isolation structure is described. However, in this technique, since the gate electrode (cell gate) of the memory cell is formed after the formation of the trench element isolation structure, the alignment between the trench and the cell gate is required, and the manufacturing becomes complicated.
That is, if the alignment between the trench and the cell gate is biased, the width dimension of the source / drain regions formed on both sides of the cell gate is biased, and the source / drain resistance is varied.

On the other hand, in recent years, a technique of forming a trench isolation structure by self-alignment has been proposed. Because this technology does not use a photoresist mask,
It is not necessary to align the trench with the cell gate, and a trench isolation structure with less displacement can be efficiently formed. This technology is, for example, T. Kobayas
hi, et al., Tech. Dig. IEDM (1997) 275 and the like.

FIG. 4 shows a method of manufacturing a flash memory according to the prior art for forming a trench isolation structure by such a self-alignment in the order of steps. First, in FIG. 4A, a tunnel oxide film 202 having a predetermined thickness, a first polysilicon layer 203 serving as a first floating gate, and a thin oxide film 20 are formed on a silicon substrate 201.
4. Polycrystalline silicon layer 205 for spacer, oxide film 20
5 ′ are sequentially laminated. Then, etching is performed by a photolithography method to form a gate electrode 206 having a predetermined shape.
To form Further, a source / drain region 207 is formed by introducing impurities of a predetermined concentration into the silicon substrate 201 by ion implantation, and a CVD oxide film is formed on the entire surface. Then, the CVD oxide film is anisotropically etched. A sidewall 208 is formed on the side surface of the gate electrode 206. Next, as shown in FIG. 4B, using the sidewall 208 as a mask, the silicon substrate 201 is used.
Is etched to form trench grooves 209 on both sides of the gate electrode 206.

Next, as shown in FIG. 4C, the side walls of the gate electrode 206 and the trench 209 are covered with a thin CVD oxide film 210, and then a BPSG film 211 is deposited.
The gate electrode 206 and the trench 209 are
It is buried with a G film 211. As a result, a trench element isolation structure 212 is formed. Further, after performing NH ₃ annealing, the BPSG film 211 is etched to expose the polycrystalline silicon layer 205 for the spacer. Next, as shown in FIG. 4D, the polycrystalline silicon layer for spacers 205 and the thin oxide film 204 thereunder are removed by dry etching. Then, by forming a second polycrystalline silicon 213 and forming it in a required pattern, the floating gate 214 is connected to the first polycrystalline silicon layer 203 and has an open shape above the sidewall 208. To form Finally, FIG.
As shown in FIG.
An oxide film 215, a control gate polycrystalline silicon film 216, and a WSi film 217 are sequentially formed, and these are formed in a required pattern to form a cell structure.

[0006]

In a flash memory manufactured by such a conventional technique, the manufacturing process of the trench isolation structure 212 is performed by using the source / drain region 2.
07, that is, after the step of introducing impurities into the silicon substrate 201 by ion implantation or the like. For this reason, for example, in the step shown in FIG.
9 is formed as a thin thermal oxide film by thermal oxidation, when the thermal oxidation of the thermal oxide film is performed, the accelerated oxidation is performed by the high-concentration impurities contained in the source / drain regions 207. As a result, the thickness of the thermal oxide film on the upper opening side of the trench groove 209 adjacent to the source / drain region 207 partially increases. For this reason, the width of the source / drain region is reduced by an amount corresponding to the increase in the thickness of the thermal oxide film, thereby causing a problem that the source / drain resistance is increased. The effect of the increase in the source / drain resistance on the operation speed of the flash memory becomes remarkable as the miniaturization of memory cells progresses.

An object of the present invention is to provide a source / drain region and a trench element isolation structure formed in a self-aligned manner with high dimensional accuracy, and to improve the operation speed by suppressing an increase in source / drain resistance. An object of the present invention is to provide a method for manufacturing a semiconductor memory device.

[0008]

According to a method of manufacturing a semiconductor memory device of the present invention, a step of forming a cell gate on a semiconductor substrate, a step of forming a side wall on a side wall of the cell gate, and the step of forming the semiconductor using the side wall Forming a trench in the substrate in a self-aligned manner, thermally oxidizing an inner surface of the trench to form a thermal oxide film, and burying the trench to form a trench isolation structure; The method is characterized by including a step of removing a wall and injecting an impurity into the semiconductor substrate in a region where the wall is removed to form a source / drain region.
In particular, according to the present invention, a source / drain region extending in a column direction is a bit line, a control gate electrode extending in a row direction is a word line, and a cell gate is periodically arranged directly below the word line. Applied to manufacture of flash memory.

According to the present invention, since the impurity for forming the source / drain regions is introduced after the formation of the trench element isolation structure, the thermal oxidation required at the time of forming the trench element isolation structure is not required. Is performed before the formation of the oxide film, so that accelerated oxidation due to impurities does not occur during the thermal oxidation treatment. Therefore, in the region where the oxide film on the inner wall of the trench groove is in contact with the source / drain region, the film thickness does not abnormally increase, and the width of the source / drain region does not decrease and the source / drain resistance does not increase.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B are a plan view of a flash memory according to the present invention and a cross-sectional view taken along line XX. On the silicon substrate 101, a plurality of word lines WL
Are arranged, and the memory cell MC is connected to each of the word lines W.
It is arranged in a region immediately below L and surrounded by a broken line in FIG. The memory cells MC are periodically arranged in a state where they are insulated and separated by trench element isolation structures 110 formed in a plurality of rows on the silicon substrate 101, and as shown in FIG. 102, a gate electrode 103 and a pillar electrode 115 as a floating gate, an ONO film 116 as an inter-gate insulating film are stacked, and a stacked structure of a polycrystalline silicon film 117 as the word line and a silicide wiring film 118 is formed thereon. Is formed. The channel region C of the memory cell MC
On both sides of H, bit lines BL are formed along the both sides of the trench element isolation structure 110 in the longitudinal direction of the trench. The bit line BL is connected to the source of the memory cell MC.
The source region and the drain region of the memory cell MC formed of the drain region 113 and arranged in the longitudinal direction of the trench element isolation structure 110 are mutually connected to form a NOR type memory cell array.

Here, the trench element isolation structure 110
A thermal oxide film 108 having a substantially uniform thickness is formed on the inner wall of the trench 107, and a CVD
The oxide film 109 is buried. Therefore, even in contact with the source / drain region 113 of the memory cell MC, the thickness of the thermal oxide film 108 on the inner wall of the trench groove 107 is not partially increased.
The width dimension of the drain region 113 is not reduced,
An increase in source / drain resistance is prevented.

FIG. 2 to FIG. 3 are views showing the manufacturing steps of the flash memory in order of steps, and are cross-sectional views corresponding to FIG. First, as shown in FIG. 2A, a gate oxide film 102 having a thickness of 90 °, a first polycrystalline silicon film 103, and a nitride film 103 ′ are sequentially laminated on the surface of a silicon substrate 101, and a photoresist (not shown) is formed. The nitride film 103 'and the first polycrystalline silicon film 103 are formed in a required pattern by a dry etching method using a mask, and a cell gate 104 is formed. Also, a CVD oxide film 1 is formed on the entire surface.
05 is formed to cover the gate oxide film 102 and the cell gate 104.

Next, a CVD nitride film is grown on the entire surface so as to be thicker than the cell gate 104, and the CVD nitride film is etched back by anisotropic etching, as shown in FIG. Is formed on the side wall of the nitride film. Here, the nitride film sidewall 106 is formed over a region corresponding to the source / drain region of the memory cell.
The thickness of the CVD nitride film is controlled. Further, the CVD oxide film 105 is removed by etching using the nitride film sidewall 106 as a mask.

Subsequently, as shown in FIG. 2C, the silicon substrate 101 is dry-etched by a self-alignment method using the nitride film sidewalls 106, and the nitride film sidewalls 10 on both sides of the cell gate 104 are formed.
A trench 107 having a predetermined depth and width is formed along the outer wall of No. 6. Next, as shown in FIG. 2D, a thermal oxide film 10 is formed on the inner wall of the trench 107 by a thermal oxidation method.
8 is formed. At this time, since the silicon substrate 101 facing the inner surface of the trench 107 does not have a region into which impurities are introduced at a high concentration, the thickness of the thermal oxide film 108 is uniform in the depth direction of the trench 107. It becomes something. Next, a thick CVD oxide film 109 is deposited on the entire surface to completely bury the trench groove 107 and to form the cell gate 104 and the nitride film sidewall 1.
06 is buried.

Next, as shown in FIG.
The surface of the oxide film 109 is chemically and mechanically polished (CMP method)
The cell gate 104 and the trench 1 are polished.
The unevenness caused by the shape 07 is flattened. At this time, polishing is performed until at least the nitride film 103 on the cell gate 104 is removed. Then, the flattened CVD oxide film 109 after CMP polishing is etched by wet or dry etching. The end point of the etching is set to a point at which the entire buried nitride film sidewall 106 is exposed. By this etching, the CVD on the trench 107 is performed.
The oxide film 109 is removed by etching, and the CVD oxide film 10 is removed.
9 is left buried only in the trench groove, and the trench element isolation structure 110 is formed. Next, the nitride film sidewalls 106 are dissolved and removed by wet etching using a phosphoric acid solution or the like. Since the nitride film side wall 106 is thus removed and the source / drain formation regions are opened on both sides of the cell gate 104, the concentration of N is about 1 to 5E14 [cm ⁻² ].
Type impurity, for example, arsenic, is ion-implanted into the LDD region 1;
11 is formed.

Next, a CVD oxide film is formed on the entire surface so as to cover the entire cell gate, and then the CVD oxide film is anisotropically etched, as shown in FIG. The second surface is formed by the CVD oxide film on the surface.
Is formed. This second sidewall 112 is formed thinner than the nitride film sidewall 106. Thereafter, for example, 1E15 [cm
^-2 ] N-type impurities of the above concentration, for example, arsenic are ion-implanted. Subsequently, a heat treatment for activating impurities at a predetermined temperature is performed to form a high-concentration region in a region interposed between the cell gate and the trench element isolation region, and this high-concentration region is formed as a source / drain region 113. As shown in FIG. 1A, the source / drain regions 113 extend in the column direction along the trench element isolation structure 110, and are configured as bit lines.

Next, as shown in FIG. 3C, a CVD oxide film 114 is formed on the entire surface so as to be thicker than the cell gate. Then, the CVD oxide film 11 is formed by dry etching.
By etching the surface of the substrate 4 until the surface of the cell gate 104 is exposed, the CVD oxide film 114 is buried between the adjacent cell gates 104, and as a result, the surface is planarized. Further, the cell gate 104
A second polycrystalline silicon film is formed to a predetermined thickness on the entire surface of the CVD oxide film 114 including the upper surface of the silicon oxide film 114, and then, using a photoresist mask (not shown) exposed and developed to a predetermined shape. By pattern-etching the second polycrystalline silicon film, a pillar-shaped electrode 115 is formed on the cell gate 104 so as to project in a pillar shape. As a result, the first polycrystalline silicon film 103 constituting the cell gate 104 and the pillar type electrode 115 are integrated,
A floating gate 116 is formed. Further, a predetermined concentration of impurities is ion-implanted into the floating gate 116 so as to have a predetermined conductivity.

Then, as shown in FIG. 1B,
An ONO film 116 having a film structure with a predetermined thickness is formed as an inter-gate insulating film so as to cover the pillar type electrode 115. Subsequently, a third polycrystalline silicon film 117 doped with conductive impurities and a silicide wiring film 118 are sequentially formed thereon. Then, the silicide wiring film 118 and the third polycrystalline silicon film 117 are formed in a predetermined shape by using a dry etching method, and the word lines WL are formed.
To form Thus, the flash memory shown in FIG. 1 is formed.

In such a manufacturing method, the cell gate 10
4 formed on both side walls of nitride film 106
Are formed so as to cover the entire source / drain regions 113 formed on both sides of the cell gate in a later step.
When the trench 107 is formed in the silicon substrate 101 by etching, it functions as a protective film so that the source / drain formation region is not etched. Therefore, by covering the entire source / drain formation region with the nitride film sidewall 106, a fine trench element isolation structure can be formed in a self-aligned manner. In addition, the cell gate 10
4, the position of the trench groove 107 is not displaced, and the width of the source / drain region 113 is uniformly formed without deviation, so that the variation in the source / drain resistance is eliminated.

As described above, since the impurity for forming the source / drain regions 113 is introduced after the formation of the trench isolation structure 110, the thermal oxide film 108 necessary for forming the trench isolation structure 110 is formed. Is performed before the formation of the source / drain regions 113, so that no accelerated oxidation due to impurities occurs during the thermal oxidation process. Therefore, in the region where the thermal oxide film 108 on the inner wall of the trench groove 107 is in contact with the source / drain region 113, the film thickness does not increase abnormally.
Since the width dimension of the source / drain region 113 formed between them is reduced and the source / drain resistance is not increased, the operation speed of the flash memory can be improved.

In the above-described embodiment, the CVD nitride film used for the nitride film sidewall is not limited to the CVD nitride film as long as the material can provide a sufficient etching selectivity in dry etching or wet etching of the oxide film. is not. Further, according to the present invention, after a trench is formed in a self-aligned manner using a cell gate, the inner wall of the trench is thermally oxidized in a step prior to ion implantation of impurities for forming a source / drain region. As long as it includes a step of forming a film, the benefits of the present invention can be obtained even when the other steps in the above embodiment are appropriately changed.

[0022]

As described above, according to the present invention, the misalignment of the trench isolation structure with respect to the cell gate is achieved by forming the trench isolation structure by self-alignment using the sidewalls formed on both side walls of the cell gate. As a result, the widths of the source / drain regions can be formed uniformly and without unevenness, and variations in the source / drain resistance can be eliminated. Further, since impurities for forming the source / drain regions are introduced after the formation of the trench element isolation structure, the accelerated oxidation due to the impurities does not occur during the thermal oxidation treatment required at the time of forming the trench element isolation structure. In the region where the oxide film on the inner wall of the trench groove is in contact with the source / drain region, the film thickness does not abnormally increase and the width dimension of the source / drain region does not decrease, and the source / drain resistance does not increase. As a result, it is possible to realize the manufacture of a semiconductor memory device such as a flash memory with high integration and improved operation speed.

[Brief description of the drawings]

FIG. 1 is a plan layout diagram of a flash memory according to the present invention and a cross-sectional view taken along line XX thereof.

FIG. 2 is a first sectional view illustrating the method of manufacturing the flash memory in FIG. 1 in the order of steps;

FIG. 3 is a second sectional view illustrating the method of manufacturing the flash memory in FIG. 2 in the order of steps;

FIG. 4 is a diagram showing an example of a conventional method for manufacturing a semiconductor memory device in the order of steps.

[Explanation of symbols]

 Reference Signs List 101 silicon substrate 102 gate oxide film 103 first polycrystalline silicon film 104 cell gate 105 CVD oxide film 106 nitride film sidewall 107 trench groove 108 thermal oxide film 109 CVD oxide film 110 trench element isolation structure 111 LDD region 112 second side Wall 113 Source / drain region 114 CVD oxide film 115 Pillar type electrode (second polycrystalline silicon film) 116 ONO film (inter-gate insulating film) 117 Third polycrystalline silicon film 118 Silicide wiring film

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F001 AA25 AB08 AD17 AG07 5F032 AA35 AA44 AA45 CA17 CA23 DA02 DA23 DA24 DA25 DA30 DA33 DA43 DA53 DA80 5F083 EP05 EP27 EP55 EP56 EP63 EP65 EP68 EP70 EP77 GA02 JA04 JA35 NA01 NA06 PR29 PR36 PR PR40

Claims (4)

[Claims] A step of forming a cell gate on a semiconductor substrate; a step of forming a sidewall on a side wall of the cell gate; and a step of forming a trench groove in the semiconductor substrate using the sidewall in a self-aligned manner. Forming a thermal oxide film by thermally oxidizing an inner surface of the groove, and forming a trench element isolation structure by burying the trench, and removing the sidewall, and removing the sidewall from the semiconductor substrate in the removed region. A method for manufacturing a semiconductor memory device, comprising a step of forming source / drain regions by implanting impurities. 2. A step of forming a cell gate by laminating a gate insulating film, a gate electrode, and an insulating film on a semiconductor substrate and forming them in a required pattern; forming a nitride film on the entire surface; Forming a trench on a sidewall of the cell gate by anisotropic etching, forming a trench by etching the semiconductor substrate to a required depth using the sidewall as a mask, and forming an inner surface of the trench. Thermally oxidizing to form a thermal oxide film;
Depositing an oxide film, burying at least the trench groove with the oxide film to form a trench element isolation structure, and etching and removing the sidewalls;
Forming a source / drain region by ion-implanting impurities into the semiconductor substrate in a region where the sidewalls have been removed by using the cell gate and the trench isolation structure as a mask; and forming an insulating film on a surface of the semiconductor substrate. And flattening the surface with respect to the surface of the gate electrode; and forming a pillar-type electrode on the gate electrode that is integrated with the gate electrode to form a floating gate electrode, A method for manufacturing a semiconductor memory device, comprising: a step of forming an inter-gate insulating film on a surface of a pillar-type electrode; and a step of forming a control gate electrode on the inter-gate insulating film. 3. The step of forming the source / drain regions comprises implanting a low concentration impurity into the semiconductor substrate by self-alignment using the cell gate as a mask.
Forming a region, forming a second sidewall thinner than the sidewall on a side wall of the cell gate, and forming a region on the semiconductor substrate by self-alignment using the cell gate and the second sidewall as a mask. 3. The method of manufacturing a semiconductor memory device according to claim 1, further comprising a step of forming a high concentration source / drain region by implanting a high concentration impurity. 4. The semiconductor memory device according to claim 1, wherein the source / drain region extending in the column direction is a bit line, the control gate electrode extending in the row direction is a word line, and the cell gate is the word line. 4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the flash memory is a flash memory that is periodically arranged immediately below the flash memory.