JP2001326175A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in the conventional method that it is difficult to control the crystal orientation of a crystalline semiconductor film, forming by subjecting an amorphous semiconductor film formed on an underlying film which is a known crystallization processing. SOLUTION: Crystal orientation of a crystalline semiconductor film, formed by a known crystallization processing, can be controlled by subjecting the interface between the underlying film and the amorphous semiconductor film to fluorination processing, which is a preprocessing for forming an amorphous semiconductor film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor formed on a substrate and using a crystalline semiconductor film.
ransistor: a method for manufacturing a semiconductor device such as a TFT (hereinafter referred to as TFT). The semiconductor device of the present invention includes a liquid crystal display device having a semiconductor circuit (a microprocessor, a signal processing circuit, a high-frequency circuit, or the like) including not only elements such as a TFT and a MOS transistor, but also an insulated gate transistor. Lumi
nescence) display device, an EC (Electro Chromic) display device, or an image sensor. In addition, the semiconductor device of the present invention includes electronic devices such as a video camera, a digital camera, a projector, a goggle display, a car navigation, a personal computer, and a portable information terminal equipped with these display devices.

[0002]

2. Description of the Related Art At present, as a semiconductor element using a semiconductor film, a thin film transistor (TFT) is used for each integrated circuit, and particularly used as a switching element of an image display device. Further, a TFT using a crystalline semiconductor film having higher mobility than an amorphous semiconductor film for an active layer has a high driving capability and is used as an element of a driving circuit.

At present, an amorphous silicon film (amorphous silicon film) or a crystalline silicon film (polysilicon film) is mainly used as an active layer.

As a method for obtaining a crystalline semiconductor film, a thermal annealing method and a laser annealing method are well known. However, crystallization of an amorphous semiconductor film by a thermal annealing method requires a heating temperature of 600 ° C. or more and a heating time of 10 hours or more, so that it is difficult to use a glass substrate as a substrate. In the laser annealing method, it is not necessary to heat the substrate to a high temperature.However, since the amorphous semiconductor film is crystallized by the energy of light emitted linearly, irregularities on the surface of the crystalline semiconductor film are large, When formed, there is a problem that crystallization of a layer hidden under the gate electrode is difficult.

As an alternative method for obtaining these crystalline semiconductor films, the techniques described in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329 by the present applicant are known. The technique described in this publication uses a metal element (especially nickel, Ni) that promotes crystallization of silicon, and has a crystallinity excellent in crystallinity by heat treatment at 500 to 600 ° C. for about 4 hours. This makes it possible to form a silicon film.

[0006]

The crystalline silicon films obtained by these methods described above are generally (110) and (11).
1) It is known that it is composed of oriented crystal grains, and the present situation is that the orientation cannot be completely controlled. It is also known that the orientation of the crystal thus formed depends on the underlying film.

It is an object of the present invention to control the crystal orientation of a crystalline silicon film and to form a crystalline semiconductor film having further excellent crystallinity.

[0008]

In order to solve the above-mentioned problems, a conventional technique of crystallization of an amorphous silicon film by adding a metal element (particularly nickel or Ni) which promotes crystallization of silicon has been developed. Characterization processing is added. less than,
The description of the fluorination treatment will be described.

First, why the fluorination treatment is performed will be described. In the active layer, fluorine is treated as an impurity that reduces the reliability of TFT characteristics. Therefore, performing the fluorination treatment reduces the reliability of the TFT characteristics. However, by intentionally crystallizing an amorphous silicon film to which fluorine is added, (110)
It has been found that oriented crystals can be formed. From this, the fluorine in the amorphous silicon film becomes (11)
0) It is considered that this contributes to the formation of the oriented crystal.

As described above, since fluorine is an impurity, the content of fluorine in the amorphous silicon film is desirably the minimum necessary. The fluorination treatment according to the present invention includes the following 2
There are several methods. Fluorination (1) The surface of the underlying film or the surface of the amorphous silicon film is subjected to fluorine plasma treatment. Fluorination (2) A thin amorphous silicon film containing fluorine is formed immediately above the base film (that is, between the base film and the amorphous silicon film) or directly above the amorphous silicon film.

In the fluorination (1) treatment, SiF ₄ or N
A fluorinated gas such as F ₃ can be used. These gases are generally used for etching a silicon oxide film or an amorphous silicon film used as an insulating film and for dry cleaning of a film forming chamber such as a CVD apparatus and a sputtering apparatus. In other words, by performing the fluorine plasma treatment,
The surface of the base film or the amorphous silicon film is etched very thinly, and only the surface is fluorinated. Therefore, when performing the fluorination (1) treatment, it is necessary to select conditions under which the etching rates of the base film and the amorphous silicon film to be subjected to the fluorination treatment are as slow as possible.

In the fluorination (2) treatment, SiH ₄ and S
iF ₄ or a mixed gas of SiH ₄ and F ₂ can be used.

Conventional methods for adding a metal element (particularly, nickel or Ni) that promotes crystallization of silicon are roughly classified into the following two methods. Addition of Ni (1) A solution containing Ni is added to the surface of the underlying film or the surface of the amorphous silicon film. Ni addition (2) An extremely thin Ni film is formed on the surface of the underlying film or the surface of the amorphous silicon film.

Ni addition (1) includes Ni aqueous solution, N
An i-ethanol solution or a salt solution of Ni such as Ni acetate and Ni nitrate can be used. It is effective to drop the Ni-containing solution on the substrate, rotate the spinner at a low speed to form a uniform liquid film on the entire substrate, and then increase the rotation speed of the spinner to perform dry spin.

As the Ni addition (2), a sputtering method, a vapor deposition method, a plasma processing method or the like can be used. The plasma processing method is a parallel plate type or a positive medium type plasma C
In the VD apparatus, Ni is added by using an electrode made of a material containing Ni and generating plasma in an atmosphere such as nitrogen, hydrogen, or argon.

In the present invention, the above fluorination treatment and Ni
It is described that the addition treatment is performed on the surface of the base film or the surface of the amorphous silicon film. The reason why the treatment is performed not only on the surface of the conventional amorphous silicon film but also on the surface of the underlying film is that the orientation of crystals formed by crystallization differs depending on the underlying film. That is, by performing the fluorination treatment or the Ni addition treatment on the surface of the base film, it is possible to control the orientation of the crystal formed by crystallization using any base film.

According to the present invention, an amorphous silicon film is crystallized by combining the above-mentioned fluorination treatment and Ni addition treatment, thereby controlling the crystal orientation and forming a crystalline silicon film having excellent crystallinity. It is characterized by the following.

[0018]

Embodiments of the present invention will be described below.

[Embodiment 1] Here, a description will be given of a case where a fluorine plasma treatment as a fluorination (1) treatment and a Ni addition treatment are combined (FIG. 1).

A base film 101 is formed on a substrate 100.
The base film here may have a single layer or a multilayer structure. The substrate on which the base film 101 is formed is placed in a film forming chamber of a plasma CVD apparatus, and plasma is generated by introducing SiF ₄ gas or NF ₃ gas, and the substrate is exposed to a fluorine plasma atmosphere. In this step, the base film 101 is etched. It is also important to find conditions for uniformly etching the surface of the substrate. The etching rate is preferably 30 ° / min or less, preferably 10 ° / min or less. In the case where the etching uniformity is good but the etching rate becomes high, the base film 101 is taken into consideration in advance in consideration of the thickness of the film to be etched.
There is no problem if is formed thicker.

After the surface of the base film 101 is subjected to a fluorine plasma treatment, an amorphous silicon film 103 is formed. Examples of the forming means include a plasma CVD method and a thermal CVD method. However, in consideration of the contamination of the film interface, it is desirable to perform a continuous treatment with the fluorine plasma treatment by using the plasma CVD method.

Next, Ni is added. The substrate is set on the spinner, an aqueous solution containing Ni is dropped, the spinner is rotated at a low speed, and the aqueous solution is spread over the entire substrate, and then the spinner is rotated at a high speed to fly and dry the aqueous solution on the substrate. Of course, instead of the aqueous solution containing Ni, Ni
, Or a Ni salt solution such as Ni acetate or Ni nitrate can be used.

It is also possible to use an extremely thin Ni film instead of the above-mentioned Ni addition. A substrate is placed in a film forming chamber of a parallel plate type or a solar medium type plasma CVD apparatus using an electrode made of a material containing Ni, and plasma is generated in an atmosphere such as nitrogen, hydrogen, or argon. Of course, a sputtering method or an evaporation method may be used instead of the plasma treatment.

In any of the above methods, the addition is made here.
The amount of Ni is 1 × 10^Tenatoms / cm^TwoFrom 1 ×
10¹³atoms / cm^TwoIt is desirable that example
For example, when a 10 ppm Ni aqueous solution is used, the N
i concentration is about 2-4 × 10 ¹²atoms / cm^Twoso
is there. The substrate temperature is 300 ° C. and the pressure is 0.05 Torr.
r, argon 100 sccm, RF power 50 W
When Ni is added by plasma treatment, Ni on the substrate surface
The concentration is about 1-3 × 10¹²atoms / cm^TwoIn
You.

After the addition of Ni, the amorphous silicon film is dehydrogenated (at 500 ° C. for 1 hour), and then thermally crystallized (at 550).
C. for 4 hours). If necessary, laser annealing may be added after this.

As described above, the description has been made in the order of the fluorine plasma treatment → the formation of the amorphous silicon film → the Ni addition treatment. However, the combination order of the fluorine plasma treatment, the amorphous silicon film formation and the Ni addition treatment is arbitrary. .

[Embodiment 2] Here, a case where the formation of an amorphous silicon film containing a thin fluorine, which is the fluorination (2) treatment, and the Ni addition treatment are combined will be described (FIG. 2). The steps up to the formation of the base film 101 are the same as in the first embodiment.

A thin amorphous silicon film 102b containing fluorine is formed on the base film 101. As a film forming means, plasma CVD or thermal CVD can be used. As a gas type to be used, a mixed gas of SiH ₄ and SiF _{4 or} a mixed gas of SiH ₄ and F ₂ is used.

Next, an amorphous silicon film 103 is formed.
As in the first embodiment, the film forming means is plasma CVD or thermal C
VD can be used. If possible, it is desirable to perform a continuous treatment with the formation of an amorphous silicon film containing fluorine.

The Ni addition treatment after the formation of the amorphous silicon film is the same as in the first embodiment.

Similarly, as described above, the description has been made in the order of the formation of the fluorine-containing amorphous silicon film → the formation of the amorphous silicon film → the Ni addition treatment. The combination order of the formation, the formation of the amorphous silicon film, and the Ni addition treatment is free.

[0032]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a TFT (an n-channel TFT) of a pixel portion and a driver circuit provided around the pixel portion on the same substrate are used.
And a method for simultaneously fabricating a p-channel TFT).

As the substrate 200, a glass substrate, a quartz substrate, a ceramic substrate or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, as shown in FIG.
A base film 201 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate. Although a two-layer structure is used as the base film 201 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 201, a silicon oxynitride film 201a formed by a plasma CVD method using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is used.
Is formed to a thickness of 50 to 100 nm. Next, as a second layer of the base film 201, SiH ₄ ,
And N the ₂ O laminating a silicon oxynitride film 201b is formed as a reaction gas to a thickness of 100 to 150 nm.

The surface of the base film 201 is subjected to F plasma treatment.
SiF using plasma CVD equipment _FourIntroduce gas and
Perform a plasma treatment. Fluorine instead of F plasma treatment
The contained amorphous semiconductor film may be formed thin.

Next, an amorphous semiconductor film is formed. The amorphous semiconductor film can be formed by known means (sputtering method, LPCVD
Method or a plasma CVD method). This amorphous semiconductor film is formed to have a thickness of 30 to 60 nm. Although there is no limitation on the material of the amorphous semiconductor film, it is preferable that the amorphous semiconductor film be formed of silicon or a silicon germanium (SiGe) alloy.

Ni is added to the amorphous semiconductor film. The substrate is set on a spinner, and an aqueous solution having a Ni concentration of 10 ppm is dropped. First, after the Ni aqueous solution is spread over the entire surface of the substrate by low-speed rotation, the number of rotations is increased and spin drying is performed. Aqueous solution or Ni ethanol solution with different Ni concentration,
Alternatively, a salt solution of Ni such as Ni acetate and Ni nitrate may be used. Also, instead of adding Ni solution, N
i-plasma treatment may be performed. Nitrogen, hydrogen, or plasma is generated in an atmosphere such as argon using a parallel plate type using a Ni-containing material electrode, or a solar medium plasma CVD apparatus, or using a sputtering method or a vapor deposition method. An extremely thin Ni film may be formed.

After the addition of Ni, the amorphous semiconductor film is dehydrogenated (500 ° C., 1 hour), and then thermally crystallized (550).
C. for 4 hours). If necessary, laser annealing may be added after this. The crystalline semiconductor film thus obtained is patterned into a desired shape to form crystalline semiconductor layers 204 to 208.

Further, by using a plasma CVD apparatus, continuous processing from formation of the base film 201 to Ni addition processing is possible. For example, in a semiconductor device having a plurality of film forming chambers as shown in FIG.
03, a base film 201a is formed, then a base film 201b is formed in the second chamber 304, and then F plasma treatment or formation of an amorphous semiconductor film containing fluorine is performed in the third film formation chamber 305. Finally, a Ni plasma process is performed in the fourth chamber 306. As a result, impurity contamination at the film interface can be prevented, and one factor of deterioration in TFT characteristics can be reduced.

After the formation of the semiconductor layers 204 to 208, a slight amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

Next, a gate insulating film 209 covering the semiconductor layers 204 to 208 is formed. The gate insulating film 209 is
It is formed by plasma CVD or sputtering and has a thickness of 4
The insulating film containing silicon is formed to have a thickness of 0 to 150 nm. The gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O_TwoAnd a reaction pressure of 40 Pa and a substrate temperature of 3
00 to 400 ° C, high frequency (13.56 MHz) power
Density 0.5-0.8W / cm ^TwoBy discharging
Can be. Silicon oxide film produced in this way
After that, gate annealing is performed by annealing at 400 to 500 ° C.
Good characteristics can be obtained as an edge film.

Next, a gate conductive film is formed on the gate insulating film 209. In this embodiment, the film thickness is 20 to 100 nm.
First conductive film (TaN) 210 and a film thickness of 100 to 40
A second conductive film (W) 211 having a thickness of 0 nm is stacked.
The gate conductive film may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, and the first conductive film is formed of tantalum nitride (TaN).
A combination of a film and an Al film as the second conductive film;
The first conductive film may be formed of a tantalum nitride (TaN) film and the second conductive film may be formed of a Cu film.

Next, masks 212 to 217 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 25/25/10 (sccm). And 500 W RF (13.56 MH) at a pressure of 1 Pa
z) Power is supplied to generate plasma to perform etching. The substrate side (sample stage) also has a 150 W RF (1
(3.56 MHz), and apply a substantially negative self-bias voltage. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered.

Thereafter, the masks 212 to 212 made of resist are formed.
The second etching condition was changed without removing 217, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and a pressure of 1 Pa was applied to the coil-type electrode. 500W RF (13.56MHz)
Power is supplied to generate plasma, and etching is performed for about 30 seconds. 20W R on substrate side (sample stage)
F (13.56 MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, the shape of the resist mask is made appropriate so that
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In this manner, the first-shaped conductive layers 219 to 224 (the first conductive layers 219a to 224a and the second conductive layers 219b to 224) formed of the first conductive layer and the second conductive layer by the first etching process.
4b) is formed. 218 is a gate insulating film,
The region not covered with the conductive layers 219 to 224 having the shape of
A region which is etched and thinned by about 50 nm is formed.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer (FIG. 4C). The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1 × 10 ¹³
-5 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 60
It is performed as １００100 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. In this case, the conductive layers 218 to 2
Reference numeral 22 denotes a mask for an impurity element imparting n-type, and first impurity regions 224 to 228 are formed in a self-aligned manner. 1 × 1 in the first impurity regions 224 to 228
An impurity element for imparting n-type is added in a concentration range of 0 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

Next, a second etching process is performed as shown in FIG. 5A without removing the resist mask. Using CF ₄ , Cl ₂ and O _{2 as} etching gas,
Each gas flow rate ratio is 25/25/10 (sccm)
And 500 W of RF to the coil-type electrode at a pressure of 1 Pa
(13.56 MHz) Power is supplied to generate plasma, and etching is performed for about 20 seconds. RF power (13.56 MHz) of 20 W is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. The W film is etched under the third etching condition. In this manner, the W film is anisotropically etched under the above third etching conditions to form second shape conductive layers 231 to 236.

The etching reaction of the W film or the TaN film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressures of the fluorides of W and TaN with the chlorides, the fluoride of W, WF _6, is extremely high, and the other WCl ₅ , TaF ₅ , and TaCl ₅ are comparable. Therefore, with the mixed gas of CF ₄ and Cl ₂ , both the W film and the TaN film are etched. However, an appropriate amount of O
_{When 2} is added, CF ₄ and O ₂ react to become CO and F,
F radicals or F ions are generated in large quantities. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in TaN, the increase in the etching rate is relatively small even if the F increases. Further, since TaN is more easily oxidized than W, the surface of TaN is slightly oxidized by adding O ₂ . Since the oxide of TaN does not react with fluorine or chlorine, the etching rate of the TaN film is further reduced. Therefore, it is possible to make a difference in the etching rate between the W film and the TaN film, and the etching rate of the W film is made to be Ta.
It can be made larger than the N film.

Next, a second doping process is performed as shown in FIG. 5A without removing the resist mask. In this case, doping with an impurity element imparting n-type is performed under a condition of a higher acceleration voltage with a lower dose than in the first doping process. For example, when the acceleration voltage is 70 to 12
0 keV, and in this embodiment, an acceleration voltage of 90 keV,
Perform at a dose of 3.5 × 10 ¹² atoms / cm ² ,
A new impurity region is formed in the semiconductor layer inside the first impurity region formed in FIG. Doping is
The second conductive layers 231a to 235a are formed using the second shape conductive layers 231 to 235 as masks for impurity elements.
Is doped so that the impurity element is also added to the semiconductor layer below the semiconductor layer.

Thus, the second conductive layers 231a to 235
The second impurity regions 237 to 241 overlapping with a and the first impurity regions 242 to 246 are formed. The impurity element imparting n-type is 1 × 10 ¹⁷ to 1 × in the second impurity region.
The concentration is set to 10 ¹⁹ atoms / cm ³ .

Next, the gate insulating film is etched as shown in FIG. 5B without removing the resist mask. Second conductive layer 23 during gate insulating film etching
1a to 235a are simultaneously etched to form third shape conductive layers 242 to 247. Accordingly, the second impurity region can be distinguished into a region overlapping with the second conductive layers 242a to 247a and a region not overlapping.

After removing the resist mask, new masks 253 to 255 are formed, and a third doping process is performed as shown in FIG. 5C. By this third doping process, third impurity regions 256 to 261 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to a semiconductor layer to be an active layer of a p-channel TFT. . Using the third shape conductive layers 243 and 246 as a mask for the impurity element, a third impurity region is formed in a self-aligned manner by adding an impurity element imparting p-type. In this embodiment, the impurity regions 256 to 261 are formed by ion doping using diborane (B ₂ H _6). In the third doping process, the semiconductor layers forming the n-channel TFT are covered with masks 253 to 255 made of resist. Phosphorus is added at different concentrations to the impurity regions 256 to 261 by the first doping process and the second doping process, and the concentration of the impurity element imparting p-type is set to 2 × in each of the regions. 10 ^{20 to} 2 × 10 ²¹
By performing the doping treatment so as to be atoms / cm ³ , there is no problem because it functions as a source region and a drain region of the p-channel TFT.

Through the above steps, an impurity region is formed in each semiconductor layer. The third shape conductive layers 242 to 246 overlapping with the semiconductor layer function as gate electrodes. 247 functions as a source wiring, and 246 functions as a second electrode for forming a storage capacitor.

Next, masks 253 to 253 made of resist are formed.
255 is removed, and a first interlayer insulating film 262 covering the entire surface is formed. As the first interlayer insulating film 262, a thickness of 100 to
The insulating film containing silicon is formed to have a thickness of 200 nm. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 262 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 6A, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
What is necessary is just to carry out at 550 degreeC. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

Further, an activation process may be performed before forming the first interlayer insulating film 262. However, 242 to 24
In the case where the wiring material used in 7 is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) to protect the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

When a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 263 made of an organic insulating material is formed on the first interlayer insulating film 262. Next, a contact hole reaching the source wiring 247 and each of the impurity regions 248, 250, 251, 256, 2
Patterning for forming a contact hole reaching 59 is performed.

Then, in the driver circuit 406, wirings 264 to 269 electrically connected to the first impurity region or the third impurity region are formed. Note that these wirings are formed by patterning a laminated film of a 50-nm-thick Ti film and a 500-nm-thick alloy film (an alloy film of Al and Ti).

In the pixel portion 407, a pixel electrode 272, a gate conductive film 271, and a connection electrode 270 are formed. (FIG. 6B) The connection wiring 270 forms an electrical connection between the source wiring 247 and the pixel TFT 404. The gate conductive film 271 is formed of a first electrode (third electrode).
And a conductive layer 246) having the shape shown in FIG.
The pixel electrode 272 is electrically connected to the drain region of the pixel TFT, and is also electrically connected to a semiconductor layer functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 272, Al or A
It is desirable to use a material having excellent reflectivity, such as a film containing g as a main component or a stacked film thereof.

As described above, the n-channel TFT 40
1, p-channel TFT 402, n-channel TFT 4
03 and a pixel portion 407 including a pixel TFT 404 and a storage capacitor 405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 40 of the drive circuit 406
Reference numeral 1 denotes a second impurity region 23 overlapping a channel formation region 273 and a third shape conductive layer 242 forming a gate electrode.
7b (GOLD region), a second impurity region 237a (LDD region) formed outside the gate electrode, and a first impurity region 2 functioning as a source region or a drain region.
48. In the p-channel TFT 402, a channel formation region 274, a third impurity region 258 overlapping with the third shape conductive layer 243 forming the gate electrode, a third impurity region 257 formed outside the gate electrode, a source region Alternatively, a third impurity region 256 functioning as a drain region is provided. n-channel TFT 403
A second impurity region 23 overlapping with a channel formation region 275 and a third shape conductive layer 244 forming a gate electrode.
9b (GOLD region), a second impurity region 239a (LDD region) formed outside the gate electrode, and a first impurity region 2 functioning as a source region or a drain region.
50.

In the pixel TFT 404 in the pixel portion, a channel formation region 276 and a second impurity region 240b (GOLD) overlapping the third shape conductive layer 245 forming the gate electrode are provided.
Region), a second impurity region 240a (LDD region) formed outside the gate electrode, and a first impurity region 251 functioning as a source region or a drain region. The semiconductor layers 259 to 261 functioning as one electrode of the storage capacitor 405 are each doped with an impurity element imparting p-type at the same concentration as the third impurity region. The storage capacitor 405 is formed using the insulating film (the same film as the gate insulating film) as a dielectric, the second electrode 246 and the semiconductor layer 2.
59 to 261.

FIG. 7 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. 4 to 8.
Are assigned the same reference numerals. A chain line AA ′ in FIG. 7 corresponds to a cross-sectional view cut along a chain line AA ′ in FIG. The dashed line BB ′ in FIG. 7 corresponds to the cross-sectional view cut along the dashed line BB ′ in FIG.

As described above, in the active matrix substrate having the pixel structure of this embodiment, the first electrode 245 partially functioning as a gate electrode and the gate conductive film 271 are formed in different layers, and the gate conductive film is formed. 271, the semiconductor layer is shielded from light.

Further, in the pixel structure of this embodiment, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

The surface of the pixel electrode of this embodiment may be made uneven by a known method, for example, a sandblast method or an etching method to prevent specular reflection and to scatter reflected light to increase whiteness. desirable.

With the above-described pixel structure, a pixel electrode having a large area can be arranged, and the aperture ratio can be improved.

According to the steps shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is five (semiconductor layer pattern mask, first wiring pattern mask (first electrode 245, second electrode 246, a source wiring 247), a pattern mask for forming a source region and a drain region of a p-type TFT, a pattern mask for forming a contact hole, and a second wiring pattern mask (pixel electrode 2).
72, connection electrode 270, and gate conductive film 271))
It can be. As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

[Embodiment 2] An example in which the order of the fluorination treatment, the formation of the amorphous semiconductor film, and the Ni treatment in Embodiment 1 is changed is shown here.

After forming the base film 201 in the same manner as in the first embodiment, first, Ni is added to the surface of the base film 201. Next, an amorphous semiconductor film 203 is formed, and a fluorination treatment is performed on the surface of the amorphous semiconductor film. The addition of Ni, the formation of the amorphous semiconductor film, the fluorination treatment, and the subsequent steps may be performed in the same manner as in the first embodiment.

[Embodiment 3] An example in which the order of the fluorination treatment, the formation of the amorphous semiconductor film, and the Ni treatment in Embodiment 1 is changed is shown here.

As in the first embodiment, after forming the base film 201, first, the surface of the base film 201 is fluorinated. Next, a Ni addition treatment is performed, and finally, an amorphous semiconductor film 203 is formed. The addition of Ni, the formation of the amorphous semiconductor film, the fluorination treatment, and the subsequent steps may be performed in the same manner as in the first embodiment.

[Embodiment 4] An example in which the order of the fluorination treatment, the formation of the amorphous semiconductor film, and the Ni treatment in Embodiment 1 is changed is shown here.

After forming the base film 201 in the same manner as in the first embodiment, first, a Ni addition treatment is performed on the surface of the base film 201. Next, an amorphous semiconductor film containing fluorine is formed, and finally, an amorphous semiconductor film 203 is formed. Here, when performing the Ni addition treatment and the fluorination treatment continuously,
It should be noted that the F plasma treatment cannot be used because the surface of the base film 201 is thinly etched together with the added Ni. Ni addition, formation of an amorphous semiconductor film, formation of an amorphous semiconductor film containing fluorine, and the subsequent steps may be performed in the same manner as in the first embodiment.

[Embodiment 5] In this embodiment, Embodiments 1, 2 and
The steps of manufacturing an active matrix liquid crystal display device from the active matrix substrates manufactured in 3 and 4 will be described below. FIG. 8 is used for the description.

First, according to Examples 1, 2, 3 and 4, an active matrix substrate in the state of FIG.
An alignment film 501 is formed on the active matrix substrate of FIG. 6, and a rubbing process is performed. In this embodiment, the alignment film 5 is used.
Before the formation of No. 01, a columnar spacer 506 for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, the colored layer 50 is formed on the opposite substrate 503.
4, 505 and a flattening film 507 are formed. A second light-blocking portion is formed by partially overlapping the red coloring layer 504 and the blue coloring layer 505. Although not shown in FIG. 8, a first light-shielding portion is formed by partially overlapping a red coloring layer and a green coloring layer.

Next, a counter electrode 510 was formed in the pixel portion, an alignment film 508 was formed on the entire surface of the counter substrate, and a rubbing process was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealant 502.
Paste in. A filler is mixed in the sealant 502, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer 572. Thereafter, a liquid crystal material is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 8 is completed.

In this embodiment, the substrates shown in Embodiments 1, 2, 3 and 4 are used. Accordingly, in FIG. 7 showing a top view of the pixel portion of the first, second, third and fourth embodiments, at least the gap between the gate wiring 271 and the pixel electrodes 272 and 280, the gap between the gate wiring 271 and the connection electrode 270, and the connection electrode 270
It is necessary to shield the gap between the pixel electrode 272 and the pixel electrode 272. In this embodiment, the opposing substrates are bonded so that the first light-shielding portion and the second light-shielding portion overlap with those positions where light is to be shielded.

[Embodiment 6] In this embodiment, Embodiments 1, 2 and
In the active matrix substrate prepared in 3 and 4, EL
An example of manufacturing a display device will be described. FIG. 9A shows a top view of the EL display panel. 9A, reference numeral 10 denotes a substrate, 11 denotes a pixel portion, 12 denotes a source-side drive circuit, and 13 denotes a gate-side drive circuit. Each drive circuit reaches the FPC 17 via wirings 14 to 16 and is connected to an external device. Connected to

FIG. 9B is a sectional view corresponding to the line AA ′ in FIG. At this time, the opposing plate 80 is provided at least above the pixel portion, preferably above the driving circuit and the pixel portion.
Is provided. The opposing plate 80 is bonded to the active matrix substrate on which a self-luminous layer using a TFT and an EL material is formed by a sealing material 19. A filler (not shown) is mixed in the sealant 19, and the two substrates are bonded to each other at substantially uniform intervals by the filler. Further, the outside of the seal member 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 uses a material such as a silicone resin, an epoxy resin, a phenol resin, and butyl rubber.

As described above, when the active matrix substrate 10 and the counter substrate 80 are bonded together by the sealant 19, a space is formed therebetween. The space is filled with a filler 83. The filler 83 also has an effect of bonding the opposing plate 80. As the filler 83, PVC (polyvinyl chloride), epoxy resin, silicone resin, EVA (ethylene vinyl acetate), or the like can be used. In addition, since the self-luminous layer is weak to moisture including water and easily deteriorates, it is desirable to mix a desiccant such as barium oxide into the filler 83 because the moisture absorbing effect can be maintained. Further, a passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the self-light-emitting layer, so that corrosion due to an alkali element or the like contained in the filler 83 is prevented.

In FIG. 9B, a TFT for a driving circuit (here, a CM in which an n-channel TFT and a p-channel TFT are combined) is formed on the substrate 10 and the base film 21.
2 illustrates an OS circuit. 22) and TFT2 for pixel portion
3 (However, in this case, the TFT controlling the current to the EL element
Is only shown. ) Is formed.

To produce an EL display device from the active matrix substrates produced in Examples 1, 2, 3 and 4,
An interlayer insulating film (planarization film) 26 made of a resin material is formed on the source wiring and the drain wiring, and a pixel portion TF is formed thereon.
A pixel electrode 27 made of a transparent conductive film electrically connected to the drain of T23 is formed. A compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used for the transparent conductive film. After the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

Next, a self-luminous layer 29 is formed. The self-luminous layer 29 may have a laminated structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials. When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

The self-luminous layer is formed by a vapor deposition method using a shadow mask, an ink jet method, a dispenser method, or the like. In any case, by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel, color display becomes possible. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the self-luminous layer 29, the cathode 30 is formed thereon. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the self-luminous layer 29 as much as possible. Therefore, it is necessary to devise a method of continuously forming the self-luminous layer 29 and the cathode 30 in a vacuum or forming the self-luminous layer 29 in an inert atmosphere and forming the cathode 30 in a vacuum without opening to the atmosphere. . In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via the anisotropic conductive paste material 32. F
A resin layer 80 is further formed on the PC 17 to increase the adhesive strength at this portion.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, contact holes need to be formed in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming a self-luminous layer). Further, when etching the insulating film 28, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are the same resin material, the shape of the contact hole can be made good.

The wiring 16 is made of a sealing material 19 and the substrate 10.
Is electrically connected to the FPC 17 through a gap (but closed with a sealant 81). Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 18 in the same manner.

Here, FIG. 10 shows a more detailed sectional structure of the pixel portion, and FIG. 11 shows a top structure thereof. In FIG. 10A, a switching TFT provided on a substrate 2401 is provided.
2402 denotes the pixel TFT 404 in FIG. 6B of the first embodiment.
It has the same structure as described above. In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

The current control TFT 2403 has a structure in which an LDD that overlaps with the gate electrode is provided only on the drain side, and a structure in which the parasitic capacitance between the gate and the drain and the series resistance are reduced to increase the current driving capability. It has become. Further, since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and the element has a high risk of deterioration due to heat or hot carriers. Therefore, by providing an LDD region that partially overlaps the gate electrode in the current control TFT,
FT degradation can be prevented, and operation stability can be improved. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. A wiring indicated by 38 is a gate line that electrically connects the gate electrodes 39a and 39b of the switching TFT 2402.

In this embodiment, the current control TFT 2403 is shown in a single-gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG.
The wiring serving as the gate electrode 37 of the FT 2403 is a region indicated by reference numeral 2404 and overlaps with the drain line 40 of the current controlling TFT 2403 via an insulating film. At this time, a capacitor is formed in a region indicated by reference numeral 2404. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403.
The drain line 40 is a current supply line (power supply line) 2501
And a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since a self-light-emitting layer formed later is extremely thin, light emission failure may occur due to the presence of a step.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
Is electrically connected to the drain of As the pixel electrode 43, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed. Further, the bank 44 formed of an insulating film (preferably resin) is used.
The light-emitting layer 44 is formed in the groove (corresponding to a pixel) formed by a and 44b. Although only one pixel is shown here, light emitting layers corresponding to each of R (red), G (green), and B (blue) may be separately formed. As an organic EL material for the light emitting layer, polyparaphenylene vinylene (P
A π-conjugated polymer material such as a PV) -based material, a polyvinyl carbazole (PVK) -based material, or a polyfluorene-based material is used.

In this embodiment, PEDOT is formed on the light emitting layer 45.
This is a self-luminous layer having a laminated structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, the light emitting layer 45
Since the light generated in step (1) is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

FIG. 10B shows an example in which the structure of the light emitting layer is inverted. The current control TFT 2601 has the same structure as the p-channel TFT 402 in FIG. For the manufacturing process, Embodiment Mode 1 may be referred to. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50.

Then, the banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed. In the case of this embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

[Embodiment 7] T formed by carrying out the present invention
The FT can be used for various electro-optical devices (typically, an active matrix type liquid crystal display and the like).
That is, the present invention can be applied to all electronic devices incorporating these electro-optical devices and semiconductor circuits as components.

Such electronic devices include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
Examples include a personal computer and a portable information terminal device (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 12, 13 and 14.

FIG. 12A shows a personal computer, which includes a main body 1201, an image input section 1202, and a display section 12.
03, a keyboard 1204, and the like. The present invention can be applied to the image input unit 1202, the display unit 1203, and other signal control circuits.

FIG. 12B shows a video camera, which includes a main body 1205, a display section 1206, an audio input section 1207, operation switches 1208, a battery 1209, and an image receiving section 121.
Including 0 and the like. The present invention can be applied to the display portion 1206 and other signal control circuits.

FIG. 12C shows a mobile computer (mobile computer), which includes a main body 1211, a camera section 1212, an image receiving section 1213, operation switches 1214, a display section 1215, and the like. The present invention can be applied to the display unit 1215 and other signal control circuits.

FIG. 12D shows a goggle type display having a main body 1216, a display section 1217, and an arm section 121.
8 and so on. The present invention can be applied to the display portion 1217 and other signal control circuits.

FIG. 12E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 1219, a display unit 1220, and a speaker unit 122.
1, a recording medium 1222, an operation switch 1223, and the like. This player uses a DVD (Di
Gital Versatile Disc), CDs, etc., can be used for music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 1220 and other signal control circuits.

FIG. 12F shows a digital camera, which includes a main body 1224, a display section 1225, an eyepiece section 1226, operation switches 1227, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 1225 and other signal control circuits.

FIG. 13A shows a front type projector, which includes a projection device 1301, a screen 1302, and the like. The present invention can be applied to the liquid crystal display device 1314 forming a part of the projection device 1301 and other signal control circuits.

FIG. 13B shows a rear type projector, which includes a main body 1303, a projection device 1304, and a mirror 130.
5, a screen 1306 and the like. The present invention relates to a projection device 1
The present invention can be applied to a liquid crystal display device 1314 constituting a part of the display device 304 and other signal control circuits.

FIG. 13C is a diagram showing an example of the structure of the projection devices 1301 and 1304 in FIGS. 13A and 13B. Projection devices 1301, 13
04 denotes a light source optical system 1307, mirrors 1308 and 131
0 to 1312, dichroic mirror 1309, prism 1313, liquid crystal display 1314, retardation plate 131
5. It is composed of a projection optical system 1316. Projection optical system 13
Reference numeral 16 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 13D is a diagram showing an example of the structure of the light source optical system 1307 in FIG. 13C. In this embodiment, the light source optical system 1307 includes a reflector 1318, a light source 1319, a lens array 1320,
321, a polarization conversion element 1322, and a condenser lens 1323. Note that the light source optical system shown in FIG. 13D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 13, a case where a transmissive electro-optical device is used is shown, and an application example of a reflective electro-optical device is not shown.

FIG. 14A shows a mobile phone, which includes a display panel 1401, an operation panel 1402, and a connection section 140.
3. Display 1404 with built-in sensor, audio output unit 1
405, operation keys 1406, a power switch 1407, a voice input unit 1408, an antenna 1409, and the like. The present invention is applied to a display 1404 with a built-in sensor,
05, it can be applied to the audio input unit 1408 and other signal control circuits.

FIG. 14B shows a portable book (electronic book), which includes a main body 1411, a display portion 1412, and a storage medium 141.
3, including an operation switch 1414, an antenna 1415, and the like. The present invention can be applied to the display portion 1412, the storage medium 1413, and other signal circuits.

FIG. 14C shows a display, which includes a main body 1416, a support base 1417, a display portion 1418, and the like.
The present invention can be applied to the display portion 1418. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields.

【The invention's effect】

According to the present invention, an active layer close to a single crystal can be formed by controlling the crystal orientation of the crystalline semiconductor layer constituting the TFT, and high-speed processing of images and the like and high-speed communication can be performed. Becomes

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment.

FIG. 2 is an explanatory diagram of the second embodiment.

FIG. 3 is a diagram of a film forming apparatus having a plurality of film forming chambers.

FIG. 4 is a sectional view of a TFT according to the first embodiment.

FIG. 5 is a sectional view of a TFT according to the first embodiment.

FIG. 6 is a sectional view of a TFT according to the first embodiment.

FIG. 7 is a top view of a pixel portion of an active matrix substrate manufactured in Embodiment 1.

FIG. 8 is a cross-sectional view of an active matrix liquid crystal display device according to a fifth embodiment.

FIG. 9 is a top view and a cross-sectional view of an EL display panel according to a sixth embodiment.

FIG. 10 is a sectional view of an EL display panel according to a sixth embodiment.

FIG. 11 is a top view of an EL display panel according to a sixth embodiment.

FIG. 12 is a diagram showing various semiconductor devices according to the seventh embodiment.

FIG. 13 is a diagram showing various semiconductor devices according to the seventh embodiment.

FIG. 14 is a diagram showing various semiconductor devices according to the seventh embodiment.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 627G 21/336 (72) Inventor Satoshi Toriumi 398 Hase, Atsugi City, Kanagawa Prefecture Stock (72) Inventor Takashi Otsuki 398 Hase, Atsugi-shi, Kanagawa F-term (reference) 2H092 JA24 JA37 MA07 MA17 MA27 MA29 MA30 NA25 PA10 PA11 RA01 RA05 4K030 BA29 BB05 CA06 DA02 DA08 DA09 FA01 HA03 HA04 LA15 5F048 AA09 AB10 AC04 BA16 BB01 BB06 BB09 BC06 BC11 BE08 BF07 BG07 5F052 AA11 CA10 DA02 DB01 DB02 DB03 EA13 EA15 FA06 JA01 5F110 AA30 BB02 BB04 CC02 DD01 DD02 DD03 DD05 DD13 DD02 DD03 DD05 DD13 EE23 EE28 FF02 FF04 FF09 FF28 FF30 GG01 GG02 GG13 GG17 GG25 GG32 GG43 GG45 GG47 HJ01 HJ 04 HJ12 HJ13 HJ23 HL04 HL06 HL11 HM15 NN03 NN04 NN22 NN34 NN35 NN72 PP01 PP03 PP27 PP29 PP31 PP34 PP35 QQ04 QQ09 QQ10 QQ11 QQ24 QQ25

Claims (11)

[Claims] A step of forming a base of an insulating film on a substrate;
Forming an amorphous semiconductor film below the insulating film; and adding a catalytic element that promotes crystallization of the amorphous semiconductor film before and after the step of forming the amorphous semiconductor film; and A method for manufacturing a semiconductor device, comprising: a step of fluorine treatment; and a step of crystallizing the amorphous semiconductor film. A step of forming a base of an insulating film on the substrate;
Performing a fluorine treatment on the underlayer surface of the insulating film, forming an amorphous semiconductor film under the insulating film subjected to the fluorine treatment, and forming the amorphous semiconductor film on the surface of the amorphous semiconductor film. A method for manufacturing a semiconductor device, comprising: a step of adding a catalytic element that promotes crystallization of a film; and a step of crystallizing the amorphous semiconductor film. A step of forming a base of an insulating film on the substrate;
A step of adding a catalytic element that promotes crystallization of the amorphous semiconductor film to a base surface of the insulating film; anda step of forming an amorphous semiconductor film on a lower surface of the insulating film to which the catalytic element is added,
A method for manufacturing a semiconductor device, comprising: performing a fluorine treatment on a surface of the amorphous semiconductor film; and crystallizing the amorphous semiconductor film. 4. A step of forming a base of an insulating film on a substrate;
A step of subjecting the underlayer surface of the insulating film to a fluorine treatment, a step of adding a catalytic element that promotes crystallization of the amorphous semiconductor film to the underlayer surface of the insulating film subjected to the fluorine treatment, A method for manufacturing a semiconductor device, comprising: a step of forming an amorphous semiconductor film below an insulating film to which an element is added; and a step of crystallizing the amorphous semiconductor film. 5. A step of forming a base of an insulating film on a substrate;
A step of adding a catalyst element for promoting crystallization of the amorphous semiconductor film to a base surface of the insulating film, a step of subjecting the base surface of the insulating film to which the catalyst element is added to a fluorine treatment, and A method for manufacturing a semiconductor device, comprising: a step of forming an amorphous semiconductor film below a fluorine-treated insulating film; and a step of crystallizing the amorphous semiconductor film. 6. The method according to claim 1, wherein Ni, Pd, Pt, Cu, Ag, Au, In, S
A method for manufacturing a semiconductor device, comprising using one or more elements selected from n, Pb, As, and Sb. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the method of adding the catalyst element includes adding a solution containing the catalyst element or forming an extremely thin film made of the catalyst element. Method. 8. The method according to claim 1, wherein the in-plane concentration of the catalyst element in the coating film to which the catalyst element is added is 1 × 10 ¹⁰
A method for manufacturing a semiconductor device, which has a concentration of atoms / cm ² to 1 × 10 ¹³ atoms / cm ² . 9. The method for manufacturing a semiconductor device according to claim 1, wherein the method of fluorination treatment is fluorine plasma treatment or formation of an amorphous semiconductor film containing fluorine. 10. The semiconductor device according to claim 1, wherein the step of crystallizing the amorphous semiconductor film is at least one of a heat treatment step and a light irradiation step. Production method. 11. The method for manufacturing a semiconductor device according to claim 1, wherein the crystalline semiconductor film formed has a substantially (110) orientation.