JP2001312243A - Image display device and its driving circuit - Google Patents

Abstract

(57) [Problem] To reduce the area occupied by a signal line driving circuit of an image display device corresponding to a digital video signal input and to reduce the parasitic capacitance and resistance of an input transmission line of the digital video signal. SOLUTION: A means for directly inputting a digital video signal to a shift register for serial-parallel conversion, and n storage circuits and D / A conversion circuits in a signal line driving circuit (n is a natural number of 2 or more)
Incorporate both means shared by signal lines. One horizontal scanning period is divided into n periods, and in each of the divided periods, the storage circuit and the D / A conversion circuit perform processing on different signal lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for inputting a digital video signal and a driving circuit thereof, and more particularly to a reduction in the area occupied by the driving circuit, and a delay and waveform distortion of the input digital video signal. The present invention relates to a driving circuit of an image display device for reducing the image quality.

[0002]

2. Description of the Related Art In recent years, an image display device in which a semiconductor thin film is formed on a glass substrate, particularly a thin film transistor (hereinafter referred to as TFT).
Active matrix type image display devices using the same are widely used. An active matrix type image display device using a TFT (hereinafter, referred to as an image display device)
It has hundreds of thousands to millions of TFTs arranged in a matrix and controls the charge of each pixel.

Further, as a recent technology, in addition to a pixel TFT constituting a pixel, a polysilicon TFT technology in which a driving circuit is simultaneously formed using a TFT outside a pixel array portion is being developed.

[0004] In addition, not only the drive circuit formed simultaneously with the analog video signal but also a digital circuit is realized.

FIG. 25 shows a configuration example of an active matrix type liquid crystal display device which is one of the image display devices. FIG.
As shown in FIG. 1, this liquid crystal display device has a signal line driving circuit 101, a scanning line driving circuit 102, a pixel array section 103,
It is composed of a signal line 104, a scanning line 105, a pixel TFT 106, a liquid crystal 107 and the like.

FIG. 26 illustrates in detail the structure of a conventional (digital) signal line drive circuit corresponding to a digital video signal. FIG. 27 is a timing chart for FIG. Here, an image display device having k (horizontal) × 1 (vertical) pixels will be described as an example. For simplicity of description, a case where the digital video signal is 3 bits is taken as an example, but the number of bits is not limited to 3 in an actual image display device. 26 and 27 show specific examples of k = 640.

The conventional signal line driving circuit has the following configuration. They include a shift register that receives a clock signal (CLK) and a start pulse (SP) and sequentially shifts a pulse, a first storage circuit (LAT1) that sequentially stores digital video signals by an output of the shift register, The output of the first storage circuit is latched by a latch signal (L
P) and a second storage circuit (LAT)
2) a D / A conversion circuit (DAC) for converting the output of the second storage circuit into an analog signal. here,
The storage circuit uses a latch circuit.

The number of shift register stages (corresponding to the number of DFFs shown in FIG. 26) is k + 1. The output signal of the shift register is directly or via a buffer,
Control signals (SR-001-S) for the storage circuit (LAT1)
R-640). The first storage circuit (LAT1) stores digital video signals (D0 to D2) in accordance with the output timing of the control signal. Here, 3 (number of bits) × k (number of horizontal signal lines) first storage circuits (LAT1) are required. The second storage circuit (LAT2) is also 3k
Required.

The signal line driving circuit receives a shift register clock signal (CLK), a start pulse (SP), digital video signals (D0 to D2), and a latch signal (LP). First, a start pulse (SP) and a clock signal (CLK) are input to the shift register, and the pulses are sequentially shifted. Output of shift register (FIG. 26)
SR-001 to SR-640) are pulses shifted by one cycle of the clock signal (CLK) as shown in FIG. Depending on the output signal of the shift register, the first
The storage circuit (LAT1) operates and stores the digital video signal input at that time. By shifting the pulse of the shift register by one line, the digital video signal for one line is stored in the first storage circuit (LAT).
It is stored in 1). (In FIG. 26, L1-001 to L1-
640. However, for simplicity, the bits are collectively shown without distinction. )

Next, during the horizontal retrace period, the latch signal (L
P) is input. The latch signal activates the second storage circuit (LAT2) and the first storage circuit (LAT2).
The video signal stored in (1) in FIG.
001-L1-640) is the second storage circuit (LAT2)
Is stored. When the horizontal retrace period ends and the next horizontal scanning period starts, the shift register starts operating again. On the other hand, the digital video signal (L2-001 to L2 in FIGS. 26 and 27) stored in the second storage circuit (LAT2)
-640. However, for the sake of simplicity, the bits are collectively shown without distinction, and are converted into analog signals by a D / A conversion circuit (DAC). This analog signal is connected to a signal line (FIG. 26).
In S001 to S640), the data is written to the corresponding pixel via the pixel TFT turned on by the scanning line driving circuit.

By the above operation, the image display device writes a video signal to the pixel and performs display.

[0012]

The digital driving circuit described above has a disadvantage that its occupied area is much larger than that of the analog driving circuit. The digital system has an advantage that a signal is represented by a binary value of “Hi” or “Lo”. However, the amount of data becomes huge instead. It has become. The increase in the area of the image display device causes an increase in the manufacturing cost thereof, and there is a problem that the profit of the manufacturing company is deteriorated.

Further, with the rapid increase in the amount of information to be handled in recent years, the number of pixels has been increased and the pixels have been refined. However, as the number of pixels increases, the number of drive circuits also increases, and it is desired to further reduce the area of the drive circuit.

Here, examples of the display resolution of a commonly used computer are shown below by the number of pixels and the standard name. Number of pixels Standard name 640 × 480 VGA 800 × 600 SVGA 1024 × 768 XGA 1280 × 1024 SXGA 1600 × 1200 UXGA

For example, taking the SXGA standard as an example,
Assuming that the number of bits is 8, the conventional driving circuit described above has 1 bit.
For each of 280 signal lines, 10240 first memory circuits, second memory circuits, and 10240 D / A conversion circuits are required. In addition, high-definition television receivers such as high-definition TV (HDTV) have become widespread, and high-definition images have become necessary not only in the computer world but also in the field of AV. Terrestrial digital broadcasting has begun in the United States, and the era of digital broadcasting will begin in Japan. In digital broadcasting, the number of pixels is 1920 × 10
80 are promising, and the reduction of the area occupied by the drive circuit is urgently required.

On the other hand, as shown in FIG. 26, in a conventional digital driving circuit, a digital video signal (D
Since the signal transmission lines for supplying 0 to D2) need to be connected to all of the first storage circuits (LAT1), the length of the wiring is very long. As a result, the load on the signal transmission line such as load capacity and resistance increases,
The delay and waveform distortion of the digital video signal increase. This tendency becomes conspicuous as the number of pixels increases, and there is a problem that it is difficult to perform display based on an accurate digital video signal.

In order to solve the above-mentioned problems, the present invention reduces the area occupied by the signal line driving circuit, and furthermore,
An object of the present invention is to provide a technique for reducing delay and waveform distortion of a digital video signal.

[0018]

A memory circuit and a D / A conversion circuit in a signal line driving circuit are shared by n (n is a natural number of 2 or more) signal lines. One horizontal scanning period is divided into n, and in each of the divided periods, the storage circuit and the D / A conversion circuit process different signal lines, so that all signal lines are equivalent to the conventional example. Can be driven. Thus, the storage circuit and the D / A conversion circuit in the signal line driving circuit can be reduced to 1 / n of the conventional example. Note that in this specification, performing appropriate processing for displaying an image on a signal line or a scanning line is referred to as “driving a signal line” or “driving a scanning line”.

Also, the digital video signal is directly input to the shift register, and when the shift register is sequentially shifted to a desired position, the input of the clock signal is stopped to stop shifting the signal, and the signal is held at that position. Let it. By inputting a latch signal before the input of the next digital video signal and clock signal is started, the signal held in the shift register is transferred to the storage circuit, which is equivalent to the conventional second storage circuit. Actions can be taken. By directly inputting the digital video signal to the shift register in this way, the signal transmission line for supplying the digital video signal is shortened, and the number of gates to be connected is increased from several thousand to several, so the gate capacity is dramatically increased. As a result, the resistance and load capacity of the signal transmission line can be reduced.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, an image display device in which the number of pixels in the horizontal direction and the number of pixels in the vertical direction are generally k and l will be described as an example. In the present embodiment, the digital video signal is described as having three bits, but the present invention is not limited to three bits, and is also effective for 6 bits, 8 bits, or any other number of bits. In the following description, n is used as a parameter indicating how many signal lines are driven by one D / A conversion circuit. However, when the number k of pixels in the horizontal direction is not a multiple of n, it is appropriate to use k. And a number that is a multiple of n is newly defined as k. in this case,
If the added pixel is treated as a virtual one, there is no hindrance to the actual operation.

The configuration of this embodiment will be described below.
Next, the operation of the present embodiment will be described. FIG. 1 shows an example of the signal line driving circuit of the present embodiment, and FIG. 2 shows the operation timing thereof. However, FIGS. 1 and 2 show specific examples of k = 640. In the following, symbols such as k are used for general description, but specific numbers corresponding to FIGS. 1 and 2 are shown in []. The configuration of the scanning line driving circuit and the configuration of the pixel array unit are the same as those of the conventional example.

The signal line driving circuit of this embodiment includes three shift registers (first to third shift registers) each including a delay flip-flop (DFF), a storage circuit (LAT), and a D / A converter. It has a circuit (DAC) and a signal line selection circuit 10a. In a conventional example, a start pulse is input to a shift register. In the present embodiment, a digital video signal is input instead of a start pulse. A latch signal (LP) is input to each storage circuit (LAT). Each D / A conversion circuit (DAC) drives n signal lines, and writes the output of the D / A conversion circuit to an appropriate signal line by the signal line selection circuit 10a. However, FIGS. 1 and 2
Has shown a specific example of n = 4.

As can be seen from FIG. 1, the DFF is 3 × ((k
/ N) +1) stage [483 stages], the storage circuit (LAT) is 3
k / n [480] and a D / A conversion circuit (DA
C) has k / n [160], each of which is present.

Next, the operation will be described with reference to FIG. Digital video signals (D0 to D2) of different bits and a clock signal (CLK) are input to each shift register. During one horizontal scanning period, digital video signals corresponding to all the signal lines are sequentially input as time elapses. Therefore, D0, D1, and D2 are each composed of digital video signals corresponding to individual signal lines. The arrangement order of digital video signals input with the lapse of time during one horizontal scanning period is different from that of the conventional example, and is represented by “(k−n + 1, k
−2n + 1,..., N + 1, 1), (kn−2, k−2)
.., n + 2, 2), (kn−3, k−2n +
3,..., N + 3, 3),..., (K, k−2n,.
n, n)] [(637, 633, ..., 5, 1), (63
8, 634, ..., 6, 2), (639, 635, ...,
7, 3), (640, 636,..., 8, 4)].
Here, parentheses “()” represent a subgroup. Each shift register sequentially shifts the input digital video signal while synchronizing with the clock signal (CLK) [S
R-001 to SR-160].

The latch signal (LP) is input to the storage circuit (LAT) n times in one horizontal scanning period. In the present embodiment, a latch signal is input at the following timing.

First, in the first sub-group, when a digital video signal whose signal line number corresponds to kn + 1 [637] is output from the k / n-th stage [160th stage] DFF, a clock signal is output. Is temporarily stopped to fix the output from each DFF. At this time, the first latch signal (L
P), and the output of each DFF of the shift register is stored in each storage circuit (LAT). By this operation, the signal line numbers “1, n + 1, 2n + 1,..., K−n + 1” [“1,
5, 9,... 637 ”] are transferred to the storage circuit (LAT).

After that, the digital video signal of the second sub-group and the clock signal are inputted, and the digital video signal whose signal line number corresponds to kn + 2 [638] is k.
When output from the / n-th stage [160th stage] DFF, the clock signal is temporarily stopped to fix the output from each DFF. At this time, the second latch signal (LP) is input, and the output of each DFF of the shift register is stored in each storage circuit (L
AT). With this operation, the signal line number “2,
n + 2, 2n + 2,..., kn + 2 "[“ 2, 6, 10,
, 638 "] has been transferred to the storage circuit (LAT).

Thereafter, the same operation is repeated until the last n-th
The digital video signal whose signal line number corresponds to k [640] in the sub-group is the k / nth stage [160th stage]
, The clock signal is temporarily stopped to fix the output from each DFF. At this time, the n-th (fourth) latch signal (LP) is input, and the output of each DFF of the shift register is stored in each storage circuit (LAT). By this operation, the signal line numbers “n, 2n, 3n,
, K "(" 4, 8, 12, ..., 640 ") has been transferred to the storage circuit (LAT).

By the input of the latch signal (LP) as described above, all the digital video signals for one row of the signal line are transferred to the storage circuit (LAT).

The output of the storage circuit (LAT) is input to a D / A conversion circuit, and a 3-bit digital signal is converted into an analog signal. The converted analog signal is written to an appropriate signal line via the signal line selection circuit 10a. Hereinafter, the write timing will be described.

In one horizontal scanning period, the storage circuit (LAT) repeats the storage operation n times as described above. Therefore, a digital video signal corresponding to a certain signal line is stored in the storage circuit (LA).
While the data is stored in T), the corresponding signal line must be selected to end the writing.

First, signal line numbers “1, n + 1, 2n + 1,..., K−n + 1” of the first subgroup.
During the period in which the digital video signal corresponding to [1, 5, 9,... 637] is stored in the storage circuit (LAT),
The first control signal (SS1) is input, and each signal line selection circuit 10a outputs “1, n + 1, 2n + 1,..., K−n + 1”.
The [1, 5, 9,..., 637]] th signal line is selected.

Next, the data in the storage circuit (LAT section) is renewed, and signal line numbers "2, n + 2, 2n + 2,..., Kn + 2" [2, 6 ,
10,..., 638 "], the second control signal (SS2) is input during a period in which the digital video signal corresponding to the digital video signal is stored in the storage circuit (LAT). n + 2, 2n + 2, ..., kn + 2 "[" 2, 6,
, 638 "] th signal line.

Generally, assuming that i is a natural number, the signal line numbers "i, n + i, 2n +"
During the period in which the digital video signal corresponding to “i,..., kn + i” is stored in the storage circuit (LAT), the i-th control signal (SSi) is input, and each signal line selection circuit 10a outputs “i”. , N + i, 2n + i,..., K−n + i ”th signal lines, respectively.

Thus, n times in one horizontal scanning period,
By inputting a control signal pulse to the signal line selection circuit 10a, it becomes possible to write the output of the D / A conversion circuit to an appropriate signal line.

The output of the storage circuit (LAT) and D / A
A buffer circuit, a level shift circuit, an enable circuit for limiting an output period, or the like may be provided between the conversion circuits. The input arrangement order of the digital video signals is not limited to the above order. The arrangement order is determined by the operation method of the signal line selection circuit, the operation direction of the shift register (input connection position of the digital video signal), and the like.

In the present embodiment, the case where a 3-bit digital video signal is input without division is described. However, the input digital video signal may be divided in order to lower the operating frequency of the shift register. In this case, signal transmission lines of a total of 3 bits × the number of divisions are input, and the same number of shift registers are required. Note that the number of DFFs included in each shift register decreases in accordance with the divided number.

In the above embodiment, the D / A conversion circuit may use a ramp type D / A conversion circuit. In that case,
The number of D / A conversion circuits is not limited to k / n.

[0039]

(Embodiment 1) In this embodiment, an image display device conforming to the XGA standard having 1024 pixels in the horizontal direction and 768 pixels in the vertical direction will be described as an example. In the present embodiment, the digital video signal is described as having three bits, but the present invention is not limited to three bits, but is also effective for six bits, eight bits, or any other number of bits. In addition, a case where four signal lines are driven by one D / A conversion circuit is taken as an example.

Hereinafter, the configuration of this embodiment will be described.
Next, the operation of the present embodiment will be described.

FIG. 3 shows a signal line driving circuit according to the present embodiment. Since the configuration of the scanning line driving circuit and the configuration of the pixel array unit are the same as those of the related art, description thereof will be omitted. The signal line driving circuit of this embodiment has three shift registers each including 257 stages of DFFs (first to third shift registers).
A 256 × 3 (number of bits) storage circuit (LAT);
It has 256 D / A conversion circuits and 256 signal line selection circuits 10b.

The clock signal (CLK) is commonly input to each shift register, but the first bit digital video signal (D0) is sent to the first shift register to the second bit digital video signal ( D1) is the third bit digital video signal (D2) to the second shift register.
Are input to the third shift register. Memory circuit (LA
T), the latch signal (LP) is supplied to the signal line selection circuit 10.
The four control signals (SS1 to SS4) are respectively input to b. In the present embodiment, unlike the case of FIG. 1, a signal transmission line or the like for supplying a digital video signal is input from the right side of the signal line driving circuit.

Next, the operation will be described with reference to FIG. Each shift register has a corresponding digital video signal (Di (i = 0 to 2)) and a clock signal (CL).
K) is input. Each shift register sequentially shifts the input digital video signal (Di) from right to left.
This situation is shown by SR-256, SR-255,..., S in FIG.
Shown in R-001. The order of arrangement of digital video signals input with the passage of time is represented by the number of the corresponding signal line, which is “(1, 5,..., 1017, 1021), (2,
6, 1018, 1022), (3, 7, ..., 101)
9, 1023), (4, 8,..., 1020, 102)
4) ". Here, parentheses “()” represent a subgroup. In the present embodiment, unlike FIG. 1, the digital video signal shifts from right to left, so that the arrangement order of the video signals is different from that shown in FIG.

The latch signal (LP) input to the storage circuit (LAT) section is input four times during one horizontal scanning period. In this embodiment, a latch signal is input at the following timing.

First, in the first subgroup, the digital video signal corresponding to the signal line number "1" is the first stage DFF (in FIG. 3, the leftmost column DFF is the zeroth stage). Output from the DF, temporarily stop the clock signal and
The output from F is fixed. At this time, the first latch signal (LP) is input, and the output of each DFF of the shift register is stored in each storage circuit (LAT). With this behavior,
The digital video signals corresponding to the signal line numbers “1, 5,..., 1017, 1021” are transferred to the storage circuit (LAT), and are simultaneously output to the D / A conversion circuit.

Thereafter, the digital video signal of the second sub-group and the clock signal are input, and when the digital video signal corresponding to the signal line number “2” is output from the first stage DFF, the clock signal is output. Temporarily stop each DFF
Fix the output from. At this time, the second latch signal (LP) is input, and the output of each DFF of the shift register is stored in each storage circuit (LAT). With this operation, the digital video signals corresponding to the signal line numbers “2, 6,..., 1018, 1022” are transferred to the storage circuit (LAT), and at the same time, those signals are output to the D / A conversion circuit. You.

Next, the digital video signal of the third sub-group and the clock signal are input, and when the digital video signal corresponding to the signal line number “3” is output from the first stage DFF, the clock is output. Stop the signal temporarily and set each DFF
Fix the output from. At this time, the third latch signal (LP) is input, and the output of each DFF of the shift register is stored in each storage circuit (LAT). In this operation, the digital video signals corresponding to the signal line numbers “3, 7,..., 1019, 1023” are transferred to the storage circuit (LAT), and at the same time, those signals are output to the D / A conversion circuit. You.

Finally, the digital video signal of the fourth subgroup and the clock signal are input, and when the digital video signal corresponding to the signal line number “4” is output from the first stage DFF, the clock is output. Stop the signal temporarily and set each DFF
Fix the output from. At this time, the fourth latch signal (LP) is input, and the output of each DFF of the shift register is stored in each storage circuit (LAT). With this operation, the digital video signals corresponding to the signal line numbers “4, 8,..., 1020, 1024” are transferred to the storage circuit (LAT), and at the same time, those signals are output to the D / A conversion circuit. You.

By the input of the latch signal as described above, all the digital video signals for one row of the signal line are stored in the storage circuit (LA).
T).

The 3-bit digital signal input to the D / A conversion circuit is converted to an analog signal. The converted analog signal is written to an appropriate signal line via the signal line selection circuit 10b. Hereinafter, the write timing will be described.

In one horizontal scanning period, the storage circuit (LAT) repeats the storage operation four times. Therefore, while the digital video signal corresponding to a certain signal line is stored in the storage circuit (LAT), the corresponding signal line must be selected and the writing must be completed.

First, during the period in which the digital video signal corresponding to the signal line number “1, 5,..., 1017, 1021” which is the first subgroup is stored in the storage circuit (LAT), , 1017, and 102. The control signal (SS1) is input to each of the signal line selection circuits 10b.
The "1" th signal line is selected.

Next, during the period in which the digital video signal corresponding to the signal line number “2, 6,..., 1018, 1022” which is the second sub-group is stored in the storage circuit (LAT), The second control signal (SS2) is input, and each signal line selection circuit 10b outputs “2, 6,..., 1018, 102”.
Select the "2nd" signal line.

Further, during a period in which the digital video signal corresponding to the signal line numbers “3, 7,..., 1019, 1023”, which is the third subgroup, is stored in the storage circuit (LAT), ., 1019, and 103.
The 23rd signal line is selected.

Finally, during the period in which the digital video signals corresponding to the signal line numbers “4, 8,..., 1020, 1024” which are the fourth sub-group are stored in the storage circuit (LAT), The fourth control signal (SS4) is input, and each signal line selection circuit 10b outputs “4, 8,.
The 24th signal line is selected.

Thus, four times during one horizontal scanning period,
By inputting a control signal pulse to the signal line selection circuit 10b, it is possible to write the output of the D / A conversion circuit to an appropriate signal line.

The output of the storage circuit (LAT) and D / A
A buffer circuit, a level shift circuit, an enable circuit for limiting an output period, or the like may be provided between the conversion circuits. The input arrangement order of the digital video signals is not limited to the above order. The arrangement order is determined by the operation method of the signal line selection circuit, the operation direction of the shift register (input connection position of the digital video signal), and the like. For example, it has already been described that the order of arrangement of the signals in the sub-group is reversed depending on which of the left and right sides of the signal line drive circuit is input in the input of the digital video signal. Further, in the above case, when the timings of inputting the pulses of the first control signal (SS1) and the fourth control signal (SS4) of the signal line selection circuit 10b are interchanged, the input order of the digital video signals is also the first order.
The fourth sub-group is replaced with the fourth sub-group.

FIG. 5 shows a specific example of the storage circuit. FIG.
FIG. 5A shows an example using a clocked inverter, FIG. 5B shows an SRAM type, and FIG.
AM type. These are representative examples, and the present invention is not limited to these types.

As described above, in the present invention, although the number of shift registers increases, the number of shift registers is one-fourth that of the conventional shift register, one-eighth of the conventional storage circuit, and one-fourth of the conventional storage circuit. The image display device can be driven by the first D / A conversion circuit, and the area occupied by the drive circuit and the number of elements can be significantly reduced. In addition, since the digital video signal is directly input to the shift register, the signal transmission line that supplies the digital video signal is shortened, and the connected gate capacitance is dramatically reduced, and the resistance and load capacitance of the signal transmission line are reduced. Can be reduced.

(Embodiment 2) In this embodiment, an example in which a D / A conversion circuit of a ramp system is adopted as the D / A conversion circuit will be described. FIG. 6 is a schematic diagram of a signal line driving circuit in the case where a D / A conversion circuit of a ramp system is used. In this embodiment, the case where the image display apparatus of the XGA standard supports a 3-bit digital video signal will be described. However, the present invention is not limited to the 3-bit image display apparatus. This is also effective for a standard image display device.

The configuration and operation of this embodiment will be described below.

This embodiment is the same as the first embodiment from the shift register to the storage circuit (LAT). Downstream of the storage circuit, a bit comparison pulse width conversion circuit (BPC), an analog switch 20, and a signal line selection circuit 10c are provided. The 3-bit digital video signal, the count signal (C0 to C2), and the set signal (ST) stored in the storage circuit (LAT) are input to the bit comparison pulse width conversion circuit (BPC). The analog switch 20 has an output (PW-i, i) of the bit comparison pulse width conversion circuit.
001 to 256) and a gray scale power supply (VR). The output of the analog switch 20 and the control signals (SS1 to SS4) are input to the signal line selection circuit 10c.

FIG. 8 shows a configuration example of the bit comparison pulse width conversion circuit (BPC) at the i-th stage from the left in FIG. B
PC is an exclusive OR gate, 3-input NAND gate, inverter, set-reset flip-flop (RS-F
F). In FIG. 8, the i-th storage circuit (LAT)
Are output by dividing the bits into Li (0), Li
(1) and Li (2).

Next, the operation of this embodiment will be described.
FIG. 7 shows the operation timing of the signal system necessary for understanding the circuit operation of FIG. The operation from the shift register to the storage circuit (LAT) is the same as in the first embodiment. Also,
The control signals (SS1 to SS1) input to the signal line selection circuit 10c
SS4) is the same as in the first embodiment. Each time four signal lines are sequentially selected by the signal line selection circuit 10c, the count signal (C0 to C2) and the set signal (S
T), a gradation power supply (VR) is periodically input. This makes it possible to write information to all signal lines equally.

In order to explain the detailed operation of the ramp type D / A conversion circuit, the operation timing during a period in which one of the four signal lines is selected by the signal line selection circuit is shown in FIG.
Shown in First, the input of the set signal causes the RS-FF 30
Is set, and the output PW-i becomes Hi level. Next, the digital video signal stored in the second latch circuit is converted into a count signal (C0) by an exclusive OR gate.
To C2) for each bit. If all three bits match, the outputs of all exclusive OR gates are Hi.
Level, and as a result, the output of the three-input NAND gate (RC-i) becomes Lo level (therefore, R
(Ci becomes Hi level). The output of the three-input NAND is also input to the RS-FF 30, and is reset when RC-i becomes Hi level, and the output PW-i returns to Lo level. FIG. 9 shows a 3-bit digital video signal {Li}.
(0), Li (1) Li (2)} is {0, 0, 1}
The output examples of RC-i, PW-i, and DA-i for the case (1) are shown. Thus, the information of the digital video signal is converted into the pulse width of the output PW-i of the bit comparison pulse width conversion circuit (BPC).

The output PW-i of the bit comparison pulse width conversion circuit (BPC) controls opening and closing of the analog switch 20. The analog switch 20 has a count signal (C0 to C
2) A gray scale power supply (V) having a step-like voltage level synchronized with
R) is applied, the BPC output PW-i conducts to the signal line only during the Hi level, and the voltage at the moment when the PW-i becomes the Lo level is written to the signal line.

With the above operation, the digital video signal is converted into an analog signal, and an arbitrary potential is written to the signal line.
Note that the gradation power supply (VR) does not need to be stepwise, and may be a monotonous one that changes continuously. Further, a buffer circuit, a level shift circuit, or the like may be provided between the output of the bit comparison pulse width conversion circuit (BPC) and the analog switch 20.

As described above, in the present invention, a ramp type D / A conversion circuit can be used as the D / A conversion circuit, and the circuit configuration is only about one-fourth of the conventional one, and the occupancy of the drive circuit is small. The area and the number of elements can be significantly reduced.

(Embodiment 3) In this embodiment, the number of pixels in the horizontal direction is 640 × 3 (3 colors of RGB), and the number of pixels in the vertical direction is 480. This will be described by taking an image display device as an example. However,
R, G, and B represent the three primary colors of light, red, green, and blue, respectively. Also in this embodiment, the digital video signal is described as having 3 bits, but the present invention is not limited to 3 bits, and the present invention is not limited to 3 bits.
It is also valid for bits or any other number of bits. Further, a case where three signal lines are driven by one D / A conversion circuit is taken as an example.

The configuration and operation of this embodiment will be described below.

FIG. 10 shows a signal line driving circuit according to this embodiment. Since the configuration of the scanning line driving circuit and the configuration of the pixel array unit are the same as those of the related art, description thereof will be omitted.
The signal line driving circuit of this embodiment has three shift registers (first to third shift registers) each composed of 641 stages of DFFs.
A 640 × 3 (bit number) storage circuit (LAT);
It has 640 D / A conversion circuits and 640 signal line selection circuits 10d.

The clock signal (CLK) is commonly input to each shift register, but the digital video signal (D0) of the first bit of RGB is supplied to the first shift register, and the second bit of RGB is transmitted to the first shift register. Digital video signal (D
1) is input to the second shift register, and the digital video signal (D2) of the third bit of RGB is input to the third shift register. The storage circuit (LAT) has a latch signal (L
P) is transmitted to the signal line selection circuit 10d by three control signals (S
S1 to SS3) are respectively input. In this embodiment, as in the case of FIG. 1, a signal transmission line or the like for supplying a digital video signal is input from the left side of the signal line driving circuit.

Next, the operation will be described with reference to FIG. Each shift register receives a corresponding RGB digital video signal (Di (i = 0 to 2)) and a clock signal (CLK). Each shift register sequentially shifts the input digital video signal (Di) from left to right. This situation is shown in SR-001 and SR-00 in FIG.
2,..., SR-640. The order of arrangement of digital video signals input over time is represented by “(R640, R63
9,..., R002, R001), (G640, G63)
9,..., G002, G001), (B640, B63)
9,..., B002, B001) ”. Here, parentheses “()” represent subgroups, which are grouped by RGB. In the present embodiment, the digital video signals are shifted from left to right as in FIG. 1, and the arrangement order of the video signals is also in the descending order in the subgroup as in FIG.

The latch signal (LP) is input to the storage circuit (LAT) three times during one horizontal scanning period. In this embodiment, a latch signal is input at the following timing.

First, the digital video signal corresponding to the signal line “R640” in the first “R” subgroup
When the signal is output from the 40th stage DFF (the leftmost column DFF in FIG. 10 is the first stage), the clock signal is temporarily stopped to fix the output from each DFF. At this time, the first latch signal (LP) is input, and the output of each DFF of the shift register is stored in each storage circuit (LAT). By this operation, the signal lines “R001, R002,.
9, R640 "is transferred to the storage circuit (LAT), and at the same time, these signals are output to the D / A conversion circuit.

After that, the digital video signal of the second “G” subgroup and the clock signal are input, and when the digital video signal corresponding to the signal line “G640” is output from the 640-stage DFF, the clock is output. The signal is temporarily stopped to fix the output from each DFF. At this time, the second latch signal (LP) is input, and each D of the shift register is input.
The output of the FF is stored in each storage circuit (LAT). By this operation, the signal lines “G001, G002,..., G639,
G640 ”is stored in the storage circuit (L
AT), these signals are output to the D / A conversion circuit at the same time.

Finally, when the digital video signal of the third sub-group “B” and the clock signal are input and the digital video signal corresponding to the signal line “B640” is output from the 640-stage DFF, The clock signal is temporarily stopped to fix the output from each DFF. At this time, the third latch signal (LP) is input, and each D of the shift register is input.
The output of the FF is stored in each storage circuit (LAT). By this operation, the signal lines “B001, B002,..., B639,
B640 "is stored in the storage circuit (L
AT), these signals are output to the D / A conversion circuit at the same time.

By inputting the latch signal as described above, all the digital video signals for one row of the signal line are stored in the storage circuit (LA).
T).

The 3-bit digital signal input to the D / A conversion circuit is converted to an analog signal. The converted analog signal is written to an appropriate signal line via the signal line selection circuit 10d. Hereinafter, the write timing will be described.

In one horizontal scanning period, the storage circuit (LAT) repeats the storage operation three times. Therefore, while the digital video signal corresponding to a certain signal line is stored in the storage circuit (LAT), the corresponding signal line must be selected and the writing must be completed.

First, the signal lines “R001, R002,..., R639, R6” which are the first subgroup of “R”
The digital video signal corresponding to “40” is stored in the storage circuit (LA
T) during the period stored in the first control signal (SS).
1), and each signal line selection circuit 10d outputs “R001,
, R639, R640 ".

Next, signal lines "G001, G002,..., G639, G6" which are the second subgroup of "G"
The digital video signal corresponding to “40” is stored in the storage circuit (LA
T) during the period stored in the second control signal (SS).
2), and each signal line selection circuit 10d outputs “G001,
, G639, G640 "are selected.

Finally, the signal lines “B001, B002,..., B639, B” which are the third subgroup of “B”
640 "is stored in the storage circuit (LA
T) during the period stored in the third control signal (SS).
3), and each signal line selection circuit 10d outputs “B001,
, B639, B640 ".

As described above, one horizontal scanning period is performed for RGB.
By inputting a control signal pulse to the signal line selection circuit 10d three times in response to the above, the output of the D / A conversion circuit can be written to an appropriate signal line.

The output of the storage circuit (LAT) and the D / A
A buffer circuit, a level shift circuit, an enable circuit for limiting an output period, or the like may be provided between the conversion circuits. The input arrangement order of the digital video signals is not limited to the above order. The arrangement order is determined by the operation method of the signal line selection circuit, the operation direction of the shift register (input connection position of the digital video signal), and the like. For example, in the input of the digital video signal, the arrangement order of the signals in the sub-group is reversed depending on which of the left and right of the signal line driving circuit is input. In the above, the signal line selection circuit 10d
The first control signal (SS1) and the third control signal (SS1)
If the pulse input timing of 3) is changed,
The input arrangement order of the digital video signals is also the same as the first “R” subgroup and the third “B” subgroup.

As described above, in the present invention, although the number of shift registers is increased, each shift register has one-third the number of conventional circuits, one-sixth storage circuit, and three-minute conventional circuits. The image display device can be driven by the first D / A conversion circuit, and the area occupied by the drive circuit and the number of elements can be significantly reduced. In addition, since the digital video signal is directly input to the shift register, the signal transmission line that supplies the digital video signal is shortened, and the connected gate capacitance is dramatically reduced, and the resistance and load capacitance of the signal transmission line are reduced. Can be reduced.

(Embodiment 4) In this embodiment, a pixel TFT which is a switching element of a pixel portion, a pixel TFT, and a pixel portion will be described as an example of a production method when the embodiments 1 to 3 are applied to an active matrix type liquid crystal display device. A method for manufacturing TFTs of driving circuits (eg, a signal line driving circuit and a scanning line driving circuit) provided on the same substrate over the same substrate will be described in accordance with the steps. However, for the sake of simplicity, a CMOS circuit, which is a basic configuration circuit, is provided in the drive circuit section for the pixel T in the pixel section.
In the FT, an n-channel TFT is illustrated by a cross section along a certain path.

First, as shown in FIG. 12A, oxidation is performed on a substrate 400 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass. A base film 401 including an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed. For example, a silicon oxynitride film 401a manufactured from SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method has a thickness of 10 to 200 nm.
(Preferably 50-100 nm) and Si
Silicon oxynitride hydride film 4 made of H ₄ and N ₂ O
01b is 50 to 200 nm (preferably 100 to 150 nm).
(nm). In this embodiment, the base film 401 is used.
Is shown as a two-layer structure, but it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

The island-shaped semiconductor layers 402 to 406 are formed of a crystalline semiconductor film formed by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method. The thickness of the island-shaped semiconductor layers 402 to 406 is 25 to 80 nm.
(Preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set to 100 to 400 mJ / cm ² (typically, 20 to 400 mJ / cm ² ).
0 to 300 mJ / cm ² ). When a YAG laser is used, its second harmonic is used and a pulse oscillation frequency of 1 is used.
-10kHz, laser energy density 300 ~
600 mJ / cm ² may (typically 350~500mJ / cm ²⁾ to. And a width of 100 to 1000 μm, for example 400
A laser beam condensed linearly in μm is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time is set to 80 to 98%.

Next, a gate insulating film 407 covering the island-shaped semiconductor layers 402 to 406 is formed. Gate insulating film 407
Uses a plasma CVD method or a sputtering method and has a thickness of 4
The insulating film containing silicon is formed to have a thickness of 0 to 150 nm. In this embodiment, a silicon oxynitride film with a thickness of 120 nm is formed. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, and the substrate temperature is 300 to 4.
00 ° C., high frequency (13.56 MHz) power density 0.5
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus manufactured is
Good characteristics as a gate insulating film can be obtained by thermal annealing at 0 to 500 ° C.

[0092] Then, a first conductive film 408 and a second conductive film 409 for forming a gate electrode are formed over the gate insulating film 407. In the present embodiment, the first conductive film 40
8 is formed of Ta to a thickness of 50 to 100 nm, and the second conductive film 409 is formed of W to a thickness of 100 to 300 nm.

The Ta film is formed by a sputtering method, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. α phase T
If a film of tantalum nitride having a crystal structure close to that of the α phase of Ta is formed on a base of Ta with a thickness of about 10 to 50 nm to form the a film, a Ta film of the α phase can be easily obtained. .

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when using the sputtering method,
By using a W target having a purity of 99.9999% and forming a W film with sufficient care so as not to mix impurities from the gas phase during film formation, the resistivity is 9 to 20 μΩc.
m can be realized.

In this embodiment, the first conductive film 408
Is Ta, and the second conductive film 409 is W.
It may be formed of an element selected from a, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a combination other than the present embodiment, the first combination
A combination of forming the first conductive film with tantalum nitride (TaN) and forming the second conductive film with Al; There is a combination in which the first conductive film is formed of tantalum nitride (TaN) and the second conductive film is Cu.

Next, resist masks 410 to 41 are used.
7, and a first etching process for forming an electrode and a wiring is performed. In this embodiment, the ICP (Inductively
Coupled Plasma: Inductively coupled plasma) etching method, CF ₄ and Cl ₂ are mixed in an etching gas, and 1 Pa
500W RF (13.56MHz) to coil type electrode at pressure of
Power is supplied to generate plasma. 100 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF ₄
When Cl and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Under the above-mentioned etching conditions, by making the shape of the mask made of resist suitable, the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes a taper shape with an angle of 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. In this manner, the first shape conductive layers 419 to 426 (the first conductive layers 419 a to 426 a) including the first conductive layer and the second conductive layer are formed by the first etching process.
And second conductive layers 419b to 426b). 41
Reference numeral 8 denotes a gate insulating film, which has first shape conductive layers 419 to 419.
The region not covered by 426 is etched by about 20 to 50 nm to form a thinned region.

Then, a first doping process is performed, and n
An impurity element for imparting a mold is added. (FIG. 12 (B))
The doping may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1
× 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60
It is performed as １００100 keV. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used. In this case, the conductive layers 419 to 423 serve as a mask for the impurity element imparting n-type, and the first impurity regions 427 to 431 are formed in a self-aligned manner. The first impurity regions 427 to 431 have 1 × 10 ²⁰ to 1 × 10 ²¹ atomic.
An impurity element imparting n-type is added in a concentration range of / cm ³ .

Next, a second etching process is performed as shown in FIG. Similarly, using an ICP etching method, CF ₄ , Cl ₂ and O ₂ are mixed in an etching gas,
RF power of 500 W (13.
(56 MHz) to generate plasma. An RF (13.56 MHz) power of 50 W is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under these conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a slower etching rate to form the second shape conductive layers 433 to 440 (first Conductive layers 433a to 440a
And second conductive layers 433b to 440b). 43
Reference numeral 2 denotes a gate insulating film, and the second shape conductive layers 433 to 433 to
Areas not covered by 437 are further etched by about 20 to 50 nm to form thinner areas.

The etching reaction of the W film or the Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ionic species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, the dose is lower than that of the first doping process, and n is set as a condition of a high acceleration voltage.
Doping with an impurity element for giving a mold. For example, the acceleration voltage is set to 70 to 120 keV and the dose is set to 1 × 10 ¹³ / cm ² , and a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. Form. The doping is performed in the second shape conductive layers 433-437.
Is used as a mask for the impurity element, and the region below the first conductive layers 433a to 437a is doped so that the impurity element is added. Thus, the third impurity regions 441 to 441 overlapping with the first conductive layers 433a to 437a are formed.
445, and second impurity regions 446 to 450 between the first impurity region and the third impurity region. The impurity element imparting n-type is 1 × 10 2 in the second impurity region.
The concentration is set to ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ ,
In the impurity region of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ .

Then, as shown in FIG. 13B, fourth impurity regions 454 to 456 having a conductivity type opposite to one conductivity type are formed in the island-shaped semiconductor layer 403 forming the p-channel TFT. Using the second shape conductive layer 434 as a mask for the impurity element, an impurity region is formed in a self-aligned manner. At this time, the entire surface of the island-shaped semiconductor layers 402, 404, 405, and 406 forming the n-channel TFT is covered with resist masks 451 to 453. Impurity region 4
Phosphorous is added at different concentrations respectively to 54-456, but by an ion doping method using diborane _{(B 2 H 6), 2} × the impurity concentration in that any region
It is set to be 10 ^{20 to} 2 × 10 ²¹ atoms / cm ³ .

Through the above steps, an impurity region is formed in each of the island-shaped semiconductor layers. The conductive layers 433 to 436 overlapping with the island-shaped semiconductor layers function as gate electrodes of the TFT. Reference numeral 439 functions as a signal line, 440 functions as a scanning line, 437 functions as a capacitor wiring, and 438 functions as a wiring in a driver circuit.

FIG. 13 shows a diagram for controlling the conductivity type.
As shown in (C), a step of activating the impurity element added to each of the island-shaped semiconductor layers is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere of ppm or less. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, 433-4
When the wiring material used for 40 is weak to heat, it is preferable to activate after forming an interlayer insulating film (mainly composed of silicon) in order to protect the wiring and the like.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, the first interlayer insulating film 457 is formed from a silicon oxynitride film with a thickness of 100 to 200 nm. A second interlayer insulating film 458 made of an organic insulating material is formed thereon. Next, an etching step for forming a contact hole is performed.

Then, a source wiring 459 for forming a contact with the source region of the island-shaped semiconductor layer in the drive circuit portion.
To 461, drain wirings 462 to 464 for forming contacts with the drain region are formed. In the pixel portion, pixel electrodes 466 and 467 and a connection electrode 465 are formed (FIG. 14). The signal line 43 is connected to the connection electrode 465.
No. 9 is electrically connected to the pixel TFT 504.
The pixel electrode 466 is electrically connected to the island-shaped semiconductor layer 405 corresponding to the active layer of the pixel TFT and the island-shaped semiconductor layer (not shown) forming the storage capacitor. Note that the pixel electrode 467 and the storage capacitor 505 are for adjacent pixels.

As described above, the n-channel TFT 5
01, p-channel TFT 502, n-channel TFT
A driver circuit portion including the pixel circuit 503 and a pixel portion including the pixel TFT 504 and the storage capacitor 505 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 501 in the driver circuit portion includes a channel formation region 468, a third impurity region 441 (GOLD region) overlapping the conductive layer 433 forming a gate electrode, and a second impurity formed outside the gate electrode. A region 446 (LDD region) and a first impurity region 427 functioning as a source or drain region are provided.
The channel forming region 46 is formed in the p-channel TFT 502.
9. a fourth impurity region 456 overlapping the conductive layer 434 forming the gate electrode, and a fourth impurity region 456 formed outside the gate electrode.
And a fourth impurity region 454 functioning as a source or drain region. n
The channel type TFT 503 includes a channel forming region 470,
A third impurity region 443 (GOLD region) overlapping with the conductive layer 435 forming the gate electrode, a second impurity region 448 (LDD region) formed outside the gate electrode, and a first impurity region functioning as a source region or a drain region. Impurity region 429.

In the pixel TFT 504 in the pixel portion, a channel forming region 471, a third impurity region 444 (GOLD region) overlapping the conductive layer 436 forming a gate electrode, and a second impurity region 449 formed outside the gate electrode. (LD
D region) and a first impurity region 430 functioning as a source region or a drain region. The semiconductor layer 431 functioning as one electrode of the storage capacitor 505 has the same concentration as the first impurity region, the semiconductor layer 445 has the same concentration as the third impurity region, and the semiconductor layer 450 has the second concentration. An impurity element imparting n-type is added at the same concentration as the impurity region, and a storage capacitor is formed by the capacitor wiring 437 and an insulating layer (the same layer as the gate insulating film) therebetween.

In this embodiment, the ends of the pixel electrodes are arranged so as to overlap the signal lines and the scanning lines so that the gap between the pixel electrodes can be shielded from light without using a black matrix.

Further, according to the steps shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is five (the island-like semiconductor layer pattern, the first wiring pattern (scanning line, signal line, capacitor wiring). ), An n-channel region mask pattern, a contact hole pattern, and a second wiring pattern (including pixel electrodes and connection electrodes). As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

(Embodiment 5) In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 4 will be described below. FIG. 15 is used for the description.

First, according to the fourth embodiment, after obtaining the active matrix substrate in the state shown in FIG. 14, an alignment film 506 is formed on the active matrix substrate shown in FIG. 14, and a rubbing process is performed.

On the other hand, a counter substrate 507 is prepared. The color filter layers 508 and 509 and the overcoat layer 510 are formed on the counter substrate 507. The color filter layer has a structure in which a red color filter layer 508 and a blue color filter layer 509 are formed over the TFT so as to also serve as a light shielding film. When the substrate of Example 4 is used, at least the TFT, the connection electrode, and the pixel electrode need to be shielded from light. Therefore, a red color filter and a blue color filter are stacked so as to shield those positions from light. It is preferable to arrange them.

The red color filter layer 508 and the blue color filter layer 5 correspond to the connection electrodes 465.
09, a green color filter layer 511 is overlapped to form a spacer. The color filter of each color is a mixture of an acrylic resin and a pigment, and is formed with a thickness of 1 to 3 μm. This can be formed in a predetermined pattern using a photosensitive material and a mask. The height of the spacer can be set to 2 to 7 μm, preferably 4 to 6 μm in consideration of the thickness of the overcoat layer 510 of 1 to 4 μm. Form a gap at the time. The overcoat layer 510 is formed of a photocurable or thermosetting organic resin material, for example, polyimide or acrylic resin.

The arrangement of the spacers may be determined arbitrarily. For example, as shown in FIG. 15, it is preferable to arrange the spacers on the opposing substrate so as to be aligned on the connection electrodes. Further, the spacer may be arranged on the opposing substrate such that the position thereof is aligned with the TFT of the driving circuit portion. The spacer may be disposed over the entire surface of the drive circuit portion, or may be disposed so as to cover the source wiring and the drain wiring.

After forming the overcoat layer 510, the counter electrode 512 is formed by patterning, and after forming the alignment film 513, a rubbing process is performed.

Then, the active matrix substrate on which the pixel portion and the drive circuit portion are formed and the opposing substrate are sealed with a sealant 51.
Attach with 4 A filler is mixed in the sealant 514, and the two substrates are bonded at a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material 515 is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used for the liquid crystal material 515. Thus, the active matrix type liquid crystal display device shown in FIG. 15 is completed.

The TFT formed by the above steps
Has a top gate structure but a bottom gate structure TF
The present invention can be applied to TFTs having T or other structures.

The present invention is also applicable to an EL display device which is a self-luminous image display device using an electroluminescence (EL) material instead of a liquid crystal material. Note that the EL element includes a layer containing an organic compound from which electroluminescence (Electroluminescence: luminescence generated by applying an electric field) is obtained (hereinafter, referred to as an organic compound layer), an anode, and a cathode. Luminescence of an organic compound includes light emission when returning from a singlet excited state to a ground state (fluorescence) and light emission when returning from a triplet excited state to a ground state (phosphorescence). The present invention can also be applied to an EL display device using.

(Embodiment 6) In this embodiment, a description will be given of a manufacturing example in which Embodiments 1 to 3 are applied to an EL display device.

FIG. 16A is a top view of an EL display device to which the present invention is applied, and FIG. 16B is a cross-sectional view of the EL display device taken along the line AA ′ shown in FIG. It is.
In FIG. 16A, reference numeral 4010 denotes a substrate; 4011, a pixel portion; 4012, a signal line driver circuit; 4013, a scanning line driver circuit;
Through 016, it reaches the FPC 4017 and is connected to an external device.

At this time, the cover member 460 is formed so as to surround at least the pixel portion, preferably the driving circuit and the pixel portion.
0, sealing material (also called housing material) 4100,
A sealing material (a second sealing material) 4101 is provided.

Further, as shown in FIG.
010, a TFT for a driving circuit (here, an n-channel TFT and a p-channel TFT
2 illustrates a CMOS circuit combining the above. ) 402
2 and a TFT 4023 for the pixel portion (here, only the TFT for controlling the current to the EL element is shown). These TFTs may use a known structure (top gate structure or bottom gate structure).

A TFT for a driving circuit is manufactured by using a known manufacturing method.
4022, when the pixel portion TFT 4023 is completed, a pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on an interlayer insulating film (planarization film) 4026 made of a resin material. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O) or a compound of indium oxide and zinc oxide. Then, the pixel electrode 4027
Is formed, an insulating film 4028 is formed, and the pixel electrode 40 is formed.
An opening is formed on 27.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

[0128] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region shown at 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 4603 and the filler 460 cover the surface of the EL element thus formed.
4. The cover material 4600 is formed.

Further, the sealing material 4600 and the sealing material 4 are provided inside the substrate 4010 so as to surround the EL element portion.
The sealing material (second sealing material) 4101 is formed outside the sealing material 4100.

At this time, the filler 4604 also functions as an adhesive for bonding the cover material 4600.
As the filler 4604, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant in the inside of the filler 4604 since a moisture absorbing effect can be maintained.

[0135] A spacer may be contained in the filler 4604. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 4603 can relieve the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 4600, a glass plate, an aluminum plate, a stainless steel plate, FRP (Fiber)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. In addition, the filler 460
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 4600 needs to have translucency.

The wiring 4016 is made of a sealing material 410.
0 and through the gap between the sealing material 4101 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealing material 4100 and the sealing material 4101.

In this embodiment, after the filler 4604 is provided, the cover 4600 is adhered and the sealing material 4100 is attached so as to cover the side surface (exposed surface) of the filler 4604. Lumber 41
After attaching 00, the filler 4604 may be provided. In this case, an injection port of a filler is provided to communicate with a space formed by the substrate 4010, the cover material 4600, and the sealing material 4100. Then, the gap is vacuumed (10
^-2 Torr or less), immerse the injection port in the water tank containing the filler, and then fill the gap with the filler by setting the pressure outside the gap higher than the pressure inside the gap.

Embodiment 7 In this embodiment, an example in which an EL display device having a mode different from that of Embodiment 6 is manufactured by using the present invention will be described with reference to FIGS. 17A and 17B. I do. 16A and 16B denote the same parts, and a description thereof will not be repeated.

FIG. 17A is a top view of the EL display device of this embodiment, and FIG. 17B is a cross-sectional view taken along line AA ′ of FIG.

According to the sixth embodiment, a passivation film 4603 is formed to cover the surface of the EL element.

Further, a filler 4604 is provided so as to cover the EL element. The filler 4604 is used as the cover material 4
It also functions as an adhesive for bonding 600. As the filler 4604, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant in the inside of the filler 4604 since a moisture absorbing effect can be maintained.

Further, a spacer may be contained in the filler 4604. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 4603 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover member 4600, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. In addition, the filler 460
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 4600 needs to have translucency.

Next, using the filler 4604, the cover 4
After bonding 600, the side surface of filler 4604 (exposed surface)
Frame material 4601 is attached so as to cover. Frame material 4601 is a sealing material (functions as an adhesive)
4602. At this time, a photocurable resin is preferably used as the sealing material 4602, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 4602 is preferably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 4602.

The wiring 4016 is made of a sealing material 460.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 4602 in the same manner.

In this embodiment, after the filler 4604 is provided, the cover 4600 is adhered, and the frame 4601 is attached so as to cover the side surface (exposed surface) of the filler 4604. Lumber 4601
And then the filler 4604 may be provided. In this case, an inlet for a filler is provided to communicate with a space formed by the substrate 4010, the cover member 4600, and the frame member 4601. Then, the gap is evacuated (10 ^-2 Torr).
r), the filler is filled in the gap by immersing the injection port in the water tank containing the filler, and then making the pressure outside the gap higher than the pressure inside the gap.

Embodiment 8 Here, FIG. 18 shows a more detailed sectional structure of a pixel portion in an EL display device, FIG. 19A shows a top structure, and FIG. 19B shows a circuit diagram. FIG.
8, FIG. 19 (A) and FIG. 19 (B) use the same reference numerals and may be referred to each other.

In FIG. 18, as a switching TFT 4502 provided on a substrate 4501, an n-channel TFT formed by a known method is used. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. In addition, p formed by a known method
It may be formed using a channel type TFT.

As the current control TFT 4503, an n-channel TFT formed by a known method is used. The source wiring (signal line) of the switching TFT 4502 is 34
It is. The drain wiring 35 of the switching TFT 4502 is connected to the current control TF
It is electrically connected to the T gate electrode 37. Also,
The wiring indicated by 38 is a switching TFT 4502
The gate wiring (scanning line) for electrically connecting the gate electrodes 39a and 39b.

Since the current control TFT 4503 is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or deterioration due to hot carriers. Therefore, the current control TFT 45
A structure in which an LDD region is provided on the drain side of the transistor 03 so as to overlap the gate electrode with a gate insulating film interposed therebetween is extremely effective.

In this embodiment, the current controlling TFT 45 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 19A, the wiring 36 serving as the gate electrode 37 of the current control TFT 4503 is electrically connected to the drain wiring 40 of the current control TFT 4503 via an insulating film in a region 4504. Power supply line 4506 which is connected to the power supply line. At this time, a capacitor is formed in the area indicated by 4504, and the current control T
It functions as a storage capacitor for holding a voltage applied to the gate electrode 37 of the FT 4503. The storage capacity 4504 is
Semiconductor film 45 electrically connected to power supply line 4506
07, an insulating film (not shown) in the same layer as the gate insulating film and the wiring 36. The wiring 36, the same layer (not shown) as the first interlayer insulating film, and the power supply line 450
6 can also be used as a storage capacitor. Note that the drain of the current controlling TFT is connected to a power supply line (power supply line) 4506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 4502 and the current control TFT 4503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

The light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by the banks 44a and 44b formed of an insulating film (preferably resin). FIG.
In (A), some banks are omitted in order to clarify the position of the storage capacitor 4504, and only the banks 44a and 44b are shown, but the power supply line 4506 and the source wiring (signal line) 34 are connected to one another. It is provided between the power supply line 4506 and the source line (signal line) 34 so as to cover the portion. Although only two pixels are shown here, R (red),
Light emitting layers corresponding to each color of G (green) and B (blue) may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of an organic EL material that can be used as a light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 4
505 is completed. Note that the EL element 4505 referred to here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, and the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display device of the present invention has the structure shown in FIG.
8 and a switching TFT having a sufficiently low off-current value and a current controlling TFT resistant to hot carrier injection. Therefore, an EL display device having high reliability and capable of displaying an excellent image can be obtained.

(Embodiment 9) In this embodiment, a structure in which the EL element 4505 is inverted in the pixel portion shown in Embodiment 8 will be described. FIG. 20 is used for the description.
Note that the difference from the structure of FIG. 18 is only the EL element portion and the current controlling TFT, and therefore, the other description will be omitted.

In FIG. 20, the current control TFT 450
Reference numeral 3 uses a p-channel TFT formed by a known method.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of an insulating film
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 4701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

(Embodiment 10) In this embodiment, FIG.
FIGS. 21A to 21C illustrate an example in which a pixel having a structure different from that of the circuit diagram illustrated in FIG. In this embodiment, reference numeral 4801 denotes a switching TFT 480.
2, a source wiring (signal line), 4803, a gate wiring (scanning line) of the switching TFT 4802, 4804, a current controlling TFT, 4805, a storage capacitor, 4806, 48
08 is a power supply line, and 4807 is an EL element.

FIG. 21A shows an example in which a power supply line 4806 is shared between two pixels. That is, the feature is that two pixels are formed so as to be line-symmetric with respect to the power supply line 4806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 21B shows a power supply line 480.
This is an example in which 8 is provided in parallel with a gate wiring (scanning line) 4803. Note that the power supply line 480 is shown in FIG.
8 and the gate wiring (scanning line) 4803 are provided so as not to overlap with each other. However, as long as the wirings are formed in different layers, they may be provided so as to overlap with each other via an insulating film. In this case, an occupied area can be shared by the power supply line 4808 and the gate wiring (scanning line) 4803, so that the pixel portion can have higher definition.

FIG. 21C shows that the power supply line 4808 is connected to the gate wiring (scanning line) similarly to the structure of FIG. 21B.
4803, and two pixels are formed so as to be symmetric with respect to the power supply line 4808. It is also effective to provide the power supply line 4808 so as to overlap with one of the gate wirings (scanning lines) 4803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

(Embodiment 11) FIG. 19 shown in Embodiment 8
19A and 19B, a storage capacitor 4504 for holding a voltage applied to the gate of the current controlling TFT 4503.
Is provided, but the storage capacitor 4504 can be omitted. In the case of the eighth embodiment, the current control TF
An LDD region is provided on the drain side of T4503 so as to overlap the gate electrode with a gate insulating film interposed therebetween. A parasitic capacitance generally called a gate capacitance is formed in the overlapping region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the storage capacitor 4504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

In addition, FIG.
Similarly, in the structures of FIGS.
05 can be omitted.

(Embodiment 12) In this embodiment, electronic equipment incorporating the image display device of the present invention will be described. These electronic devices include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. Examples of those are shown in FIGS. However, for the active matrix type liquid crystal display device among the image display devices, FIGS. 22, 23 and 24 are applied, and EL
FIGS. 22 and 23 are applied to the display device.

FIG. 22A shows a mobile phone,
01, audio output unit 9002, audio input unit 9003, display unit 9004, operation switch 9005, antenna 9006
It is composed of The present invention can be applied to the display portion 9004.

FIG. 22B shows a video camera, which includes a main body 9101, a display portion 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 910.
Consists of six. The present invention can be applied to the display portion 9102.

FIG. 22C shows a mobile computer or a portable information terminal which is a kind of personal computer, and includes a main body 9201, a camera section 9202, and an image receiving section 92.
03, an operation switch 9204, and a display unit 9205. The present invention can be applied to the display portion 9205.

FIG. 22D shows a head-mounted display (goggle type display).
A display portion 9302 and an arm portion 9303 are provided. The present invention can be applied to the display portion 9302.

FIG. 22E shows a television set, which includes a main body 940.
1, speaker 9402, display portion 9403, receiving device 94
04, an amplification device 9405 and the like. The invention can be applied to the display portion 9402.

FIG. 22F shows a portable book, and a main body 95.
01, a display unit 9502, a storage medium 9504, operation switches 9505, and an antenna 9506.
It displays the data stored in the satellite disc) and the data received by the antenna. The invention can be applied to the display portion 9502.

FIG. 23A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display section 96.
03, and a keyboard 9604. The present invention can be applied to the display portion 9603.

FIG. 23B shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 9701, a display portion 9702, and a speaker portion 970.
3, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD, a CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 9702.

FIG. 23C shows a digital camera, which comprises a main body 9801, a display portion 9802, an eyepiece portion 9803, operation switches 9804, and an image receiving portion (not shown).
The present invention can be applied to the display portion 9802.

FIG. 23D shows a head mounted display of one eye, in which a display portion 9901 and a head mounted portion 9 are provided.
902. The present invention can be applied to the display portion 9901.

FIG. 24A shows a front type projector, which comprises a projection device 3601 and a screen 3602.

FIG. 24B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3. It is composed of a screen 3704.

FIG. 24C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 24A and 24B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display unit 3808, retardation plate 3809,
It is composed of a projection optical system 3810. Projection optical system 3810
Is composed of an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but the present invention is not limited to this. For example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good. The present invention can be applied to the liquid crystal display portion 3808.

FIG. 24D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 24D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields using an image display device.

[0197]

The driving circuit of the image display device according to the present invention can greatly reduce the area of the signal line driving circuit, is effective for miniaturizing the image display device, and has a resistance parasitic on the wiring of the digital video signal. And the capacity are reduced, and the operation margin of the drive circuit is increased. These are effective in reducing the cost and improving the yield of the image display device.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a signal line driving circuit according to an embodiment.

FIG. 2 is a diagram showing operation timings of the signal line driving circuit of FIG.

FIG. 3 is a diagram illustrating a configuration of a signal line driving circuit according to the first embodiment.

FIG. 4 is a diagram showing operation timings of the signal line driving circuit of FIG. 3;

FIG. 5 is a diagram illustrating an example of a latch circuit.

FIG. 6 is a diagram illustrating a configuration of a signal line driving circuit according to a second embodiment.

7 is a diagram showing operation timings of the drive circuit of FIG.

FIG. 8 is a diagram showing a configuration of a bit comparison pulse width conversion circuit (BPC).

FIG. 9 is a diagram illustrating the operation of the ramp type D / A conversion circuit.

FIG. 10 is a diagram illustrating a configuration of a signal line driving circuit according to a third embodiment.

FIG. 11 is a diagram showing operation timings of the drive circuit of FIG.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 14 is a sectional view of an active matrix substrate.

FIG. 15 is a diagram showing a sectional structural view of an active matrix liquid crystal display device.

FIG. 16 illustrates an example of manufacturing an EL display device.

FIG. 17 illustrates an example of manufacturing an EL display device.

FIG. 18 illustrates an example of manufacturing an EL display device.

FIG. 19 illustrates an example of manufacturing an EL display device.

FIG. 20 illustrates an example of manufacturing an EL display device.

FIG. 21 illustrates an example of manufacturing an EL display device.

FIG. 22 is a diagram illustrating an example of an electronic device using the present invention.

FIG. 23 illustrates an example of an electronic device using the present invention.

FIG. 24 is a diagram showing a configuration of a projection type liquid crystal display device.

FIG. 25 is a configuration diagram of an active matrix liquid crystal display device.

FIG. 26 is a configuration diagram of a conventional digital signal line drive circuit.

FIG. 27 is a diagram showing a timing chart of a conventional digital signal line driving circuit.

[Explanation of symbols]

 Reference Signs List 10 (ad) Signal line selection circuit 20 Analog switch 30 Set reset flip-flop (RS-FF) 101 Signal line drive circuit 102 Scan line drive circuit 103 Pixel array unit 104 Signal line 105 Scan line 106 Pixel TFT 107 Liquid crystal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/30 G09G 3/30 J 3/36 3/36

Claims (33)

[Claims] A plurality of scanning lines; a plurality of scanning lines; a plurality of pixel electrodes provided in each region where each of the signal lines intersects with each of the scanning lines; A pixel array unit having a plurality of switching elements for driving the plurality of pixel electrodes; a signal line driving circuit for driving the k signal lines; and a scanning line driving circuit for driving the plurality of scanning lines Wherein the signal line drive circuit includes m or multiples of shift registers to which m-bit (m is a natural number) digital video signals are input, and an output signal of the shift registers. N × k (n is an integer of 2 or more) storage circuits for storing n, and a plurality of Ds for converting an output signal of the storage circuit into an analog signal
An image display device comprising: a / A conversion circuit; and n signal line selection circuits for n for sending an output signal of the D / A conversion circuit to a corresponding signal line. 2. A plurality of signal lines, a plurality of scanning lines, a plurality of pixel electrodes provided in respective regions where the respective signal lines intersect with the respective scanning lines, and a plurality of pixel electrodes for driving the plurality of pixel electrodes. A pixel array unit having a plurality of switching elements, a signal line driving circuit driving the plurality of signal lines, and a scanning line driving circuit driving the plurality of scanning lines. The signal line driver circuit includes a plurality of shift registers to which a plurality of bits of digital video signals are input, a plurality of storage circuits that store output signals of the shift registers, and converts an output signal of the storage circuit into an analog signal. A plurality of D / A conversion circuits; and a plurality of signal line selection circuits for sending output signals of the D / A conversion circuits to corresponding signal lines. The digital video signal is input to each of the shift registers. , The input digital video signal is sequentially shifted in each shift register until it is output to the corresponding storage circuit, and the shifted digital video signal is fetched into the storage circuit by a latch signal. 1
N times within the time corresponding to the horizontal scanning period (n is an integer of 2 or more)
An image display device characterized by repeating. 3. The three primary colors of light, R (red), G (green), and B
A signal line composed of multiples of three (hereinafter, referred to as k) in units of three signal lines corresponding to (blue), a plurality of scanning lines,
A pixel array unit having a plurality of pixel electrodes provided in each region where the signal lines and the scanning lines intersect, and a plurality of switching elements for driving the plurality of pixel electrodes; And a scanning line driving circuit for driving the plurality of scanning lines. The image display device for color display, wherein the signal line driving circuit is provided for each of the RGB. m
M or multiples of m shift registers to which a digital video signal of bits (m is a natural number) are inputted; and m × k (n is a multiple of 3) of n minutes for storing output signals of the shift registers A storage circuit, a plurality of D / A conversion circuits for converting an output signal of the storage circuit into an analog signal, and k signal lines of n for sending the output signal of the D / A conversion circuit to a corresponding signal line An image display device comprising: a selection circuit. 4. The three primary colors of light, R (red), G (green), and B
(Blue) signal lines each consisting of a multiple of 3 in units of three signal lines, a plurality of scanning lines, and a plurality of signal lines provided in each region where the signal lines intersect with the scanning lines. A pixel array unit having a pixel electrode and a plurality of switching elements for driving the plurality of pixel electrodes; a signal line driving circuit for driving a signal line having a multiple of 3; and the plurality of scanning lines And a scanning line driving circuit for driving the image display device, wherein the signal line driving circuit has m
A plurality of shift registers to which digital video signals of bits (m is a natural number) are input, a plurality of storage circuits for storing output signals of the shift registers, and a plurality of storage circuits for converting output signals of the storage circuits into analog signals A D / A conversion circuit; and a plurality of signal line selection circuits for sending output signals of the D / A conversion circuit to corresponding signal lines. A digital video signal corresponding to the R is input to each of the shift registers during the first period, and the digital video signal corresponding to the G is input to the shift register during the second period. The digital video signal corresponding to B is input to each shift register during the third period, and the input digital video signal is input within each of the three periods. Is Each shift register is sequentially shifted until it is output to the corresponding storage circuit, and the shifted digital video signal performs an operation to be taken into the storage circuit by a latch signal once or a plurality of times. Image display device. 5. The method according to claim 1, wherein
An image display device, wherein the number of / A conversion circuits is k for n. 6. An image display device according to claim 1, wherein said D / A conversion circuit is a ramp type D / A conversion circuit. 7. The image display device according to claim 1, wherein said storage circuit is a latch circuit. 8. The image display device according to claim 7, wherein said latch circuit has an analog switch and a storage capacitor. 9. The image display device according to claim 7, wherein said latch circuit has a clocked inverter. 10. The image display device according to claim 7, wherein said latch circuit has an analog switch and a plurality of inverters. 11. The image display device according to claim 1, wherein display is performed using a liquid crystal material. 12. The image display device according to claim 1, wherein display is performed using an electroluminescent (EL) material. 13. A mobile phone using the image display device according to claim 1. Description: 14. A video camera using the image display device according to any one of claims 1 to 12. 15. A personal computer using the image display device according to any one of claims 1 to 12. 16. A head-mounted display using the image display device according to claim 1. Description: 17. A television using the image display device according to claim 1. Description: 18. A portable book using the image display device according to any one of claims 1 to 12. 19. A digital camera comprising the image display device according to claim 1. Description:
VD player. 20. A digital camera using the image display device according to any one of claims 1 to 12. 21. A projector using the image display device according to any one of claims 1 to 11. 22. A signal line driving circuit of an image display device for driving k (k is an integer of 2 or more) signal lines, wherein the signal line driving circuit converts an m-bit (m is a natural number) digital video signal. M or multiples of m input shift registers, n × m (n is an integer of 2 or more) memory circuits for storing output signals of the shift registers, and output signals of the memory circuits To convert analog signals into analog signals
A driving circuit for an image display device, comprising: a / A conversion circuit; and k signal line selection circuits for n for sending an output signal of the D / A conversion circuit to a corresponding signal line. 23. A signal line driving circuit of an image display device for driving a plurality of signal lines, the signal line driving circuit comprising: a plurality of shift registers to which a plurality of bits of digital video signals are input; A plurality of storage circuits for storing output signals; a plurality of D / A conversion circuits for converting output signals of the storage circuits into analog signals; and a plurality of output circuits for sending output signals of the D / A conversion circuits to corresponding signal lines The digital video signal is input to each of the shift registers, and the input digital video signals are sequentially output from the respective shift registers to the corresponding storage circuits. The shifted digital video signal is shifted by the latch signal into the storage circuit by one operation.
N times within the time corresponding to the horizontal scanning period (n is an integer of 2 or more)
A driving circuit for an image display device, wherein the driving circuit is repeated. 24. R (red), G (green), three primary colors of light,
A signal line driving circuit of an image display device for driving a signal line composed of multiples of 3 (hereinafter, referred to as k) in units of three signal lines corresponding to B (blue), wherein the signal line driving circuit is , M for each of the RGB
M or multiples of m shift registers to which a digital video signal of bits (m is a natural number) are inputted; and m × k (n is a multiple of 3) of n minutes for storing output signals of the shift registers A storage circuit, a plurality of D / A conversion circuits for converting an output signal of the storage circuit into an analog signal, and k signal lines of n for sending the output signal of the D / A conversion circuit to a corresponding signal line A drive circuit for an image display device, comprising: a selection circuit. 25. R (red), G (green), three primary colors of light,
In a signal line driving circuit of an image display device for driving a signal line composed of multiples of 3 in units of three signal lines corresponding to B (blue), the signal line driving circuit is configured to have m signals for each of the RGB.
A plurality of shift registers to which digital video signals of bits (m is a natural number) are input, a plurality of storage circuits for storing output signals of the shift registers, and a plurality of storage circuits for converting output signals of the storage circuits into analog signals A D / A conversion circuit; and a plurality of signal line selection circuits for sending output signals of the D / A conversion circuit to corresponding signal lines. A digital video signal corresponding to the R is input to each of the shift registers during the first period, and the digital video signal corresponding to the G is input to the shift register during the second period. The digital video signal corresponding to B is input to each shift register during the third period, and the input digital video signal is input within each of the three periods. Is Each shift register is sequentially shifted until it is output to the corresponding storage circuit, and the shifted digital video signal performs an operation to be taken into the storage circuit by a latch signal once or a plurality of times. Drive circuit for an image display device. 26. The method according to claim 22, wherein
A driving circuit for an image display device, wherein the number of the D / A conversion circuits is k for n. 27. Any one of claims 22 to 25
3. The driving circuit for an image display device according to claim 1, wherein the D / A conversion circuit is a ramp type D / A conversion circuit. 28. Any one of claims 22 to 27.
9. The driving circuit according to claim 1, wherein the storage circuit is a latch circuit. 29. The driving circuit according to claim 28, wherein said latch circuit has an analog switch and a storage capacitor. 30. A driving circuit according to claim 28, wherein said latch circuit has a clocked inverter. 31. A driving circuit according to claim 28, wherein said latch circuit has an analog switch and a plurality of inverters. 32. One of claims 22 to 31
9. The driving circuit for an image display device according to claim 1, wherein the driving circuit for the image display device is formed of a polysilicon thin film transistor. 33. Any one of claims 22 to 31
9. The driving circuit for an image display device according to claim 1, wherein the driving circuit for the image display device is formed of a single crystal transistor.