JP2001309469A - Digital exchange apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correspond to CTI, without using a private resource for performing exchange and connection for CTI and as a result to realize a digital exchange apparatus with a simple constitution. SOLUTION: Whole tristate buffers 16 are set forcedly made settable to a high impedance state, by closing an AND gate by an inhibition control part 93. A control CPU 91 sets a time slot, corresponding to the channel of a non-use state for CTI. In a time slot period for CTI, the inhibit control part 93 forcedly sets the whole tristate buffers 16 in the high impedance state. In the time slot period for CTI, transmission data for CTI are transmitted from a CTI part 8 to a TSW extension bus 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital exchange applied to a key telephone, a PBX, and the like.

[0002]

2. Description of the Related Art In recent years, a CTI (Computer Telephony Integrati) that enables services such as voice processing and IVR (Interactive Voice Response) using a computer.
on) has become popular, and it has become necessary for digital exchange devices such as key telephones and PBXs to support CTI.

FIG. 3 is a block diagram showing the configuration of a main part of a conventional digital switching apparatus configured to support CTI.

In FIG. 1, reference numeral 1 denotes a time switch. To this time switch 1, m incoming highways 2 (2-1,... 2-k, 2-m) and outgoing highways 3 (3-1,... 3-k, 3-m) are connected. ing. In FIG. 3, “k” corresponds to [m−1].

In the time switch 1, signals arriving via each of the incoming highways 2 are parallelized by serial / parallel conversion circuits (S / P conversion circuits) 11 (11-1,... 11-k, 11-m). After that, the signal is time-division multiplexed by the multiplexing circuit 12 into one parallel signal. For example, n codecs 4 (4-1, 4-2..., 4-n) are connected to the incoming highway 2 as shown with respect to the incoming highway 2-1. Transmission data of four to one channel are to be transmitted in bursts at different timings, and each of them accommodates n channels. Therefore, data of m × n channels is time-division multiplexed on the output signal of the multiplexing circuit 12. The codec 4 is connected to a communication line (extension or office line) connected to a communication terminal or a communication network, and the codec 4 receives a transmission signal arriving via this communication line and enters the input highway 2. Send to.

The data of m × n channels are sequentially written in the exchange memory 13.

The data written in the exchange memory 13 is
The data is output from the exchange memory 13 in the time slot assigned to the output destination. Thus, a signal in which m × n channels of data are arranged in a different order from that when the data is output from the multiplexing circuit 12 is created.
Given to.

The separation circuit 14 extracts data for each of n channels from the signal output from the exchange memory 13,
Separate into m signals. The m signals separated here are serialized by m parallel / serial conversion circuits (P / S conversion circuits) 15 (15-1,... 15-k, 15-m), respectively. It is sent to each of the outgoing highways 3-1 to 3-m.

The entry highway 2 and the exit highway 3
One pair is formed, and as shown with respect to the incoming highway 2-1 and the outgoing highway 3-1, the same codec 4 is provided on the paired incoming highway 2-1 and outgoing highway 3-1. Connected.

Thus, by arbitrarily changing the output order of the data of each channel from the exchange memory 13, each channel on the input side and each channel on the output side can be exchanged, and arbitrary channel exchange can be performed. It is.

Originally, the incoming highway 2 and the outgoing highway 3 are all used for accommodating extensions and office lines, but at least one pair of the incoming highway 2 and the outgoing highway 3 are used to accommodate the CTI. Assigned for. In the example of FIG. 3, the incoming highway 2-m and the outgoing highway 3-m are allocated for CTI.

A CTI unit 8 is connected to the incoming highway 2-m and the outgoing highway 3-m assigned for the CTI, and the CTI unit 8 is connected to the CTI unit 8 via a H110 bus 6 by a computer. Is realized.

However, when the input highway 2 and the output highway 3 dedicated to the CTI are set as described above, and the CTI channel formed thereby is switched and connected to an arbitrary communication line, the CTI is thus changed. Will have an extra configuration for users who do not need
There is much waste in the circuit.

[0014]

As described above, in the conventional digital switching device, since a part of the incoming highway and the outgoing highway is provided with a dedicated resource for performing the switching connection for the CTI, the circuit is not provided. There was a problem that large waste was large.

The present invention has been made in view of such circumstances, and an object of the present invention is to support CTI without using a dedicated resource for performing switching connection for CTI. Accordingly, it is an object of the present invention to provide a digital exchange device which can be realized with a simple configuration.

[0016]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for transmitting data on k channels, for example, a data bus such as a TSW extension bus in which k time slots are set in a unit time. After each transmission data is stored in the memory, the switching connection is performed by arbitrarily outputting the transmission data to the k-channel outgoing channel, and the transmission data such as CTI transmission data arriving on at least one special incoming channel. Outputting special transmission data to the data bus at an arbitrary time slot timing, for example, C
In a digital switching device in which a special data output device such as a TI unit can be connected to the data bus, each of the normal transmission data arriving on k normal input channels is output at the timing of a time slot corresponding to each channel. A normal data output means including, for example, an S / P conversion circuit and a tri-state buffer; a first state in which normal transmission data output from the normal data output means is output to the data bus; and the normal data as viewed from the data bus. A second method in which the output means side has a high impedance
A gate means such as a tri-state buffer capable of selectively taking a state; and a slot allocating means comprising, for example, a control CPU, an inhibit control unit and an AND gate, and transmission of valid normal transmission data by the slot allocating means. At the timing of a time slot corresponding to a predetermined normal incoming channel among the normal incoming channels that are not used, the gate means is set to the second state, and the special data output device sets the time slot to the special data. Assigned as a time slot for output.

By taking such means, the transmission data of k channels transmitted through the data buses whose time slots are set to the same number as the number of normal input channels are respectively stored in the memory, and then the output channels of k channels are stored. The exchange connection is performed by arbitrarily outputting to
In a time slot corresponding to a predetermined normal input channel among normal input channels not used for transmission of valid normal transmission data, the normal data output means side as viewed from the data bus is set to high impedance by gate means. When the special data output device is used as a time slot for outputting the special data, the special data is exchanged and output. Therefore, the exchange output of the special data is realized without setting a dedicated time slot for the special data.

Further, the present invention further comprises a normal data output means provided with a gate circuit such as a tri-state buffer which can be in a high impedance state when viewed from the data bus except at the output timing of the normal transmission data. The gate means is realized by diverting the gate circuit.

By taking such means, the gate circuit provided in the normal data output means allows the special data output device to output the special data from the data bus during the time slot period for outputting the special data. The means side is set to high impedance. Therefore, it is not necessary to newly provide a gate circuit to realize the gate means.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a main part of a digital exchange according to the present embodiment. The same parts as those in FIG. 3 are denoted by the same reference numerals.

As shown in this figure, the digital exchange of the present embodiment has m incoming highways 2 (2-1 to 2-m).
And an outgoing highway 3 (3-1 to 3-m), a number of codecs 4 (only 4-1 to 4-n are shown in the figure), an H110 bus 6, a time switch 7, a CTI unit 8, and a control unit 9. are doing.

The incoming highway 2 and the outgoing highway 3
Each one is a pair. A codec 4 is commonly connected to the incoming highway 2 and the outgoing highway 3 for pairing. A maximum of n codecs 4 (4-1 to 4-n) (n is the number of multiplexes on the incoming highway 2 and the outgoing highway 3) can be connected to the pair of incoming highway 2 and outgoing highway 3. FIG. 1 shows the connection status of the codec 4 with respect to the ingress highway 2-1 and the egress highway 3-1.
Is connected.

The time switch 7 is connected to the codec 4
, The PCM data transmitted to the channel assigned to each codec 4 on the incoming highway 2, and these PCM data are transmitted to the codec 4 connected to the output source codec 4 on the output highway. By transmitting to the assigned channel, the exchange connection between the codecs 4 is performed.

The time switch 7 includes m serial / parallel converters (S / P converters) 11 (11-1 to 11-m),
Exchange memory 13, separation circuit 14, m parallel / serial conversion circuits (P / S conversion circuits) 15 (15-1 to 15-m),
It has m tri-state buffers 16 (16-1 to 16-m), a time switch extension bus (TSW extension bus) 17, and an address generator 18.

The signals arriving via each of the incoming highways 2 are parallelized by a serial / parallel conversion circuit (S / P conversion circuit) 11 (11-1,..., 11-k, 11-m), respectively. Each transmission data of each channel included in this signal is output at the timing of the time slot allocated on the TSW expansion bus 17 for each channel. Then, the transmission signal output from the S / P conversion circuit 11 is transmitted to the TSW extension bus 17 via the tristate buffer 16. As a result, data obtained by time-division multiplexing of transmission data for m × n channels is transmitted on the TSW extension bus 17.

The data of m × n channels are sequentially written in the exchange memory 13.

The data written in the exchange memory 13 is
The data is output from the exchange memory 13 in the time slot assigned to the output destination. Thus, a signal in which the data of m × n channels are arranged in a different order from that when the data is output from the multiplexing circuit 12 (see FIG. 3) is created and supplied to the separating circuit 14.

The separation circuit 14 extracts data for each of n channels from the signal output from the exchange memory 13,
Separate into book signals. The m signals separated here are serialized by the m P / S conversion circuits 15, respectively, and then sent out to each of the outgoing highways 3.

The change in the output order of the data from the exchange memory 13 is realized by the address generation section 18 changing the generation order of the read addresses in accordance with an instruction from the control unit 9. The address generator 18 has a connection memory 18a, and information indicating the order in which read addresses are generated is transmitted by the control unit 9 to the connection memory 18a.
is written to a. And this connection memory 18
The order in which the read addresses are generated is determined according to the information written in a.

The CTI unit 8 comprises an H110 interface (H110 I / F) 81, a tristate buffer 82
And a time slot control unit 83.

The H110 interface 81 is an H110
It is interposed between the bus 6 and the TSW extension bus 17 and performs interface processing for sending data transmitted on both buses to the other bus.

The tri-state buffer 82 has an H110
It is interposed between the output terminal of the interface 81 on the TSW extension bus 17 side and the TSW extension bus 17. Under the control of the time slot control unit 83, the tri-state buffer 82 outputs the data output from the H110 interface 81 to the TSW extension bus 17, and outputs the data to the TSW extension bus 17 of the H110 interface 81.
The state is such that the output terminal on the side is in a high impedance state when viewed from the TSW extension bus 17.

The time slot control unit 83 controls the tristate buffer 82 to pass data only at the timing of the time slot allocated for CTI by the control unit 9.

The control unit 9 includes a control CPU 91, an extended bus transmission control unit 92, an inhibit control unit 93 and m
AND gates 94 (94-1 to 94-m). The control CPU 91, the extended bus sending control unit 92, and the inhibit control unit 93 are connected to each other via a CPU bus 95.

The control CPU 91 controls the operations of the CTI unit 8 and the time switch 7 so as to realize a function as a digital exchange.

The extended bus transmission control section 92 sets only the tri-state buffer 16 corresponding to the S / P conversion circuit 11 at the data output timing to the data passing state, and sets the other tri-state buffers 16 to the high impedance state. , And outputs a transmission control signal S1 (S1-1 to S1-m) to each of the tristate buffers 16-1 to 16-m.

The inhibit control section 93 closes each AND gate 94 at the timing of the time slot allocated for CTI, and outputs an inhibit signal to open the AND gate 94 at the timing of the other time slots to the AND gate 94. I do.

Transmission control signals S1-1 to S1-m are supplied to AND gates 94-1 to 94-m, respectively. Further, an inhibit signal is given to each of the AND gates 94-1 to 94-m. The AND gates 94-1 to 94-m turn ON / OF the transmission of the transmission control signals S1-1 to S1-m to the tri-state buffers 16-1 to 16-m according to the state of the inhibit signal.
F.

Next, the operation of the digital exchange device configured as described above will be described.

On the incoming highway 2, transmission data for n channels is transmitted serially for one frame period.
The transmission data for these n channels is represented by the corresponding S / P
The signal is input to the conversion circuit 11, parallelized and latched, and output over a period of 1 / n frame. Thus, from each of the S / P conversion circuits 11-1 to 11-m,
Transmission data of different channels are output simultaneously.

On the other hand, in the TSW expansion bus 17, m × n time slots T _{1 to} T _mn are set per frame period as shown in FIG. Therefore, the extension bus transmission control unit 92 sets the transmission control signals S1-1 to S1-m to the "H" level in the order of the transmission control signals S1-1, S1-2,. The signal is as shown in FIG.

The inhibit control unit 93 is provided with the codec 4
At the timing of the time slot corresponding to the channel on which valid transmission data is transmitted, the inhibit signal is set to “L”. Accordingly, at the timing of such a time slot, each AND gate 94 is open, and the transmission control signals S1-1 to S1-m are supplied to the tristate buffers 16-1 to 16-m, respectively.

As a result, transmission data of m channels simultaneously output from each of the S / P conversion circuits 11-1 to 11-m is time-division multiplexed on the TSW extension bus 17 in a 1 / n frame period. By repeating such an operation n times in one frame period, m × n channel transmission data is time-division multiplexed on the TSW extension bus 17 in one frame period.

By the way, one or a plurality of codecs 4 are mounted on one card, and this card can be arbitrarily attached to a port. And the channels on Incoming Highway 2 and Outgoing Highway 3
In fact, they are associated with ports.

Therefore, although a channel corresponding to a port on which no card is mounted physically exists, valid transmission data is not transmitted. In the case of a card supporting ISDN, two channels are secured for one line. However, it is rare that two B channels in an ISDN line are fully used. In many cases, valid transmission data is not transmitted in the channel corresponding to the second B channel.

Therefore, control CPU 91 sets a time slot corresponding to such an unused channel for CTI, and sets it to inhibit control unit 93 and CTI.
The time slot control unit 83 of the unit 8 is designated. In addition,
If the number of time slots corresponding to unused channels is larger than the number of time slots required for CTI, for example, it is necessary to use the number of time slots corresponding to unused channels for CTI. Any number of time slots may be selected, or a required number of time slots may be selected according to a predetermined rule (priority or the like).

The inhibit control unit 93 sets the inhibit signal to "L" at the timing of the time slot designated for CTI by the control CPU 91 as described above. FIG. 2 shows an example in which time slot T ₂ and time slot T _{m + 1} are set for CTI.

In the time slot period in which the inhibit signal is at "L", each AND gate 94
Is closed, and accordingly, each tri-state buffer 16 also enters the high impedance state. Thus, during the time slot period set for CTI, each S / P conversion circuit 11 does not participate in the TSW extension bus 17.

On the other hand, in the CTI section 8, the time slot control section 83 outputs the transmission data for CTI during the time slot period set for CTI as shown in FIG.
During the other periods, the H
The state of the tri-state buffer 82 is controlled so that the 110 interface 81 is in a high impedance state. The transmission data for CTI is provided from a computer (not shown) to the H110 interface 81 via the H110 bus 6, and includes, for example, processed PCM data and PCM data indicating an IVR message.
Data.

Thus, the multiplexed data transmitted on the TSW extension bus 17 includes transmission data for CTI. The transmission data including the transmission data for the CTI is once written in the exchange memory 13 and then read out in a different order to be provided to the appropriate codec 4.

As described above, according to the present embodiment, the TSW
Only the same number of time slots as the maximum number of accommodated lines are set in the expansion bus 17, and time slots not used for transmitting valid transmission data among these time slots are used for transmitting transmission data for CTI. Used. In this way, during the time slot used for transmitting the transmission data for the CTI, all the tri-state buffers 16 are forcibly set to the high impedance state, so that transmission of the transmission data for the CTI is not hindered. I can do it. Therefore, there is no need to provide a dedicated channel for inputting / outputting transmission data for CTI, and it is possible to realize a simple configuration without waste.

Further, according to the present embodiment, in order to set all the S / P conversion circuits 11 to a high impedance state as viewed from the TSW extension bus 17, transmission data arriving via each incoming highway 2 is reduced to one. Since the tri-state buffer 16 for multiplexing is diverted, it is not necessary to provide a new gate circuit, so that it can be realized with a simpler configuration.

The present invention is not limited to the above embodiment. For example, in the above embodiment, all S / P
In order to bring the conversion circuit 11 into a high impedance state when viewed from the TSW extension bus 17, a tri-state buffer 16 for multiplexing transmission data arriving via each incoming highway 2 into one is diverted. In addition to the tri-state buffer 16, a gate means such as a tri-state buffer may be provided.

In addition, various modifications can be made without departing from the gist of the present invention.

[0056]

According to the present invention, transmission data for k channels transmitted on a data bus in which k time slots are set in a unit time are stored in a memory, and then the data is transmitted to an output channel of k channels. And a special data output device for outputting the special transmission data arriving through at least one special incoming channel to the database at an arbitrary time slot timing. In a digital switching device connectable to a data bus, a normal data output means for outputting each of normal transmission data arriving on k normal input channels at timing of a time slot corresponding to each channel; A first state in which normal transmission data output by the means is output to the data bus; Gate means capable of selectively taking a second state in which the normal data output means side as a high impedance when viewed from the source is provided, and slot allocating means, and the slot allocating means is used to transmit valid normal transmission data. At the timing of a time slot corresponding to a predetermined normal input channel among the normal input channels that are not used, the gate unit is set to the second state at the timing of the time slot,
Since the time slot is assigned as a time slot for the special data output device to output the special data, the exchange output of the special data is realized without setting a special time slot for the special data. As a result, a digital switching device that can support CTI without using a dedicated resource for performing switching connection for CTI is provided, and can be realized with a simple configuration.

Further, according to the present invention, the normal data output means further includes a gate circuit which can take a state of high impedance when viewed from the data bus other than the output timing of the normal transmission data, and Since the gate means is realized by diverting the gate circuit, there is no need to newly provide a gate circuit for realizing the gate means, and a digital switching device capable of further simplifying the configuration. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a digital exchange according to an embodiment of the present invention.

FIG. 2 is a timing chart showing transmission timing of transmission data to a TSW extension bus 17 in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a main part of a conventional digital exchange configured to support CTI.

[Explanation of symbols]

2 (2-1 to 2-m) ... incoming highway 3 (3-1 to 3-m) ... outgoing highway 4 (4-1 to 4-n) ... codec 6 ... H110 bus 7 ... time switch 8 ... CTI section 9 Control unit 11 (11-1 to 11-m) Serial / parallel conversion circuit (S
/ P conversion circuit) 13: Exchange memory 14: Separation circuit 15 (15-1 to 15-m): Parallel / serial conversion circuit (P
/ S conversion circuit) 16 (16-1 to 16-m) tristate buffer 17 TSW expansion bus 18 address generator 18a connection memory 81 H110 interface 82 tristate buffer 83 time slot controller 91 Control CPU 92: Extended bus transmission control unit 93: Inhibit control unit 94 (94-1 to 94-m): AND gate 95: CPU bus

Claims (2)

[Claims] 1. A method for storing transmission data for k channels transmitted through a data bus in which k time slots are set within a unit time in a memory, and arbitrarily outputting the transmission data to an output channel of k channels. And a special data output device that outputs special transmission data arriving on at least one special input channel to the database at an arbitrary time slot timing can be connected to the data bus. A normal data output means for outputting each of the normal transmission data arriving at the k normal input channels at a timing of a time slot corresponding to each channel, and a normal transmission output by the normal data output means. A first state of outputting data to the data bus and the first state as viewed from the data bus; Gate means capable of selectively taking a second state in which the normal data output means has a high impedance, and a time corresponding to a predetermined normal input channel among normal input channels not used for transmitting valid normal transmission data Slot timing means for setting the gate means to the second state at the slot timing and allocating the time slot as a time slot for the special data output device to output the special data. Digital switching equipment. 2. The normal data output means includes a gate circuit capable of attaining a high impedance when viewed from the data bus other than at an output timing of normal transmission data. 2. The digital exchange according to claim 1, wherein the digital exchange is realized by utilizing