JP2001308336A - Thin film transistor substrate and inspection method thereof - Google Patents

Abstract

(57) [Summary] PROBLEM TO BE SOLVED: To measure even when characteristic anisotropy is a problem.
The inspection is performed efficiently without increasing the number of times. A pattern is formed in two directions orthogonal to each other.
A pair of thin film transistors 15a and 15b
Thin film transistor with test elements connected in parallel
A substrate is used. In particular, use a glass substrate for the substrate
Polysilicon thin film (especially line thin
Irradiate an excimer laser beam shaped into a
Polycrystalline silicon thin film formed by melt crystallization)
Is a thin film transistor using anisotropic thin film material
Or n of the thin film transistor ⁺Region or p⁺Territory
Between the gate region and the LDD region
In a thin film transistor substrate that is created in a non-
Effective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate (hereinafter abbreviated as "TFT substrate"), and more particularly to a polysilicon thin film transistor (p.
Test elements for manufacturing a TFT substrate using Si-TFTs (such test patterns for process control and design are called test element groups; hereinafter, TE elements).
G) and an inspection method thereof.

[0002]

2. Description of the Related Art FIG. 5 shows the structure of a conventional TFT substrate for a liquid crystal display device, where (a) is a schematic plan view of the TFT substrate,
(B) is a plan view showing an example of a TEG pattern, and (c) is a sectional view showing an example of a TEG pattern.

[0005] In FIG. 5 (a), a glass substrate 1 is a large-sized substrate of several tens of cm square. Usually, a plurality of TFT arrays 2 used for a liquid crystal display device are arranged in a matrix on the glass substrate 1. In a conventional TFT substrate for a liquid crystal display device, a TEG block 3 for process management is arranged in the same manner as when an LSI is manufactured.

As shown in FIG. 5A, the TEG block 3 is arranged in the gap or the periphery of the TFT array 2 or is arranged in the TFT array 2 which is shipped as a product. In the TEG block 3, a thin film transistor (TFT), a resistance evaluation element of each conductive material, a contact evaluation element between each conductive material, a capacitance evaluation element, and the like are usually formed.

FIG. 5B is an example of a TEG pattern 3 and is a plan pattern diagram of a TEG for evaluating the characteristics of a p-Si TFT. The gate electrode, source electrode, and drain electrode of the TFT 5 are connected to the three measurement pads 4b, 4a, 4c, respectively. Arrow 6 in the figure indicates the direction of current flow (channel direction). Measurement pad 4
a, 4c and the TFT 5 between the source / drain wiring 11
Are provided, and a gate electrode 9 is provided between the measurement pad 4 b and the TFT 5.

FIG. 5C shows a schematic sectional view of the TEG pattern 3. In FIG. 5C, a semiconductor layer (polysilicon thin film) 7 patterned to the size of the TFT 5 is formed on the glass substrate 1, and a gate insulating film 8 and a gate electrode 9 are formed thereon. An interlayer insulating film 10 is provided on the gate insulating film 8, a source / drain wiring 11 connected to a source / drain region in the semiconductor layer 7 is further provided thereon, and a passivation film 12 is provided thereon. ing.

The portion of the polysilicon thin film 7 that is not covered with the gate electrode 9 is doped (impurity implantation), and the contact portion 16 is an n ⁺ or p ⁺ region. The side portion is an LDD region (lightly doped drain region: n ⁻ region or p ⁻ region) 13.

[0008]

SUMMARY OF THE INVENTION As described above, the conventional T
FT substrates are often prone to anisotropy in various characteristics. In particular, it is remarkable in the case of using a large-sized substrate for a liquid crystal display device. For example, the anisotropy of the photolithography process (mask alignment deviation, uniaxial exposure unevenness due to optical system fluctuation, etc.), the anisotropy of the etching process (chemical solution flow, cleaning displacement unevenness, etc.), anisotropy of the thin film material ( In particular,
Film formation while transporting the substrate in one direction such as belt transport type normal pressure CVD or in-line type sputtering.
Large anisotropy easily occurs in stress and resistance). As a result, various characteristics of the TFT substrate vary.

In particular, a silicon thin film is irradiated with an excimer laser formed into a line beam, which has recently attracted attention, and melt-crystallized to form a polysilicon thin film. In a low-temperature polysilicon TFT substrate using this, a polysilicon thin film is used. Since the laser irradiation has a large anisotropy, an extremely large characteristic anisotropy is likely to occur if the processing conditions are incorrect. Also,
When the boundary between the high dose region and the low dose region (LDD region) is formed without using a self-alignment method with respect to the gate electrode in the TFT structure, the TFT characteristics greatly change depending on the size of the LDD region. Strict management is required to secure them.

FIG. 6 shows an n-type thin film transistor (n-type TF).
T) shows a typical failure. (A) is a graph showing an OFF defect, and (b) is a graph showing an ON defect. In the graph, the horizontal axis is the gate voltage Vg, and the vertical axis is the drain current (logarithmic plot) Log (Id). The region where the current value is small is the OFF region, and the region where the current value is large is the ON region. (A),
Each solid line in (b) conforms to the characteristic originally intended to be created.

On the other hand, in the characteristic indicated by the broken line in FIG. 3A, the current in the OFF region jumps as indicated by the arrow. This is likely to occur when the size of the LDD region changes (becomes smaller), when the LDD region is not self-aligned, shifts in one of the channel directions, or when there is an abnormality in the dose. In particular, pixel TFTs for liquid crystal display devices
In the case of (screen TFT), the signal holding ability is affected,
The display quality is significantly reduced.

In the characteristic shown by the broken line in (b), the current in the ON region is greatly reduced as indicated by the arrow. This also tends to occur when the size of the LDD region changes, when the LDD region shifts in one of the channel directions, or when there is an abnormality in the dose.

Therefore, when there is only a TEG pattern in only one direction in the manufacturing process, it may not be possible to find these anisotropic abnormalities. In order to simply avoid this problem, two types of TEG patterns (usually in two directions of the vertical and horizontal sides of the substrate) are prepared for each evaluation item, and when there is no problem of anisotropy. A double measurement will be performed. However, inspection (T
Doubling the EG pattern and the inspection itself) is not welcomed due to productivity and capital investment.

The present invention focuses on the above points, and a TFT substrate having a TEG and a method of inspecting the TFT substrate, which can efficiently perform an inspection without doubling the number of measurements even when characteristic anisotropy is a problem. It is intended to provide.

[0015]

According to the present invention, there is provided a thin film transistor substrate having a test element in which a pair of unit elements patterned in two orthogonal directions are connected in series or in parallel. . In particular,
A glass substrate is used as the substrate, and the semiconductor layer is made of a polysilicon thin film (especially a polysilicon thin film formed by irradiating a silicon thin film with an excimer laser beam shaped into a line beam and melt-crystallizing it), stress or resistance. This is more effective for a thin film transistor using a thin film material having a property, or a thin film transistor substrate formed by a method in which the boundary between the n ⁺ region or p ⁺ region and the LDD region of the thin film transistor is not self-aligned with the gate electrode.

As the pair of unit elements, a thin film transistor, an inverter element using the thin film transistor, a resistance element, or the like can be considered.

The method of inspecting the thin film transistor substrate is to judge that a process abnormality has occurred when the current value between the terminals of the inspection element in which a pair of unit elements is connected in series or in parallel deviates from a specified value. .

According to the present invention, the above configuration or method enables a TEG to efficiently perform an inspection without doubling the number of measurements even when characteristic anisotropy is a problem.
And an efficient inspection method thereof.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1A and 1B
(2) A test element (pattern in a TEG block) in which a pair of TFT elements, which are a pair of unit elements formed in a pattern in two orthogonal directions, are connected in parallel.
1 shows a plan view and a circuit diagram of FIG.

In FIG. 1, the process of forming the thin film transistor itself is the same as that of the conventional example. Amorphous silicon is formed on a glass substrate of 50 cm class (for example, Corning # 1733), and XeCl It is made using a polysilicon thin film obtained by irradiating an excimer laser beam, and also has a cross-sectional structure similar to that of FIG.

The boundary between the n ⁺ region and the LDD region (n ^- region) of the thin film transistor is formed by using a photolithography process requiring mask alignment. Also,
The overall structure of the thin film transistor substrate is the same as that shown in FIG. 5A, and a detailed description is omitted here.

In this embodiment, as shown in FIG. 1A, two TFTs 15a and 15b are arranged (patterned) in a direction perpendicular to each other, and
5a and 15b are connected in parallel as shown in FIG. The measuring pads 14a, 14c and the TFT 15a,
Source / drain wirings 17 are provided between the pads 15b, respectively, and a gate electrode 18 is provided between the measurement pad 14b and the TFTs 15a and 15b.

With this TEG pattern, the TFT characteristics are turned off.
When the characteristic evaluation is performed, if one of the TFTs 15a and 15b becomes abnormal and the OFF current jumps, it can be detected and excluded by one probing and one measurement.

For example, if the OFF current value at Vg = −20 V in FIG. 6A is equal to or more than 1E−10 (= 1 × 10 ⁻¹⁰ ) amps, it is considered that this corresponds to a process failure. In this case, when a value equal to or larger than 2E-10 (= 2 × 10 ⁻¹⁰ ) amperes is detected, a failure is set. In the conventional measurement, two probing operations and two measurement operations are required to detect two TEG patterns in which a single TFT is orthogonalized, which requires twice as many steps.

According to this embodiment, even when the characteristic anisotropy becomes a problem, the inspection of the OFF current can be carried out efficiently without increasing the number of measurements twice.

(Second Embodiment) FIGS. 2A and 2B
(2) A test element (pattern in a TEG block) in which a pair of TFT elements, which are a pair of unit elements, each of which is patterned in two orthogonal directions, are connected in series.
1 shows a plan view and a circuit diagram of FIG.

In FIG. 2, the manufacturing process of the thin film transistor itself is the same as that of the first embodiment, and the detailed description is omitted here.

In this embodiment, as shown in FIG. 2A, two TFTs 25a and 25b are arranged (patterned) in a direction orthogonal to each other, and
5a and 25b are connected in series as shown in FIG. The measuring pads 24a, 24c and the TFT 25a,
Source / drain wires 26 are provided between the gate electrodes 25b, respectively, and a gate electrode 27 is provided between the measurement pad 24b and the TFTs 25a and 25b.

When the ON characteristics of the TFT characteristics are evaluated using this TEG pattern, when one of the TFTs 25a and 25b becomes abnormal and the ON current is reduced, it is set to 1
Defects can be excluded with a single probing and a single measurement. Incidentally, in the conventional measurement, two probings and two
It took twice as many man-hours to detect in a single measurement.

According to this embodiment, even when the characteristic anisotropy becomes a problem, the inspection of the OFF current can be carried out efficiently without increasing the number of measurements twice.

(Third Embodiment) FIG. 3 shows a test element (in a TEG block) in which a pair of inverter elements, which are a pair of unit elements formed in two orthogonal directions, are connected in parallel. FIG. The manufacturing process of the TFTs themselves constituting each of the inverter elements is the same as in the first embodiment, and the detailed description is omitted here.

In the present embodiment, as shown in FIG.
The inverter elements 30a and 30b are arranged (patterned) in directions orthogonal to each other. Each of the inverter elements 30a and 30b is composed of n-type and p-type CMOS TFTs. Source / drain wires 31 are provided between the measuring pads 34a and 34c and the TFTs forming the inverter elements 30a and 30b, respectively, and between the measuring pad 34b and the TFTs forming the inverter elements 30a and 30b. A gate electrode 32 is provided.

When the standby current of the inverter is evaluated using this TEG pattern, if one of the inverter elements 30a and 30b becomes abnormal and the standby current increases, it is detected by one probing and one measurement. Defects can be excluded. In the conventional measurement, two TEG patterns in which a single inverter
It took twice as many man-hours to detect by two probings and two measurements.

According to this embodiment, even when the characteristic anisotropy is a problem, the standby current can be inspected efficiently without increasing the number of measurements twice.

(Fourth Embodiment) FIG. 4 shows a test element (TEG block) according to the present invention in which a pair of resistive elements, which are a pair of unit elements patterned in two orthogonal directions, are connected in series. FIG.

Two resistance elements 40a and 40b are arranged in a direction perpendicular to each other (a direction in which current flows perpendicularly). The wiring 41 is provided between the measuring pads 44a, 44b, 44c and the resistance elements 40a, 40b, respectively.

The resistance value is evaluated using this TEG pattern.
And one of the resistance elements 40a and 40b is
If the resistance value increases due to an abnormal condition, it must be
Defects can be excluded by bing and one measurement. Obedience
In the next measurement, two TEGs with a single resistance element orthogonal
The pattern is detected by two probings and two measurements.
It took twice as many steps to get out. In addition, the resistance element
As n⁺, P⁺, N ^-Such as doped polysilicon
A thin film. In particular, n^-The resistance of the area depends on each characteristic
This is important because it has a large effect on

According to this embodiment, even when the characteristic anisotropy becomes a problem, the resistance value can be efficiently inspected without increasing the number of measurements twice.

Although not shown in the figure, a structure in which two resistance elements are connected in parallel is convenient for evaluating the lower limit of resistance.

[0041]

As described above, according to the present invention, the number of measurements can be doubled by the above configuration or method even when characteristic anisotropy is a problem as described above. TF with TEG that can perform inspections efficiently without cost
A T-substrate and its inspection method can be provided, and productivity is improved.

[Brief description of the drawings]

FIG. 1A is a plan view showing a configuration of an inspection element (TFT parallel type) of a thin film transistor substrate according to a first embodiment of the present invention, and FIG.

FIG. 2A is a plan view showing a configuration of a test element (TFT serial type) of a thin film transistor substrate according to a second embodiment of the present invention, and FIG.

FIG. 3 is a plan view showing a configuration of a thin film transistor substrate test element (inverter serial type) according to a third embodiment of the present invention;

FIG. 4 is a plan view showing a configuration of a test element (resistor series type) of a thin film transistor substrate according to a fourth embodiment of the present invention.

5A is a schematic plan view showing a configuration of a conventional thin film transistor substrate, FIG. 5B is a plan view showing an example of a TEG,
(C) is a sectional view showing an example of the same TEG.

FIG. 6 is a graph for explaining a failure mode of a thin film transistor.

[Explanation of symbols]

 Reference Signs List 1 glass substrate 2 TFT array 3 TEG block 4a, 4b, 4c measurement pad 5 TFT 6 channel direction 7 polysilicon thin film 8 gate insulating film 9 gate electrode 10 interlayer insulating film 11 source / drain wiring 12 passivation film 13 LDD region 14a, 14b, 14c Measurement pad 15a, 15b TFT 16 Contact part 17 Source / drain wiring 18 Gate electrode 24a, 24b, 24c Measurement pad 25a, 25b TFT 26 Source / drain wiring 27 Gate electrode 30a, 30b Inverter element 31 Source / drain Wiring 32 Gate electrode 34a, 34b, 34c Measurement pad 40a, 40b Resistance element 41 Wiring 44a, 44b, 44c Measurement pad

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/20 H01L 29/78 624 5F052 21/66 G02F 1/136 500 5F110 27/04 H01L 27/04 T 5G435 21/822 PF term (reference) 2G003 AA01 AA07 AB01 AF06 AH02 AH10 2H092 JA24 JA34 JA37 JA41 JB22 JB31 JB57 JB77 KA04 KA05 MA13 MA17 MA30 MA57 NA24 4M106 AA07 AB12 AB15 AB16 AB17 BA01 CA01 DJ04A27 DJ01 BA43 CA19 EA03 EA04 EA05 EA07 GB10 5F038 AR09 AR21 AR29 CA02 CA03 DT04 DT12 EZ06 EZ20 5F052 AA02 BA07 BB07 DA02 JA01 5F110 AA24 BB01 BB04 CC02 DD02 GG02 GG13 HM15 NN77 NN78 KK17 KK17 A09

Claims (9)

[Claims] 1. A thin film transistor substrate having a test element in which a pair of unit elements patterned in two orthogonal directions are connected in series or in parallel. 2. The thin film transistor substrate according to claim 1, wherein the thin film transistor has a thin film transistor using a glass substrate as a substrate and a polysilicon thin film as a semiconductor layer. 3. The thin film transistor substrate according to claim 2, wherein the polysilicon thin film is formed by irradiating a silicon thin film with an excimer laser beam shaped into a line beam and melting and crystallizing the same. 4. The thin film transistor substrate according to claim 1, further comprising a thin film transistor using a thin film material having anisotropy in stress or resistance as a constituent element. 5. An n ⁺ region or p ^{+ of a} thin film transistor
2. The thin film transistor substrate according to claim 1, wherein the boundary between the region and the LDD region is formed by a method that is not self-aligned with the gate electrode. 6. The thin film transistor substrate according to claim 1, wherein each of the pair of unit elements is a thin film transistor. 7. The thin film transistor substrate according to claim 1, wherein each of the pair of unit elements is an inverter element formed by a thin film transistor. 8. A thin film transistor comprising a contact portion and an LDD region formed of a doped polysilicon thin film, wherein the pair of unit elements are formed of a resistance element formed of the same doped polysilicon thin film as the doped polysilicon thin film. The thin film transistor substrate according to claim 1, wherein 9. The method for inspecting a thin film transistor substrate according to claim 1, wherein the step is performed when a current value between terminals of the inspection element in which a pair of unit elements is connected in series or in parallel is out of a specified value. A method for inspecting a thin film transistor substrate, comprising determining that an abnormality has occurred.