JP2001298664A - X-y address selection type solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an X-Y address selection type solid-state image pickup device which can suppress increase of the stable time and lowering of stability of an output block that are problems caused in an initialization mode of a horizontal signal line despite a large number of pixels. SOLUTION: This image pickup device is provided with a pixel block 1 where the pixels are arranged in a matrix form, a row selection block 2, a vertical signal line group 3, an analog signal processing block 4 which performs the analog signal processing to the pixel output, a hold capacitor group 5 which stores the signals that undergo the analog signal processing, a switch group 6 which selects the reading of signals, a horizontal signal line 7, a horizontal scan block 9 which controls a switch group, an output block 10 which consists of an operation amplifier 11, a feed back capacitance 12, an offset voltage holding capacitance 13 and a feedback capacitance initialization switch 14 and reads out the signal level of the line 7 and a voltage source 18 which performs initialization of the line 7. In such a constitution, the initialization of the line 7 is separated from the reset operation of an output block in terms of direct current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an XY address selection type solid-state imaging device, and more particularly to an XY address selection type solid-state imaging device suitable for increasing the number of pixels.
The present invention relates to a Y-address selection type solid-state imaging device.

[0002]

2. Description of the Related Art In general, an XY address selection type solid-state image pickup device arranges photoelectric conversion pixels for outputting an electric signal corresponding to the amount of incident light in a matrix, and outputs the pixel output to a vertical signal line for each row. After being transferred and subjected to analog signal processing such as removal of noise components, the signal of each pixel is read out to a horizontal signal line, and is output in time series through an output circuit connected to the horizontal signal line. . X having such a configuration
An example of a -Y address selection type solid-state imaging device is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-283386.

FIG. 4 is a block diagram showing the configuration of such a conventional XY address selection type solid-state imaging device. 4, reference numeral 1 denotes a pixel block in which photoelectric conversion pixels are arranged in a matrix, 2 denotes a row selection block that selects an arbitrary row of the pixel block 1, 3 denotes a vertical signal line group that outputs a pixel output of the selected row, Reference numeral 4 denotes an analog signal processing block that removes noise components from the pixel output of the vertical signal line group 3, reference numeral 5 denotes a hold capacitor group that stores analog-signal processed signals, and reference numeral 6 denotes a signal that is stored in the hold capacitor group 5. A switch group using NMOS transistors for selecting the read operation, 7 is a horizontal signal line for transferring an accumulation signal of the hold capacitor group 5, 8 is a wiring capacitance of the horizontal signal line 7 and a source capacitance of a transistor forming the switch group 6. Parasitic capacitance associated with the horizontal signal line 7 which is a main factor, a horizontal scanning block 9 for controlling the operation of the switch group 6,
An output block 10 reads the signal level of the horizontal signal line 7. Further, 11 is an operational amplifier, 12 is a feedback capacitance of the operational amplifier 11, 15 is a reference voltage source having a voltage value VREF applied to the + input terminal of the operational amplifier 11, 16 is an output terminal of the operational amplifier 11, and 31 is a short circuit of the feedback capacitance 12. Switch
These constitute an output block 10. In addition,
The pixel block 1 has light-shielded pixels 1a that are shielded from light by AL wiring or the like on the outer periphery, and light-receiving pixels 1b that detect light are arranged inside the light-shielded pixels.

[0004] Next, the operation of the XY address selection type solid-state imaging device having the above-described configuration will be described with reference to the row selection block 2.
Will be described by way of example when N rows are selected. First, when N rows are selected from the row selection block 2, pixel signals corresponding to the amount of incident light are sent from each pixel arranged in the N rows to the vertical signal line group 3, and the analog signal processing block 4
After the noise component is removed in step (5), the noise component is accumulated in the hold capacitor group 5. Here, the terminal voltage of the hold capacitor group 5 decreases in accordance with the light amount in the light-shielded pixel and the light amount in the light-shielded pixel without incident light. Assuming that the terminal voltages of the hold capacitors in the 0th and 1st columns are VOB and VOB, −Vsig.

Next, a reset operation for setting the switch 31 to CLOSE, that is, a short circuit of the feedback capacitor 12 and the horizontal signal line 7
Is initialized. At this time, the operational amplifier 11 is in a voltage follower connection, and sets the horizontal signal line 7 to the voltage value (= VREF) of the reference voltage source 15. At this time, since the parasitic capacitance 8 acts as the load capacitance of the output block 10, attention must be paid to the charging and discharging time of the parasitic capacitance 8 and the stability of the output block 10.

Further, after the switch 31 is set to 0PEN (reset operation is released), the switch in the 0th column of the switch group 6 is set to CLOS
The signal stored in the hold capacitor is transferred to the horizontal signal line 7 as E. The reset operation and the transfer operation are set as one set and are referred to as a signal read operation. Subsequently, the signal read operation in which the reset operation and the transfer operation are set
Perform for the column. By these signal reading operations,
The voltage difference between the initialization voltage of the horizontal signal line 7 and the signal voltage stored in the hold capacitor is inverted and amplified via the output block 10 with reference to the reset output (= VREF). The amplification factor of the output block 10 is (capacity value of hold capacitor / capacity value of feedback capacitance).

If the voltage of the hold capacitor terminal in the first column is VOB-Vsig, the output terminal 16 of the operational amplifier 11 is
, An output voltage VOUT expressed by the following equation (1) appears. VOUT = VREF − ｛(VOB−Vsig) −VREF｝ (Ch / Cf) = VREF + (VREF−VOB) (Ch / Cf) + (Ch / Cf) Vsig (1) Here, Ch is the capacitance value of the hold capacitor, and Cf is the capacitance value of the feedback capacitance. Further, if the reference voltage source 15 is adjusted so that VOB = VREF, the equation (1) can be simplified as the following equation (2). VOUT = VREF + (Ch / Cf) Vsig (2) From equation (2), a pixel signal is output in the form of a difference voltage from the reference voltage VREF. After this, the second and third rows ...
.., The signal reading operation is sequentially performed up to the last column, and the processing of the Nth row is completed.

[0008]

By the way, in the conventional XY address selection type solid-state image pickup device shown in FIG.
Acts as a load capacity of 10. When the number of pixels per row increases due to the increase in the number of pixels, the wiring of the horizontal signal line 7 is extended and the number of switches included in the switch group 6 increases, so that the parasitic capacitance 8 increases. Therefore, by increasing the number of pixels, the load capacity of the output block 10 increases at the time of initializing the horizontal signal line, so that the load on the circuit increases, and the stabilization time increases and the stability decreases. As described above, in the conventionally proposed XY address selection type solid-state imaging device, sufficient consideration has not been given to increasing the number of pixels.

The present invention has been made to solve the above-mentioned problem in the conventional XY address selection type solid-state image pickup device. Even if the number of pixels is increased, the stabilization time which becomes a problem when initializing the horizontal signal line is reduced. It is an object of the present invention to provide an XY address selection type solid-state imaging device capable of suppressing an increase and a decrease in stability of an output block.

[0010]

According to a first aspect of the present invention, there is provided a pixel block in which photoelectric conversion pixels are arranged in a matrix, and a row selection for selecting an arbitrary row of the pixel block. A block, a vertical signal line group that outputs a pixel output of a selected row selected by the row selection block, an analog signal processing block that performs analog signal processing on the pixel output of the vertical signal line group, and an analog signal processing Hold capacitors that store the signal
A switch group for selecting reading of a signal stored in the hold capacitor group, a horizontal signal line for transferring a stored signal of the hold capacitor group, a horizontal scanning block for controlling the operation of the switch group, an inverting amplifier, A first capacitor connected between a horizontal signal line and an output terminal of the inverting amplifier, a second capacitor connected between the horizontal signal line and an input terminal of the inverting amplifier, and an input terminal and an output terminal of the inverting amplifier; An output block for reading the signal level of the horizontal signal line, comprising a switch connected between the output block and a power supply for initializing the horizontal signal line, and performing a horizontal signal line initialization and an output block reset operation. The XY address selection type solid-state imaging device is configured so as to be separated in direct current.

In the XY address selection type solid-state image pickup device having such a configuration, since the reset operation of the output block and the initialization of the horizontal signal line can be separated in a DC manner, the parasitic capacitance of the horizontal signal line is increased by increasing the number of pixels. Does not cause a decrease in the stability of the output block. The function required for the voltage source used for initializing the horizontal signal line is as follows:
It can be realized with a relatively simple circuit using only the current capacity for rapidly charging the capacitance, and therefore, it is possible to easily suppress an increase in the stabilization time during initialization due to an increase in the parasitic capacitance of the horizontal signal line. Becomes

According to a second aspect of the present invention, there is provided a pixel block in which photoelectric conversion pixels are arranged in a matrix, a row selection block for selecting an arbitrary row of the pixel block, and a selection row selected by the row selection block. A vertical signal line group that outputs a pixel output, an analog signal processing block that performs analog signal processing on the pixel output of the vertical signal line group,
A hold capacitor group for storing signals processed by analog signal processing, a switch group for selecting reading of signals stored in the hold capacitor group, a horizontal signal line for transferring a stored signal of the hold capacitor group, A horizontal scanning block for controlling operation; an inverting amplifier, a first capacitor connected between the horizontal signal line and an output terminal of the inverting amplifier, and a first capacitor connected between the horizontal signal line and an input terminal of the inverting amplifier. An output block for reading a signal level of the horizontal signal line, the output block including a capacitor of No. 2 and a switch connected between an input terminal and an output terminal of the inverting amplifier; and an adjustment block for adjusting an initialization voltage value of the horizontal signal line. DC separation between the initialization of the horizontal signal line and the reset operation of the output block, and the black level output of the output block It constitutes a X-Y address selection type solid state image pickup device so as to equal the preset value.

In the XY address selection type solid-state imaging device having the above-described configuration, the reset operation of the output block and the initialization of the horizontal signal line can be separated in a direct current manner. Does not cause a decrease in the stability of the output block. The function required for the voltage source used for initializing the horizontal signal line is as follows:
It can be realized with a relatively simple circuit using only the current capacity for rapidly charging the capacitance, and therefore, it is possible to easily suppress an increase in the stabilization time during initialization due to an increase in the parasitic capacitance of the horizontal signal line. Becomes Further, the black level output of the output block can be adjusted to a preset value, which is advantageous for manufacturing variations and temperature changes.

[0014]

Next, an embodiment will be described. FIG. 1 is a circuit diagram showing a first embodiment of an XY address selection type solid-state imaging device according to the present invention. Components corresponding to those of the conventional example shown in FIG. Is shown. In FIG. 1, 1 is a pixel block in which photoelectric conversion pixels are arranged in a matrix, 2 is a row selection block for selecting an arbitrary row of the pixel block 1,
Reference numeral 3 denotes a vertical signal line group that outputs a pixel output of a selected row, 4 denotes an analog signal processing block that performs analog signal processing such as noise component removal on the pixel output of the vertical signal line group 3,
Reference numeral 5 denotes a group of hold capacitors for storing the signals processed by the analog signal processing, 6 denotes a group of switches using NMOS transistors for selecting the reading of the signals stored in the group of hold capacitors 5, and 7 transfers the stored signal of the group of hold capacitors 5. A horizontal signal line 8 is a parasitic capacitance associated with the horizontal signal line 7 mainly due to a wiring capacitance of the horizontal signal line 7 and a source capacitance of a transistor constituting the switch group 6, and 9 controls an operation of the switch group 6. A horizontal scanning block, 10 is an output block for reading the signal level of the horizontal signal line 7;
Is a switch for initializing the horizontal signal line 7, and 18 is a voltage source whose voltage value for initializing the horizontal signal line 7 is VBIAS.

Reference numeral 11 denotes an operational amplifier, and 12 denotes an operational amplifier.
A feedback capacitance of an operational amplifier connected between the output terminal of the operational amplifier 11 and the horizontal signal line 7; a capacitance 13 for storing an offset voltage connected between the negative input terminal of the operational amplifier 11 and the horizontal signal line 7;
14 is a switch for initializing the feedback capacitor 12 connected between the output terminal and the-input terminal of the operational amplifier 11, 15 is a reference voltage source whose voltage applied to the + input terminal of the operational amplifier 11 is VREF, and 16 is an operational amplifier. The output block 11 is composed of 11 output terminals. Note that the pixel block 1 has light-shielded pixels 1a on the outer periphery that are shielded from light by AL wiring or the like.
A light receiving pixel 1b for detecting light is arranged inside the light shielding pixel.

Next, the operation of the first embodiment configured as described above will be described by taking as an example a case where N rows are selected by the row selection block 2. The operation until the signal from which the noise component has been removed is stored in the hold capacitor group 5 is the same as that of the conventional example shown in FIG. It is assumed that the terminal voltage of the first column of the hold capacitor group 5 is expressed as VOB-Vsig.

First, a reset operation in which both the initialization switch 14 and the switch 17 are set to CLOSE is performed. At this time, the operational amplifier 11 has a voltage follower connection, and the + input terminal and the − input terminal have the same voltage (= VREF). On the other hand, since the horizontal signal line 7 is connected to the voltage source 18, it has the same potential as VBIAS. Therefore, the output terminal 16 of the operational amplifier 11 is connected to the horizontal signal line 7 via the feedback capacitance 12 and the offset capacitance 13, and is separated from the horizontal signal line 7 in a DC manner. That is,
The parasitic capacitance 8 does not become a load capacitance of the output block 10 and does not affect circuit characteristics such as stability. Note that VREF−VBI is provided between the terminals of the feedback capacitance 12 and the offset capacitance 13.
AS voltage is applied.

Next, after both the initialization switch 14 and the switch 17 are set to OPEN (cancel the reset operation), only the switch in the 0th column of the switch group 6 is set to CLOSE, and the signal accumulated in the hold capacitor is changed to horizontal. Transfer to signal line 7. The reset operation and the transfer operation are set as one set and are referred to as a signal read operation. Further, a signal read operation in which the reset operation and the transfer operation are set is performed on the first column. By these signal reading operations, the voltage difference between the initialization voltage of the horizontal signal line 7 and the signal voltage stored in the hold capacitor is inverted and amplified via the output block 10.
The amplification factor of the output block 10 is (capacitance value of hold capacitor / capacitance value of feedback capacitance) and is based on the reset output (= VREF) of the output block 10.

Assuming that the voltage of the hold capacitor terminal in the first column is VOB-Vsig, the output terminal 16 of the operational amplifier 11 is
, An output voltage V0UT expressed by the following equation (3) appears. VOUT = VREF − ｛(VOB−Vsig) −VBIAS｝ (Ch / Cf) = VREF + (VBIAS−VOB) (Ch / Cf) + (Ch / Cf) Vsig (3) Here, Ch is the capacitance value of the hold capacitor, and Cf is the capacitance value of the feedback capacitance. Further, if the voltage source 18 is adjusted so that VOB = VBIAS, the equation (3) can be simplified as the following equation (4). VOUT = VREF + (Ch / Cf) Vsig (4) From equation (4), a pixel signal is output in the form of a voltage difference from the reference voltage VREF. After this, the second and third rows ...
.., The signal reading operation is sequentially performed up to the last column, and the processing of the Nth row is completed.

As described above, in the XY address selection type solid-state imaging device according to the embodiment shown in FIG. 1, since the horizontal signal line 7 is initialized by the independent voltage source 18, the horizontal signal line 7 is initialized. And the reset operation of the output block 10 can be separated in a DC manner. That is, the load capacitance of the output block 10 is only the feedback capacitance 12 and the offset voltage storage capacitance 13, and the parasitic capacitance 8 does not become the load capacitance of the output block 10. Therefore, even if the parasitic capacitance 8 of the horizontal signal line 7 increases due to the increase in the number of pixels, the characteristics of the output block 10 are not affected, and the stability of the output block 10 is not impaired. The only characteristic required of the voltage source 18 is the current capability for rapidly charging the parasitic capacitance 8.
Since this can be realized by a general regulator circuit, it is possible to easily suppress an increase in the stabilization time during initialization even when the parasitic capacitance 8 of the horizontal signal line 7 becomes large.

This embodiment can be variously modified and changed. For example, by adjusting the output voltage VBIAS of the voltage source 18 as shown in Expression (3), the output voltage VOU
The voltage level of T can be changed arbitrarily. Further, as shown in FIG. 2, the reference voltage source 15 can be shared with the initialization voltage source of the horizontal signal line 7.

Next, a second embodiment will be described with reference to FIG. Components corresponding to those in the first embodiment are denoted by the same reference numerals. In FIG. 3, reference numeral 1 denotes a pixel block in which photoelectric conversion pixels are arranged in a matrix.
Reference numeral 2 denotes a row selection block for selecting an arbitrary row of the pixel block 1, reference numeral 3 denotes a vertical signal line group for outputting a pixel output of the selected row, and reference numeral 4 denotes removal of noise components from the pixel output of the vertical signal line group 3. 5 is a hold capacitor group for storing analog-processed signals, 6 is a switch group using NMOS transistors for selecting reading of signals stored in the hold capacitor group 5, and 7 is a hold capacitor group 5 is a horizontal signal line for transferring an accumulation signal, 8 is a parasitic capacitance associated with the horizontal signal line 7 mainly due to a wiring capacitance of the horizontal signal line 7 and a source capacitance of a transistor constituting the switch group 6, and 9 is the switch A horizontal scanning block for controlling the operation of the group 6, an output block 10 for reading the signal level of the horizontal signal line 7, and a switch 17 for initializing the horizontal signal line 7. Switch 19 changes the initializing voltage value of the horizontal signal line 7 to make the black level signal obtained from the output block 10 equal to the black level setting value 19. An adjustment block 21 is a switch for inputting the black level signal of the output block 10 to the adjustment block 20.

Reference numeral 11 denotes an operational amplifier, and 12 denotes an operational amplifier.
13, a capacitor for storing the offset voltage, 13 a switch for initializing the feedback capacitor 12, 15 a reference voltage source whose voltage applied to the + input terminal of the operational amplifier 11 is VREF, and 16 an output terminal of the operational amplifier 11. In these, output block 10
Is configured. A comparator 22 compares a black level signal obtained from the output block 10 with a black level set value 19 and outputs a control signal so that the two signals become equal.
Reference numeral 23 denotes a voltage source that changes the output voltage according to a control signal output from the comparator 22.
20 are configured. Note that the pixel block 1 has A
A light-receiving pixel 1b that has a light-shielded pixel 1a that is light-shielded by an L wiring or the like and that detects light is disposed inside the light-shielded pixel.

Next, the operation of the second embodiment configured as described above will be described. First, black level adjustment is performed using a light-shielded pixel having no incident light. A description will be given of an example in which the 0th row is selected by the row selection block 2 and the black level adjustment using the 0th shaded row is performed. Since no light enters the light-shielded pixels arranged in the 0th row, the voltage stored in the hold capacitor group 5 is VOB. First, a reset operation for setting both the initialization switch 14 and the switch 17 to CLOSE is performed. At this time, the operational amplifier 11 has a voltage follower connection, and the + input terminal and the − input terminal have the same voltage (=
VREF). On the other hand, the horizontal signal line 7 is
Output voltage = VCHANGE. Therefore, the output terminal 16 of the operational amplifier 11 is connected to the horizontal signal line 7 via the feedback capacitance 12 and the offset capacitance 13, and is separated from the horizontal signal line 7 in a DC manner. That is, the parasitic capacitance 8 does not become a load capacitance of the output block 10 and does not affect circuit characteristics such as stability. Note that a voltage of VREF-VCHANGE is applied between the terminals of the feedback capacitance 12 and the offset capacitance 13.

Next, after both the initialization switch 14 and the switch 17 are opened (the reset operation is released), only the switch in the 0th column of the switch group 6 is set to CLOSE, and the signal accumulated in the hold capacitor is changed to the horizontal position. Transfer to signal line 7. The reset operation and the transfer operation are set as one set and are referred to as a signal read operation. By these operations, the voltage difference between the initialization voltage of the horizontal signal line 7 and the signal voltage stored in the hold capacitor is inverted and amplified via the output block 10. The amplification factor of the output block 10 is (capacity value of hold capacitor / capacitance value of feedback capacitance),
Based on 10 reset outputs (= VREF). Here, since the hold capacitor terminal voltage is VOB, the operational amplifier 11
The output voltage V0U represented by the following equation (5)
T appears. VOUT = VREF− (VOB−VCHANGE) (Ch / Cf) (5) where Ch is the capacitance value of the hold capacitor, and Cf is the capacitance value of the feedback capacitance.

At the time of this transfer operation, the switch 21 is set to CLOSE
As a result, the output terminal 16 of the operational amplifier 11 (output voltage V
OUT) and the adjustment block 20. This allows the comparator
At 22, the output voltage VOUT is compared with the black level setting value 19 (= VOBCLP), and the voltage source 23 is controlled as shown in the following equations (6), (7) and (8) to realize VOUT = VOBCLP. I do. When VOUT> VOBCLP, the output of the voltage source 23 = VCHANGE−α (6) When VOUT = VOBCLP, the output of the voltage source 23 = VCHANGE (7) When VOUT <VOBCLP, the voltage source 23 = VCHANGE + α (8) where α is the amount of voltage change by the control signal. The new output value of the voltage source 23 represented by the equations (6), (7), and (8) is used in the next initialization of the horizontal signal line 7. This is called a black level adjustment operation.

Further, by performing a signal reading operation (light-shielded pixel) and a black level adjusting operation up to the second column, the third column,... And the last column, the output of the voltage source 23 is given by the following equation (9). Set to satisfy. VCHANGE = (VOBCLP-VREF) (Cf / Ch) + VOB (9)

After the black level adjustment using line 0 is completed, 1
Only a normal signal read operation is performed from the row. For example, 1
Assuming that the hold capacitor terminal voltage in the column is VOB-Vsig, an output voltage VOUT expressed by the following equation (10) appears at the output terminal 16 of the operational amplifier 11. VOUT = VREF − ｛(VOB−Vsig) −VCHANGE｝ (Ch / Cf) (10) Here, since the black level adjustment has been completed, the equation (9) is used. Then, the following equation (11) is obtained. VOUT = VOBCLP + (Ch / Cf) Vsig (11) From equation (11), the pixel signal is reflected in the form of a voltage difference from the black level setting value 19 (= VOBCLP). Is done. Subsequently, the signal reading operation is sequentially performed on the second column, the third column,... And the last column, and the processing of the first row is completed.

In general, the pixel signal VOB without incident light is affected by the use environment such as the manufacturing process and the temperature, so that the output level varies for each sample or the output level varies depending on the use environment. However, by performing the black level adjustment as in the present embodiment shown in FIG. 3,
The term of the pixel signal VOB without incident light is canceled, and does not affect the output voltage VOUT shown in the equation (11).

As described above, in the XY address selection type solid-state imaging device according to the second embodiment shown in FIG. 3, the initialization operation of the horizontal signal line 7 and the reset operation of the output block 10 are performed by direct current. Can be separated. That is, the load capacitance of the output block 10 is only the feedback capacitance 12 and the offset voltage storage capacitance 13, and the parasitic capacitance 8 is
Load capacity. Therefore, even if the parasitic capacitance 8 of the horizontal signal line 7 increases due to the increase in the number of pixels, the characteristics of the output block 10 are not affected, and the stability of the output block 10 is not impaired. Further, the characteristic required for the voltage source 23 is only the current capability for rapidly charging the parasitic capacitance 8 and can be realized by a general regulator circuit. Therefore, even if the parasitic capacitance 8 of the horizontal signal line 7 becomes large, It is possible to easily suppress an increase in the stabilization time at the time of formation. Further, the black level output of the output block can be adjusted to a preset value, which is advantageous for manufacturing variations and temperature changes.

[0031]

As described above with reference to the embodiment, according to the first aspect of the present invention, since the initialization of the horizontal signal line is performed by an independent voltage source, the initialization operation of the horizontal signal line is performed. And the reset operation of the output block can be separated in a DC manner, so that even if the parasitic capacitance of the horizontal signal line increases due to the increase in the number of pixels, the stability of the output block does not decrease. Also, an increase in the stabilization time of the horizontal signal line due to an increase in the parasitic capacitance can be basically suppressed by a simple circuit. According to the second aspect of the present invention, the initialization operation of the horizontal signal line and the reset operation of the output block can be separated from each other in a DC manner.
Even if the parasitic capacitance of the horizontal signal line increases due to the increase in the number of pixels, the stability of the output block does not decrease. Furthermore, an increase in the stabilization time of the horizontal signal line due to an increase in the parasitic capacitance can be basically suppressed by a simple circuit. In addition, since the black level output of the output block can be adjusted to a preset value, it is advantageous for manufacturing variations and temperature changes.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an XY address selection type solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram showing a modification of the first embodiment shown in FIG.

FIG. 3 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a conventional XY address selection type solid-state imaging device.

[Explanation of symbols]

 Reference Signs List 1 pixel block 1a light-shielded pixel 1b light-receiving pixel 2 row selection block 3 vertical signal line group 4 analog signal processing block 5 hold capacitor group 6 switch group 7 horizontal signal line 8 parasitic capacitance 9 horizontal scanning block 10 output block 11 operational amplifier 12 feedback capacitance 13 Offset voltage storage capacitor 14 Feedback capacitance initialization switch 15 Reference voltage source 16 Operational amplifier output terminal 17 Horizontal signal line initialization switch 18 Voltage source 19 Black level set value 20 Adjustment block 21 Black level signal input switch 22 Comparator 23 Voltage source

Claims (2)

[Claims] 1. A pixel block in which photoelectric conversion pixels are arranged in a matrix, a row selection block for selecting an arbitrary row of the pixel block, and a vertical block for outputting a pixel output of a selected row selected by the row selection block. A signal line group, an analog signal processing block that performs analog signal processing on the pixel output of the vertical signal line group, a hold capacitor group that stores analog signal-processed signals, and a signal line that is stored in the hold capacitor group. A switch group for selecting reading, a horizontal signal line for transferring an accumulation signal of the hold capacitor group, a horizontal scanning block for controlling the operation of the switch group, an inverting amplifier, an output terminal of the horizontal signal line, and an output terminal of the inverting amplifier A first capacitor connected between the horizontal signal line and an input terminal of the inverting amplifier; An output block comprising a switch connected between an input terminal and an output terminal of the inverting amplifier, for reading a signal level of the horizontal signal line; and a power supply for initializing the horizontal signal line, and An XY address selection type solid-state imaging device characterized in that it is configured to separate a DC operation from a reset operation of an output block. 2. A pixel block in which photoelectric conversion pixels are arranged in a matrix, a row selection block for selecting an arbitrary row of the pixel block, and a vertical block for outputting a pixel output of a selected row selected by the row selection block. A signal line group, an analog signal processing block that performs analog signal processing on the pixel output of the vertical signal line group, a hold capacitor group that stores analog signal-processed signals, and a signal line that is stored in the hold capacitor group. A switch group for selecting reading, a horizontal signal line for transferring an accumulation signal of the hold capacitor group, a horizontal scanning block for controlling the operation of the switch group, an inverting amplifier, an output terminal of the horizontal signal line, and an output terminal of the inverting amplifier A first capacitor connected between the horizontal signal line and an input terminal of the inverting amplifier; An output block comprising a switch connected between an input terminal and an output terminal of the inverting amplifier, for reading a signal level of the horizontal signal line; and an adjustment block for adjusting an initialization voltage value of the horizontal signal line, XY address selection, wherein DC initialization is performed for line initialization and output block reset operation, and the black level output of the output block is made equal to a preset value. Type solid-state imaging device.