JP2001298145A - Spherical semiconductor device - Google Patents
Spherical semiconductor deviceInfo
- Publication number
- JP2001298145A JP2001298145A JP2000110370A JP2000110370A JP2001298145A JP 2001298145 A JP2001298145 A JP 2001298145A JP 2000110370 A JP2000110370 A JP 2000110370A JP 2000110370 A JP2000110370 A JP 2000110370A JP 2001298145 A JP2001298145 A JP 2001298145A
- Authority
- JP
- Japan
- Prior art keywords
- spherical semiconductor
- semiconductor element
- semiconductor device
- spherical
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 25
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000004643 cyanate ester Substances 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1017—Shape being a sphere
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、球面半導体素子を実装
した球面半導体装置に関する。更に詳しくは、球面半導
体素子をマザーボード等の基板上に実装した球面半導体
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spherical semiconductor device on which a spherical semiconductor element is mounted. More specifically, the present invention relates to a spherical semiconductor device in which a spherical semiconductor element is mounted on a substrate such as a motherboard.
【０００２】[0002]
【従来の技術】現在の２次元の平面を利用して作る現在
の集積回路においては、新工場設立のための投資金額が
１０００億円以上必要と言われている。将来、１Ｇ Ｄ
ＲＡＭ以上の量産工場を想定すると、新工場設立のため
の投資金額は１兆円以上とも言われている。それに加え
て微細加工化が進んで工程が複雑化するため、最終製品
を得るまでのサイクルタイムも１２０日以上と、極端に
長くなる問題もある。2. Description of the Related Art It is said that a current integrated circuit manufactured using a two-dimensional plane requires an investment of 100 billion yen or more for establishing a new factory. Future 1G D
Assuming a mass-production factory larger than RAM, the investment amount for establishing a new factory is said to be more than 1 trillion yen. In addition, the fine processing is advanced and the process is complicated, so that there is a problem that the cycle time until obtaining the final product is extremely long, such as 120 days or more.
【０００３】半導体産業が抱えるこれらの問題を解決す
る方法として、近年、球面半導体（Ｂａｌｌ Ｓｅｍｉ
ｃｏｎｄｕｃｔｏｒ）という新しいコンセプトが提案さ
れている。ここにいう「球面半導体」とは、従来の２次
元の平面を利用して作る現在の集積回路をチップと称す
るのに対して、３次元の球面上に作る集積回路の呼称で
ある。[0003] As a method for solving these problems in the semiconductor industry, a ball semiconductor (Ball Semi) has recently been used.
A new concept has been proposed. The term "spherical semiconductor" as used herein refers to an integrated circuit formed on a three-dimensional spherical surface, whereas a current integrated circuit formed using a conventional two-dimensional plane is referred to as a chip.
【０００４】球状半導体を用いることで、．従来のチ
ップに対して、同じ投影面積当たりの表面積が約３倍で
ある。．クリーンルームが不要になり、初期投資コス
トが１／１０程度に削減できる。．最終製品を得るま
でのサイクルタイムが従来の１２０日から１週間以内に
削減できる。、等のメリットが得られる。[0004] By using a spherical semiconductor,. The surface area per projected area is about three times that of the conventional chip. . A clean room becomes unnecessary, and the initial investment cost can be reduced to about 1/10. . The cycle time required to obtain the final product can be reduced from the conventional 120 days to less than one week. , Etc. are obtained.
【０００５】係る球面半導体には金等からなるマイクロ
バンプからなる接続端子が形成されており、基板への実
装形態としては、．マイクロバンプによる直接接続
（いわゆる「Ｏｎ ＰＣＢ」）と、．球面半導体同士
をマイクロバンプを介して接合した状態での接続（いわ
ゆる「クラスタリング」）がある。球面半導体同士のク
ラスタリングを用いた球面半導体装置が、電子材料、１
９９８年１１月号、ｐ．２１〜２６に開示されている。[0005] The spherical semiconductor has connection terminals formed of microbumps made of gold or the like. Direct connection by micro-bumps (so-called “On PCB”); There is a connection (so-called "clustering") in a state where spherical semiconductors are joined via micro bumps. Spherical semiconductor devices using clustering of spherical semiconductors can be used for electronic materials,
November 998, p. 21 to 26.
【０００６】[0006]
【発明が解決しようとする課題】しかし、球面半導体と
実装基板とのマイクロバンプ接合部においては、構造上
その接合部の面積割合が従来と比較して小さくなる。そ
のため、温度変化が繰返し負荷された場合、球面半導体
と実装基板との熱膨張差に起因するせん断応力によって
マイクロバンプ接合部の破断が発生しやすくなる問題が
ある。However, at the micro-bump junction between the spherical semiconductor and the mounting substrate, the area ratio of the junction is structurally smaller than in the prior art. Therefore, when a temperature change is repeatedly applied, there is a problem that the micro-bump bonding portion is easily broken due to shear stress caused by a difference in thermal expansion between the spherical semiconductor and the mounting substrate.
【０００７】また、クラスタリングした球面半導体同士
のマイクロバンプ接合部についても、上記の球面半導体
と実装基板との熱膨張差に起因するせん断応力の影響を
受けるため、球面半導体同士のマイクロバンプ接合部で
も破断が発生しやすくなる問題がある。[0007] Also, the microbump junction between the clustered spherical semiconductors is affected by the shear stress caused by the difference in thermal expansion between the spherical semiconductor and the mounting substrate. There is a problem that the fracture is likely to occur.
【０００８】本発明は、球面半導体と実装基板との熱膨
張差に起因するせん断応力によって発生するマイクロバ
ンプ接合部の破断を防止した、接続信頼性に優れた球面
半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a spherical semiconductor device which is excellent in connection reliability and prevents breakage of a micro-bump joint caused by shear stress caused by a difference in thermal expansion between a spherical semiconductor and a mounting substrate. And
【０００９】[0009]
【課題を解決するための手段】請求項１の発明は、該基
板と該球面半導体素子の間にアンダーフィル材が充填さ
れている球面半導体装置を要旨とする。球面半導体装置
は、その端面が略同一面上に揃うように形成された接続
端子を有する。球面半導体装置は、接続端子が確保でき
る接続面積が非常に狭いため、基板上に直接実装する
と、接続信頼性の確保が難しい問題がある。この球面半
導体装置と基板の間に、実装部周辺の応力集中を緩和す
るためのアンダーフィル材させることで、実装部の応力
集中を効果的に緩和して、高い接続信頼性を得ることが
できる。The gist of the present invention resides in a spherical semiconductor device in which an underfill material is filled between the substrate and the spherical semiconductor element. The spherical semiconductor device has connection terminals formed so that the end faces thereof are substantially flush with each other. Since the spherical semiconductor device has a very small connection area in which connection terminals can be secured, there is a problem that it is difficult to secure connection reliability when directly mounted on a substrate. By providing an underfill material between the spherical semiconductor device and the substrate to alleviate the stress concentration around the mounting portion, the stress concentration at the mounting portion can be effectively alleviated, and high connection reliability can be obtained. .
【００１０】アンダーフィル材としては、そのヤング率
が５ＧＰａ以上であるのがよい。ここにいう「ヤング
率」とは、アンダーフィル材の硬化体に超微小硬度計を
用いて測定される見かけヤング率をいう。具体的には、
アンダーフィル材の硬化体に超微小硬度計（Ｆｉｓｃｈ
ｅｒ社製 フィッシャースコープ Ｈ−１００）を用い
て測定される見かけヤング率｛Ｅ／（１−ν2）｝（単
位；ＧＰａ）をいう。ここで、Ｅはヤング率（単位；Ｇ
Ｐａ）、νはポアソン比である。測定方法はＤＩＮ５０
３５９−１に準じて行えばよい。そのヤング率が５ＧＰ
ａ以上のヤング率を有するアンダーフィル材を用いるこ
とで、球面半導体素子の実装部周辺の応力集中をさらに
効果的に緩和して、より高い接続信頼性を発揮すること
が可能となる。The underfill material preferably has a Young's modulus of 5 GPa or more. The term "Young's modulus" as used herein refers to an apparent Young's modulus measured on a cured body of an underfill material using an ultra-micro hardness tester. In particular,
Ultra-fine hardness tester (Fisch)
It refers to the apparent Young's modulus {E / (1-ν2)} (unit: GPa) measured using a Fisherscope H-100 manufactured by ER Co., Ltd. Here, E is Young's modulus (unit; G
Pa) and ν are Poisson's ratios. Measurement method is DIN50
What is necessary is just to carry out according to 359-1. The Young's modulus is 5GP
By using an underfill material having a Young's modulus equal to or more than a, stress concentration around the mounting portion of the spherical semiconductor element can be more effectively reduced, and higher connection reliability can be exhibited.
【００１１】面接続端子を有する基板は、Ｃ４パッドや
Ａｕバンプに代表される面接続端子を有する。マザーボ
ード等のプリント配線板、多層配線基板等を用いること
ができる。材質は、ＦＲ−４等のガラス−エポキシ複合
材料、ＰＴＦＥ等のフッ素系樹脂やフッ素系樹脂とシア
ネートエステル系樹脂との複合材料といった有機系材料
や、アルミナ、窒化アルミニウム、ムライト、ガラスセ
ラミック複合材料といった無機系材料を用いることがで
きる。A substrate having surface connection terminals has surface connection terminals typified by C4 pads and Au bumps. A printed wiring board such as a motherboard, a multilayer wiring board, or the like can be used. The material is an organic material such as a glass-epoxy composite material such as FR-4, a fluorine resin such as PTFE, or a composite material of a fluorine resin and a cyanate ester resin, or an alumina, aluminum nitride, mullite, or glass ceramic composite material. Such inorganic materials can be used.
【００１２】請求項２の発明は、アンダーフィル材の充
填高さと実装時における球面半導体素子の高さとの関係
を規定した球面半導体装置を要旨とする。球面半導体素
子の高さに対するアンダーフィル材の充填高さを調整す
ることで、球面半導体素子にかかる応力集中を緩和し
て、球面半導体装置の信頼性を高めることができる。球
面半導体素子の中心線以上の部分を露出させることで、
球面半導体素子からの放熱性を高めて、実装部周辺の応
力集中を効果的に緩和できる。A second aspect of the present invention provides a spherical semiconductor device which defines a relationship between a filling height of an underfill material and a height of a spherical semiconductor element at the time of mounting. By adjusting the filling height of the underfill material with respect to the height of the spherical semiconductor element, stress concentration on the spherical semiconductor element can be reduced, and the reliability of the spherical semiconductor device can be improved. By exposing the portion above the center line of the spherical semiconductor element,
The heat radiation from the spherical semiconductor element is enhanced, and the stress concentration around the mounting portion can be effectively reduced.
【００１３】ここにいう「実装時における球面半導体自
体の垂直方向の寸法の中心点」とは、実装状態にある球
面半導体素子のうち、接続端子の高さを除いた球面半導
体のみの部分の垂直方向に引いた仮想寸法線の中心点、
つまり、球面半導体のみの部分の垂直方向における中心
点をいう。The "central point of the vertical dimension of the spherical semiconductor itself at the time of mounting" as used herein means the vertical portion of the spherical semiconductor element alone in the mounted semiconductor device excluding the height of the connection terminals. The center point of the virtual dimension line drawn in the direction,
That is, it refers to the center point in the vertical direction of only the spherical semiconductor.
【００１４】この中心点に仮想の中心線を水平方向に引
いた場合において、アンダーフィル材の少なくとも一部
がこの中心線以上、かつ、実装時における球面半導体素
子の高さ未満の高さまで充填されていることが必要であ
る。ここにいう「実装時における球面半導体素子の高
さ」とは、基板等の上に実装された状態の球面半導体素
子の高さ、つまり、基板等の面から実装された状態の球
面半導体素子の最上部までの高さをいう。When an imaginary center line is drawn in the horizontal direction at the center point, at least a part of the underfill material is filled up to the height of the center line and less than the height of the spherical semiconductor element at the time of mounting. It is necessary to be. The “height of the spherical semiconductor element at the time of mounting” here is the height of the spherical semiconductor element mounted on a substrate or the like, that is, the height of the spherical semiconductor element mounted from the surface of the substrate or the like. The height to the top.
【００１５】尚、球面半導体素子が隣り合う球面半導体
素子と接続端子で接合されている場合があるが、この場
合は、垂直方向の最上部に位置する接続端子部が埋設さ
れるようにアンダーフィル材を充填するのがよい。隣り
合う球面半導体素子を繋ぐ接続端子にかかる応力集中を
効果的に緩和できる。In some cases, a spherical semiconductor element is joined to an adjacent spherical semiconductor element by a connection terminal. In this case, the underfill is formed so that the connection terminal located at the top in the vertical direction is buried. It is good to fill the material. The stress concentration applied to the connection terminals connecting the adjacent spherical semiconductor elements can be effectively reduced.
【００１６】ここにいう「実装された状態の球面半導体
素子の最上部」とは、基板等の上に球面半導体素子を単
層で実装した状態のみならず、いわゆる「クラスター」
状に実装した場合も含まれる。このクラスター状に実装
した場合の「実装時における球面半導体素子の高さ」と
は、クラスターの最上層の球面半導体素子における中心
線を基準とする。したがって、クラスターの最上層以外
の球面半導体素子は、アンダーフィル材の中に埋設され
た状態になっている。The "top of the mounted spherical semiconductor element" as used herein means not only a state in which the spherical semiconductor element is mounted in a single layer on a substrate or the like, but also a so-called "cluster".
This includes the case of mounting in the form. The “height of the spherical semiconductor element at the time of mounting” when mounted in a cluster is based on the center line of the spherical semiconductor element in the uppermost layer of the cluster. Therefore, the spherical semiconductor elements other than the top layer of the cluster are buried in the underfill material.
【００１７】尚、クラスターの最上層以外の球面半導体
素子が隣り合う球面半導体素子と接続端子で接合されて
いる場合があるが、この場合は、垂直方向の最上部に位
置する接続端子部が埋設されるようにアンダーフィル材
を充填するのがよい。隣り合う球面半導体素子を繋ぐ接
続端子にかかる応力集中を効果的に緩和できる。In some cases, a spherical semiconductor element other than the uppermost layer of the cluster is joined to an adjacent spherical semiconductor element at a connection terminal. In this case, the connection terminal part located at the top in the vertical direction is buried. It is better to fill the underfill material so that The stress concentration applied to the connection terminals connecting the adjacent spherical semiconductor elements can be effectively reduced.
【００１８】[0018]
【実施例】本発明を、以下に実施例を用いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.
【００１９】図１に基づいて、基板に直接球状半導体素
子を実装した実施例を以下に説明する。球状半導体素子
（３）は、Ｓｉ製の球状半導体（１）にＡｕパンプから
なる接続端子（２）が形成されている。基板（６）は、
プリント配線板（４）にＣｕメッキからなる面接続端子
（５）が形成されている。面接続端子（５）の表面に
は、Ｓｎメッキ層が形成されている。球状半導体素子
（３）と基板（６）とをリフロー炉により接合されてい
る。接合部は、Ａｕ／Ｓｎ系合金が形成されているの
で、その後チップ部品をハンダ実装しても再び融解する
ことはない。An embodiment in which a spherical semiconductor element is directly mounted on a substrate will be described below with reference to FIG. In the spherical semiconductor element (3), a connection terminal (2) made of Au pump is formed on a spherical semiconductor (1) made of Si. The substrate (6)
Surface connection terminals (5) made of Cu plating are formed on the printed wiring board (4). An Sn plating layer is formed on the surface of the surface connection terminal (5). The spherical semiconductor element (3) and the substrate (6) are joined by a reflow furnace. Since the bonding portion is formed of an Au / Sn-based alloy, it does not melt again even when the chip component is solder-mounted thereafter.
【００２０】実装部を覆うようにアンダーフィル材
（７）が充填されている。アンダーフィル材（７）は、
球状半導体素子を構成する球状半導体の仮想の中心線よ
りも高くなるように充填されている。図１では、アンダ
ーフィル材（７）のフィレット（８）が中心線以上に形
成されている。一方、図３では、アンダーフィル材
（７）のフィレット（８）が中心線以下に形成されてい
る。このような構成であると、接続端子周辺の応力緩和
を効果的に向上できなくなる。An underfill material (7) is filled so as to cover the mounting portion. The underfill material (7)
The filling is performed so as to be higher than the virtual center line of the spherical semiconductor constituting the spherical semiconductor element. In FIG. 1, the fillet (8) of the underfill material (7) is formed above the center line. On the other hand, in FIG. 3, the fillet (8) of the underfill material (7) is formed below the center line. With such a configuration, stress relaxation around the connection terminal cannot be effectively improved.
【００２１】図２は、隣り合う球面半導体素子同士が接
続端子により接続される実施例である。この場合、アン
ダーフィル材（７）のフィレット（８）は、垂直方向の
最上部にある接続端子を覆うように充填するのがよい。
接続端子間の信頼性を高めることができるからである。FIG. 2 shows an embodiment in which adjacent spherical semiconductor elements are connected by connection terminals. In this case, the fillet (8) of the underfill material (7) is preferably filled so as to cover the connection terminal at the top in the vertical direction.
This is because the reliability between the connection terminals can be improved.
【００２２】次に、図４及び図５に基づいて、クラスタ
ー状に実装した場合の球状半導体装置を説明する。図４
では、クラスターの最上層の球状半導体素子における中
心線よりも上にアンダーフィル材（７）のフィレット
（８）が形成されている。図５は、隣り合う球面半導体
素子同士が接続端子で接合されている場合である。垂直
方向の最上部に位置する接続端子部が埋設されるように
アンダーフィル材を充填している。Next, a spherical semiconductor device when mounted in a cluster will be described with reference to FIGS. FIG.
In the figure, the fillet (8) of the underfill material (7) is formed above the center line of the spherical semiconductor element in the uppermost layer of the cluster. FIG. 5 shows a case in which adjacent spherical semiconductor elements are joined by connection terminals. The underfill material is filled so that the connection terminal located at the top in the vertical direction is embedded.
【００２３】[0023]
【発明の効果】本発明によれば、球面半導体と実装基板
との熱膨張差に起因するせん断応力によって発生するマ
イクロバンプ接合部の破断を防止した、接続信頼性に優
れた球面半導体装置を提供することができる。According to the present invention, there is provided a spherical semiconductor device excellent in connection reliability which prevents breakage of a micro-bump joint caused by shear stress caused by a difference in thermal expansion between a spherical semiconductor and a mounting substrate. can do.
【図１】基板に直接球状半導体素子を実装した実施例で
ある球状半導体装置の説明図。FIG. 1 is an explanatory view of a spherical semiconductor device which is an embodiment in which a spherical semiconductor element is directly mounted on a substrate.
【図２】基板に直接球状半導体素子を実装するととも
に、隣接する球状半導体素子同士を接合した実施例であ
る球状半導体装置の説明図。FIG. 2 is an explanatory view of a spherical semiconductor device which is an embodiment in which a spherical semiconductor element is directly mounted on a substrate and adjacent spherical semiconductor elements are joined to each other.
【図３】基板に直接球状半導体素子を実装した比較例で
ある球状半導体装置の説明図。FIG. 3 is an explanatory view of a spherical semiconductor device as a comparative example in which a spherical semiconductor element is directly mounted on a substrate.
【図４】基板に直接クラスター状の球状半導体素子を実
装した実施例である球状半導体装置の説明図。FIG. 4 is an explanatory view of a spherical semiconductor device which is an embodiment in which a cluster-like spherical semiconductor element is directly mounted on a substrate.
【図５】基板に直接クラスター状の球状半導体素子を実
装した実施例である球状半導体装置の説明図。FIG. 5 is an explanatory view of a spherical semiconductor device which is an embodiment in which a cluster-like spherical semiconductor element is directly mounted on a substrate.
１ 球状半導体 ２ 接続端子 ３ 球状半導体素子 ４ プリント配線板 ５ 面接続端子 ６ 基板 ７ アンダーフィル材 ８ フィレット DESCRIPTION OF SYMBOLS 1 Spherical semiconductor 2 Connection terminal 3 Spherical semiconductor element 4 Printed wiring board 5 Surface connection terminal 6 Substrate 7 Underfill material 8 Fillet
Claims (2)
有する球面半導体素子と、該球面半導体素子の実装部周
辺の応力集中を緩和するためのアンダーフィル材とから
構成される球面半導体装置であって、 前記球面半導体素子が前記接続端子によって前記基板の
面接続端子に接続されるとともに、該基板と該球面半導
体素子の間に前記アンダーフィル材が充填されているこ
とを特徴とする球面半導体装置。1. A spherical semiconductor device comprising: a substrate having surface connection terminals; a spherical semiconductor element having connection terminals; and an underfill material for alleviating stress concentration around a mounting portion of the spherical semiconductor element. Wherein the spherical semiconductor element is connected to the surface connection terminal of the substrate by the connection terminal, and the underfill material is filled between the substrate and the spherical semiconductor element. apparatus.
面半導体自体の垂直方向の寸法の中心点に仮想の中心線
を水平方向に引いた場合において、 前記アンダーフィル材の少なくとも一部が前記中心線以
上、かつ、実装時における球面半導体素子の高さ未満の
高さまで充填されていることを特徴とする請求項１に記
載の球面半導体装置。2. When a virtual center line is drawn in a horizontal direction at a center point of a vertical dimension of the spherical semiconductor itself when the spherical semiconductor element is mounted, at least a part of the underfill material is the center line. 2. The spherical semiconductor device according to claim 1, wherein the spherical semiconductor element is filled to a height less than the height of the spherical semiconductor element at the time of mounting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000110370A JP2001298145A (en) | 2000-04-12 | 2000-04-12 | Spherical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000110370A JP2001298145A (en) | 2000-04-12 | 2000-04-12 | Spherical semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001298145A true JP2001298145A (en) | 2001-10-26 |
Family
ID=18622892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000110370A Pending JP2001298145A (en) | 2000-04-12 | 2000-04-12 | Spherical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001298145A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7407833B2 (en) | 2004-04-27 | 2008-08-05 | Advanced Semiconductor Engineering, Inc. | Process for fabricating chip package structure |
-
2000
- 2000-04-12 JP JP2000110370A patent/JP2001298145A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7407833B2 (en) | 2004-04-27 | 2008-08-05 | Advanced Semiconductor Engineering, Inc. | Process for fabricating chip package structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7692278B2 (en) | Stacked-die packages with silicon vias and surface activated bonding | |
| US6657311B1 (en) | Heat dissipating flip-chip ball grid array | |
| US6780675B2 (en) | Flip-chip technique for chip assembly | |
| US6657134B2 (en) | Stacked ball grid array | |
| JP6686040B2 (en) | Semiconductor assembly having bridge module for die-to-die interconnection | |
| US20160079214A1 (en) | Bva interposer | |
| US7566649B2 (en) | Compressible films surrounding solder connectors | |
| US10396114B2 (en) | Method of fabricating low CTE interposer without TSV structure | |
| US20070158856A1 (en) | Gap control between interposer and substrate in electronic assemblies | |
| GB2356083A (en) | Interposer for mounting semiconductor dice on substrates | |
| US6410861B1 (en) | Low profile interconnect structure | |
| WO2011086613A1 (en) | Semiconductor device and method for fabricating same | |
| JP2000100986A (en) | Mounting semiconductor part, mounting structure and method | |
| EP0852395A3 (en) | Method of multiplexed joining of solder bumps to a substrate during assembly of an integrated circuit package | |
| US20070222053A1 (en) | Semiconductor constructions having interconnect structures, methods of forming interconnect structures, and methods of forming semiconductor constructions | |
| JP2004327951A (en) | Semiconductor device | |
| US20050139389A1 (en) | Method of mounting electronic component on substrate without generation of voids in bonding material | |
| US6757968B2 (en) | Chip scale packaging on CTE matched printed wiring boards | |
| US20180190620A1 (en) | Interconnect structures with intermetallic palladium joints and associated systems and methods | |
| JP2001298145A (en) | Spherical semiconductor device | |
| WO2015153296A1 (en) | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation | |
| JP2001298148A (en) | Spherical semiconductor device | |
| US20020081771A1 (en) | Flip chip process | |
| JPS6057957A (en) | Connecting construction | |
| JP2004055660A (en) | Wiring board and semiconductor device |