JP2001291849A - Output delay variable circuit, asic and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of times of required layout up to a delay condition convergence by making the delay time of ASIC variable, also increase the appropriation to a plurality of chips different in AC characteristics, and vary the delay time by following external conditions such as temperatures of the outside, power supply voltages, or the like. SOLUTION: An output delay variable circuit is provided between an output buffer 2 in ASIC and a usable gate l as a logic gate in an output final step of a signal, and controls variably an output delay time of ASIC. This output delay variable circuit has: a delay element 4 for delaying a final step output signal of the usable gate 1 by only a constant time to output; an input terminal 6 for inputting a selecting signal from externally; and a selector 5 which connects a first delay signal as an output signal of the usable gate 1 and a second delay signal as an output signal of the delay element 4 to the input side, and selects any one of the first delay signal and second delay signal according to the selecting signal from the input terminal 6, to output it to the output buffer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a variable output delay circuit, an ASIC, and a semiconductor integrated circuit device, and more particularly to an ASIC.
The present invention relates to an output delay variable circuit that variably controls an output delay time of an (Application Specific Integrated Circuit), an ASIC, and a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Recent advances in semiconductor technology have been remarkable.
High integration and high speed are rapidly progressing. With this high integration, a system which has conventionally been realized by a plurality of semiconductor chips such as LSIs can be realized by one chip. However, with this one-chip implementation, there are many advantages, such as ease of restrictions on the operating frequency of the mounting board due to input / output signal delay between chips, reduction of the number of input / output PINs, and price, but flexible system. There is also a disadvantage that the configuration cannot be adopted. For this reason, a system configuration using a plurality of chips is still often used as before,
One ASIC (Application Specific Integrated Circuit)
It (application-specific integrated circuits) are often used to control chips of different generations. However, in this case, a difference in signal transmission delay between input / output signals of chips of different generations may cause a reduction in diversion.

As devices such as semiconductor chips increase in generation, setup, hold time, and output delay time at the time of input are reduced. By reducing the input setup time and the maximum output delay time, the frequency of the system clock can be increased, and the performance of the entire system improves.
In general, the minimum output delay time is also reduced to the extent that the hold time of a device of the same generation can be satisfied. Therefore, when connecting a device to the previous generation device and outputting a signal to the previous generation device, it is difficult to meet the Hold standard of the previous generation device, and both devices are connected on the board At this time, a measure such as insertion of a delay element must be taken.

Therefore, if it is known in advance that one ASIC may be diverted for controlling a plurality of devices, the ASIC can be diverted when determining and laying out the output buffer of the ASIC. Selection and layout of buffers that can simultaneously satisfy both the maximum output delay that can satisfy the maximum setup time at the highest frequency and the minimum output delay that can satisfy the maximum hold time in a system with potential It is carried out.

[0005]

In the above-mentioned prior art, a logic gate (AND gate, OR gate, flip-flop, etc.) at the final stage of output of an ASIC signal is used to adjust the delay of the output signal. Inserting a delay element between the last stage output of the usable gate and the output buffer,
Techniques such as changing the output buffer, increasing the number of power supply terminals, and fine-tuning the layout position of the last stage of the usable gate are adopted. Tend to. In particular, there is a problem that as the performance of a plurality of devices to which one ASIC is applied is different, the number of layouts required until convergence of delay conditions at the time of design increases.

[0006] Further, depending on the combination of the performances of a plurality of devices, it may not be possible to cope with a system using the plurality of devices with the same single ASIC. There is a problem of doing.

Further, in the prior art, the delay time by the ASIC is fixed, and the delay time cannot be varied according to external conditions such as the external temperature and the power supply voltage. In addition, there is a problem that external conditions that can be applied are limited.

A main object of the present invention is to provide an output delay variable circuit, an ASIC and a semiconductor integrated circuit device which solve the above problems.

[0009]

A first output delay variable circuit according to the present invention is provided in a preceding stage of an output buffer in an ASIC, and is an output delay variable circuit for variably controlling an output delay time of the ASIC. A delay element for delaying an output signal of a usable gate, which is a logic gate at the final stage of signal output in the ASIC, by a predetermined time and outputting the input signal; an input terminal for receiving a selection signal from the outside; A first delay signal that is an output signal of the first delay signal and a second delay signal that is an output signal of the delay element are connected to an input side, and the first delay signal or the second signal is output by the selection signal from the input terminal. A selector for selecting any of the second delay signals and outputting the selected signal to the output buffer.

A second output delay variable circuit according to the present invention comprises an ASIC
The ASIC is provided in the front stage of the internal output buffer.
An output delay variable circuit for variably controlling an output delay time of the ASIC, wherein a delay element for delaying an output signal of a usable gate, which is a logic gate of a signal output final stage in the ASIC, by a predetermined time, and outputting a delay element; A register for setting and registering a selection signal, a first delay signal that is an output signal of the usable gate, and a second delay signal that is an output signal of the delay element are connected to an input side; And a selector for selecting either the first delay signal or the second delay signal according to the selection signal from the selector and outputting the selected signal to the output buffer.

A third output delay variable circuit according to the present invention comprises an ASIC
The ASIC is provided in the front stage of the internal output buffer.
An output delay variable circuit for variably controlling an output delay time of the ASIC, wherein a delay element for delaying an output signal of a usable gate, which is a logic gate of a final stage of signal output in the ASIC, by a fixed time, and outputting an external signal; An input terminal to which a selection signal is input from a register, a register to which a selection signal is previously set and registered, and a first signal which is an output signal of the usable gate.
And the second delay signal, which is the output signal of the delay element, are connected to the input side, and either the input terminal or the selection signal from the register is selected depending on the state of the device equipped with the ASIC. And the first delay signal or the second delay signal
And a selector for selecting one of the delayed signals and outputting the selected signal to the output buffer.

A fourth output delay variable circuit according to the present invention is the third output delay variable circuit according to the third invention, wherein the selector comprises: the selection signal which is made valid only for a predetermined time immediately after power-on of the device. And the selection signal to be made effective at a later time is selectively used between the selection signal from the input terminal and the selection signal from the register.

According to a fifth output delay variable circuit of the present invention, in the third output delay variable circuit of the present invention, the selector comprises: the selection signal that is enabled only for a predetermined time immediately after resetting the device; The selection signal to be made effective in the subsequent time is selectively used between the selection signal from the input terminal and the selection signal from the register.

A sixth output delay variable circuit according to the present invention comprises an ASIC
An output delay variable circuit provided in a preceding stage of an internal output buffer and variably controlling an output delay time of the ASIC when a plurality of semiconductor chips having different AC characteristics are connected in a subsequent stage, wherein the ASIC has a variable output delay time. At least one type of delay element for delaying the output signal of the usable gate, which is the last-stage logic gate, by a different delay time, and one or more delay elements to which a selection signal is externally input Input terminal, a first delay signal that is an output signal of the usable gate, and second to nth delay signals that are output signals of the delay element are connected to the input side, and the A selector for selecting one of the first to n-th delay signals by the selection signal and outputting the selected signal to the output buffer.

An ASIC according to the present invention comprises: an output delay variable circuit according to any one of the first to third output delay variable circuits according to the present invention;
A usable gate which is a logic gate of a final stage of signal output in the IC, an output buffer to which a delay signal from the output delay variable circuit is input, and the delay signal connected to another semiconductor chip via the output buffer And an output terminal for outputting the same to the other semiconductor chip. A first semiconductor integrated circuit device according to the present invention includes a first output delay variable circuit according to the present invention, a usable gate which is a logic gate at a final stage of signal output in an ASIC, and a delay signal from the output delay variable circuit. An ASIC having an output buffer for inputting the ASIC, an output terminal connected to another semiconductor chip and outputting the delay signal via the output buffer to the other semiconductor chip, and an apparatus provided with the ASIC. A signal receiving unit for receiving an external condition, receiving the external condition from the signal receiving unit, comparing the external condition with a predetermined threshold, and determining whether the external condition is equal to or greater than a threshold or less than a threshold. And a CPU for outputting a different selection signal level to the input terminal of the output delay variable circuit.

According to a second semiconductor integrated circuit device of the present invention, there is provided a second output delay variable circuit of the present invention, a usable gate which is a logic gate at a final stage of signal output in an ASIC,
An ASIC comprising: an output buffer that receives a delay signal from the output delay variable circuit; and an output terminal that is connected to another semiconductor chip and outputs the delay signal via the output buffer to the other semiconductor chip. A signal receiving unit for receiving an external condition of the device in which the ASIC is mounted, and receiving the external condition from the signal receiving unit and comparing the received signal with a predetermined threshold value. A CPU that outputs a different selection signal level to the register of the output delay variable circuit depending on whether the value is equal to or more than the value or less than the threshold value.

According to a third semiconductor integrated circuit device of the present invention, the first or second semiconductor integrated circuit device of the present invention is provided.
The external condition is a temperature or a voltage.

[0018]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention, FIG. 2 is a diagram showing a circuit configuration of a second embodiment of the present invention, and FIG. FIG. 9 is a diagram illustrating a circuit configuration according to a third embodiment of the present invention.

According to the present invention, an output delay variable circuit for varying an output delay is provided at an output buffer portion in an ASIC such as a gate array or a standard cell.
3 to 3 differ from each other in the configuration of the output delay variable circuit.

Referring to FIG. 1, there is shown an output delay variable circuit 3 which can select one of two types of output delays by an input signal from an input terminal 6 of the ASIC. The output delay variable circuit 3 is provided between a usable gate 1 which is a logic gate (AND gate, OR gate, flip-flop, etc.) at the final stage of output of an ASIC signal and an output buffer 2. A delay element 4 for delaying the output of the last stage, a selector 5, and an input terminal 6 for variable delay are provided. The selector 5 selects and outputs one of the signal from the delay element 4 and the signal at the last stage output of the usable gate 1 according to the signal level input to the input terminal 6 corresponding to the connected chip. The output of the selector 5 is input to the output buffer 2 connected to the output terminal 7 of the ASIC. The output terminal 7 is connected to one chip for receiving the output signal of the ASIC.

FIG. 2 differs from FIG. 1 in that a register 8 which is provided inside the ASIC and which can be set and registered from outside is provided instead of the input terminal 6 in the variable output delay circuit 3 of FIG. Output delay circuit 3 selectable by
a is shown. Selector 5 of variable output delay circuit 3a
Selects one of the signal from the delay element 4 and the signal at the last stage output of the usable gate 1 according to the signal level corresponding to each chip to be connected according to the preset level from the register 8. Output.

FIG. 3 shows a configuration in which both the input terminal 6 of FIG. 1 and the register 8 of FIG. 2 are provided in the output delay variable circuit 3b. Thus, one of the method using the input terminal 6 and the method using the internal register 8 is effectively used and selectively used. As an example, immediately after the power is turned on or after a reset, an input signal is externally input to the input terminal 6 to enable selection by the input terminal 6, and after a certain time, the input signal level to the input terminal 6 is changed. By doing so, the set value in the internal register 8 may be validated.

Although only one delay element 4 is shown in FIGS. 1 to 3, a plurality of delay elements having different delay amounts are provided, and one of them or the output of the last stage of the usable gate 1 is provided. The signal may be selected by a selector.

Next, the operation of the first to third embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3 and FIGS.

FIG. 4 is a time chart for explaining an allowable output delay to the first semiconductor chip which receives a signal from the ASIC of the present invention. FIG. 5 is a time chart for explaining a second signal receiving from the ASIC of the present invention. 6 is a time chart for explaining an allowable output delay to a semiconductor chip.

FIG. 4 shows an allowable output delay to the first chip of Setup 4.5 [ns] and Hold 1.5 [ns] in a system with a clock frequency of 66.6 [MHz]. +1.0 [n wiring delay on the board and clock skew between chips
s] and -0.4 [ns], the maximum allowable output delay is
9.5 [ns], the minimum value is 1.9 [ns].

FIG. 5 shows the allowable output delay to the second chip of Setup 3.0 [ns] and Hold 1.0 [ns] in a system with a clock frequency of 100 [MHz]. Figure 4 shows the wiring delay on the board and the clock skew between chips.
Considering +1.0 [ns] and -0.4 [ns], the maximum value of the allowable output delay is 6.0 [ns] and the minimum value is 1.4 [ns]. In other words, in order to use one ASIC in both the systems of FIGS. 4 and 5, the output delay must be up to 6.0 [n
s], minimum 1.9 [ns].

Therefore, as in the first chip of FIG. 4, the operating frequency is relatively slow, and therefore the maximum value of the output delay (9.
When a chip that is more difficult to satisfy the case of the minimum value (1.9 ns) than the case of 5 ns) is connected, the output of the final stage of the usable gate 1 delayed by the delay element 4
The level of the input terminal 6 or the level of the internal register 8 is set so as to select. Also, like the second chip in FIG.
On the other hand, if a chip whose operating frequency is relatively fast and it is difficult to satisfy the case where the maximum value (6.0 ns) is less than the minimum value (1.4 ns) of the output delay is connected, the usable gate 1 The level of the input terminal 6 or the level of the internal register 8 is set so that the selector 5 selects the output of the last stage.

In this case, when the final stage output of the usable gate 1 is selected by the selector 5 and output to the second chip, the ASIC is designed so that the delay at the output terminal 7 becomes 1.4 ns or more. deep. When outputting to the first chip, the selector 5 selects the output of the last stage of the usable gate 1 delayed by the delay element 4. Therefore, the delay at the output terminal 7 of the delay element 4 is 1.9 ns. 0.5ns (1.9ns-1.4ns)
The one with the above delay amount is selected.

As described above, one chip is commonly used for a plurality of chips having different allowable output delays (the first and second chips).
Assuming that the ASIC is used, the ASIC is provided with an output delay variable circuit that can handle the allowable delay to both chips, so that when each chip is connected, an appropriate delay can be selected and output. Will be possible.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

In this embodiment, the basic configuration is the same as that of the above-described first embodiment of the present invention. However, the present invention has been further devised when external conditions (temperature, voltage, etc.) change. Things.

When the output of a temperature sensor for detecting the temperature of the outside world is input to the input terminal 6 for variable delay shown in FIG. 1, it becomes possible to prevent the operation from becoming unstable due to the outside temperature or the heating of the apparatus. . For example, when the temperature is low, for example, immediately after the power is turned on in a cold region, a signal delayed by the delay element 4 is output to assure the hold, and after a lapse of time after the power is turned on, the temperature of the device itself is increased due to heat generation. When it rises, an unstable operation can be prevented by outputting a signal to which no delay is inserted. In this case, for example, a threshold value of the temperature is set, and different signal levels are input to the input terminal 6 when the temperature is equal to or higher than the threshold value and when the temperature is lower than the threshold value.

When the output of a voltmeter for checking the power supply voltage is input to the variable delay input terminal 6 shown in FIG. 1, if a voltage drop occurs due to a retrofitting device,
Switching can be performed to reduce the output delay, thereby preventing unstable operation. In this case, for example, a threshold value of the voltage is set, and different signal levels are input to the input terminal 6 when the voltage is equal to or higher than the threshold value and when the voltage is lower than the threshold value.

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing a circuit configuration according to the fifth embodiment of the present invention.

In the fourth embodiment of the present invention,
Although it has been described that the signal level corresponding to the temperature and the voltage is input to the input terminal 6 of FIG. 1 and the selection is instructed from the input terminal 6 to the selector 5, in the present embodiment, the input terminal 6
Is different from that of the first embodiment in that the register 8 instructs the selector 5 to make a selection instead of. The function of this register 8 is
This is as described in FIG.

Referring to FIG. 6, a signal receiving section 9 for receiving the output of an external temperature sensor or voltage sensor and a CPU 10 are added as compared with FIG. These are provided in the semiconductor integrated circuit device on which the ASIC is mounted. Then, the output of the external temperature sensor or voltage sensor is received by the signal receiving unit 9, and the received value is compared with a predetermined threshold value by the CPU 10. Different signal levels are set from the CPU 10 to the register 8. As a result, the same effect as that described in the fourth embodiment of the present invention can be obtained. The setting of the signal level by the CPU 10 of the present embodiment is not limited to the register 8, and the signal level may be output to the input terminal 6 in FIG.

Next, a sixth embodiment of the present invention will be described with reference to FIG.

In the above-described first to fifth embodiments of the present invention, it is assumed that one chip is simultaneously connected to a certain output signal (the output terminal 7 of the ASIC),
Although the output delay variable circuit that varies the output delay according to changes in AC characteristics (data propagation delay characteristics) and the outside world has been described, in the present embodiment, the output terminal 7 of the ASIC is used.
The output delay variable circuit when a plurality of chips having different AC characteristics are connected at the same time will be described.

FIG. 7 is a diagram showing a circuit configuration of a sixth embodiment of the present invention. Two chips (chip A and chip B) are connected to the output terminal 7 of the ASIC, and the input terminal 6 of the ASIC is connected to the output terminal 7 of the ASIC. Is connected to a chip B. It is assumed that the chip A and the chip B have different AC characteristics, and that neither chip needs the same signal at the same time.

In such a configuration, the chip B outputs the variable delay signal to the input terminal 6 only when it is necessary, and otherwise outputs the variable delay signal having the opposite polarity. The selector 5 receives the variable delay signal from the chip B and selects an output delay so that the AC characteristic matches the chip B. When the variable delay signal of the opposite polarity is received from the chip B, the AC characteristic Select output delay to match A. In this way, chip A
Even if the AC characteristics of the chip B and the chip B are different, the ASIC does not have to perform trial and error design to output a signal with a delay that satisfies both of them. Further, since the output section of the ASIC is not configured as in the present invention, it is not necessary to recreate either the chip A or the chip B so as to match the AC characteristics of the other chip.

In the above description, two chips are simultaneously connected to the output terminal 7 of the ASIC. However, three or more chips may be connected. In that case, the ASIC has multiple input terminals for variable delay signal input. Further, the delay element 4 may include a plurality of delay elements having different delay amounts.

[0044]

The first effect of the present invention is that an output delay variable circuit capable of coping with an allowable delay to a plurality of chips is provided in an ASIC, and an appropriate delay is selected and output to each chip. One ASIC can be diverted to multiple chips in common, resulting in increased ASIC diversion. In the past, it was difficult to reuse ASICs in systems with extremely different system frequencies, but the present invention makes it possible.

The second effect is that the convergence of the layout at the time of design can be accelerated. Conventionally, when adjusting the delay of an output signal, a delay element is inserted between the output of the last stage of the usable gate and the output buffer, the output buffer is changed, the number of power supply terminals is increased, or the last stage of the usable gate is adjusted. Although a method of finely adjusting the layout position is employed, the number of required layouts until the delay condition converges tends to increase as the system frequency increases in recent years. On the other hand, according to the present invention in which the delay is externally variable, there is an effect that the required number of layouts until the convergence of the delay condition at the time of design can be reduced.

The third effect is that the selector can be appropriately adjusted by inputting external conditions such as the output of a temperature sensor for detecting the temperature of the outside world and the output of a voltmeter for checking the power supply voltage to the input terminal for variable delay. External delay conditions (temperature and voltage) at maximum and minimum delays
That is, the limitation of the difference can be relaxed and unstable operation can be prevented. Restriction of applicable external conditions means that it is vulnerable to disturbance, and the present invention has the effect of contributing to the design of an ASIC that is resistant to disturbance.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration according to first and fourth embodiments of the present invention.

FIG. 2 is a diagram illustrating a circuit configuration according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a circuit configuration according to a third embodiment of the present invention.

FIG. 4 is a time chart for explaining an allowable output delay to a first semiconductor chip receiving a signal from an ASIC of the present invention.

FIG. 5 is a time chart for explaining an allowable output delay to a second semiconductor chip receiving a signal from the ASIC of the present invention.

FIG. 6 is a diagram illustrating a circuit configuration according to a fifth embodiment of the present invention.

FIG. 7 is a diagram illustrating a circuit configuration according to a sixth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Usable gate 2 Output buffer 3, 3a, 3b Variable output delay circuit 4 Delay element 5 Selector 6 Input terminal 7 Output terminal 8 Register 9 Signal receiving unit 10 CPU

Claims (10)

[Claims] An output delay variable circuit provided in a preceding stage of an output buffer inside an ASIC and variably controlling an output delay time of the ASIC, wherein a user who is a logic gate of a final stage of signal output in the ASIC is provided. A delay element that delays the output signal of the bullgate by a certain time and outputs the input signal; an input terminal to which a selection signal is input from the outside; a first delay signal that is an output signal of the usable gate; A second delay signal, which is an output signal, is connected to an input side, and either the first delay signal or the second delay signal is selected by the selection signal from the input terminal, and the selected signal is supplied to the output buffer. An output delay variable circuit, comprising: a selector for outputting. 2. An output delay variable circuit which is provided at a preceding stage of an output buffer inside an ASIC and variably controls an output delay time of the ASIC, wherein a user which is a logic gate of a final stage of signal output in the ASIC is provided. A delay element for delaying the output signal of the bullgate by a predetermined time and outputting the register; a register for setting and registering a selection signal in advance; a first delay signal as an output signal of the usable gate; A second delay signal, which is an output signal, is connected to an input side, and either the first delay signal or the second delay signal is selected by the selection signal from the register and output to the output buffer; A variable output delay circuit comprising: 3. An output delay variable circuit which is provided in a preceding stage of an output buffer inside the ASIC and variably controls an output delay time of the ASIC, wherein the user is a logic gate of a final stage of signal output in the ASIC. A delay element for delaying the output signal of the bullgate by a certain time and outputting the input signal; an input terminal for receiving a selection signal from outside; a register for setting and registering the selection signal in advance; A certain first delay signal and a second delay signal, which is an output signal of the delay element, are connected to the input side, and the selection signal from the input terminal or the register depends on the state of the device equipped with the ASIC. Is valid, and either the first delay signal or the second delay signal is selected by the validated selection signal and output to the output buffer. Output variable delay circuit, characterized in that a selector. 4. The method according to claim 1, wherein the selector selects, from the input terminal, the selection signal that is valid only for a certain period of time immediately after power-on of the device, and the selection signal that is valid for a period thereafter. 4. The output delay variable circuit according to claim 3, wherein the signal is selectively used between a signal and the selection signal from the register. 5. The selection signal from the input terminal, wherein the selector outputs the selection signal from the input terminal, the selection signal being made valid only for a certain time immediately after the reset of the device, and the selection signal being made valid after that time. 4. The variable output delay circuit according to claim 3, wherein the output signal is selectively used between the register and the selection signal from the register. 6. An output delay variable circuit provided in a preceding stage of an output buffer in an ASIC and variably controlling an output delay time of the ASIC when a plurality of semiconductor chips having different AC characteristics are connected in a subsequent stage. Wherein at least one or more types of delay elements for outputting the output signals of the usable gates, which are logic gates at the final stage of output of signals in the ASIC, by different delay times, respectively, and a selection signal inputted from outside. One or more input terminals, a first delay signal that is an output signal of the usable gate, and second to n-th delay signals that are output signals of the delay element are connected to an input side. A selector for selecting one of the first to n-th delay signals according to the selection signal from the input terminal and outputting the selected signal to the output buffer. Delay variable circuit. 7. An output delay variable circuit according to claim 1, a usable gate which is a logic gate of a final stage of signal output in an ASIC, and a delay signal from said output delay variable circuit. An ASIC comprising: an output buffer to be input; and an output terminal connected to another semiconductor chip and outputting the delay signal via the output buffer to the other semiconductor chip. 8. The variable output delay circuit according to claim 1, further comprising:
A usable gate which is a logic gate of a final stage of signal output in the IC, an output buffer to which a delay signal from the output delay variable circuit is input, and the delay signal connected to another semiconductor chip via the output buffer An ASIC having an output terminal for outputting to the other semiconductor chip,
A signal receiving unit for receiving an external condition of the device equipped with the ASIC; receiving the external condition from the signal receiving unit; comparing the received signal with a predetermined threshold value; C that outputs a different selection signal level to the input terminal of the output delay variable circuit depending on whether it is above or below the threshold value
A semiconductor integrated circuit device comprising a PU. 9. The variable output delay circuit according to claim 2, further comprising:
A usable gate which is a logic gate of a final stage of signal output in the IC, an output buffer to which a delay signal from the output delay variable circuit is input, and the delay signal connected to another semiconductor chip via the output buffer An ASIC having an output terminal for outputting to the other semiconductor chip,
A signal receiving unit for receiving an external condition of the device equipped with the ASIC; receiving the external condition from the signal receiving unit; comparing the received signal with a predetermined threshold value; C that outputs a different selection signal level to the register of the output delay variable circuit depending on whether it is above or below the threshold value
A semiconductor integrated circuit device comprising a PU. 10. The semiconductor integrated circuit device according to claim 8, wherein the external condition is a temperature or a voltage.