JP2001284904A - Phase shifter - Google Patents
Phase shifterInfo
- Publication number
- JP2001284904A JP2001284904A JP2000094375A JP2000094375A JP2001284904A JP 2001284904 A JP2001284904 A JP 2001284904A JP 2000094375 A JP2000094375 A JP 2000094375A JP 2000094375 A JP2000094375 A JP 2000094375A JP 2001284904 A JP2001284904 A JP 2001284904A
- Authority
- JP
- Japan
- Prior art keywords
- hybrid coupler
- phase shifter
- semiconductor element
- terminal
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、マイクロ波帯、
ミリ波帯で信号の位相を電気的に変化させる移相器に関
するものである。TECHNICAL FIELD The present invention relates to a microwave band,
The present invention relates to a phase shifter that electrically changes the phase of a signal in a millimeter wave band.
【0002】[0002]
【従来の技術】図5は例えば、昭和51年電子通信学会
総合大会予稿集pp. 3-121に示された従来の移相器であ
る。図5において、1a、1bは入出力端子、2はハイ
ブリッドカプラ、3a、3bは整合回路、4a、4bは
半導体素子である。また、図6は、例えば半導体素子4
aに順バイアスを印加したON時と逆バイアスを印加し
たOFF時の高周波等価回路である。なお、半導体素子
4aが接続されるハイブリッドカプラ2の端子とはアイ
ソレーションされる端子に接続される半導体素子4bも
同様な等価回路が形成される。2. Description of the Related Art FIG. 5 shows a conventional phase shifter disclosed in, for example, Proceedings of the IEICE General Conference, 1979, pp. 3-121. In FIG. 5, 1a and 1b are input / output terminals, 2 is a hybrid coupler, 3a and 3b are matching circuits, and 4a and 4b are semiconductor elements. FIG. 6 shows, for example, the semiconductor element 4
4A is a high-frequency equivalent circuit when ON is applied with a forward bias and OFF when a reverse bias is applied to a. Note that a similar equivalent circuit is formed for the semiconductor element 4b connected to a terminal that is isolated from the terminal of the hybrid coupler 2 to which the semiconductor element 4a is connected.
【0003】次に動作について説明する。入出力端子1
aから入力した高周波信号は、3dBハイブリッドカプ
ラ2にて等振幅、90度位相差で2分配される。2分配
された一方の高周波信号は、整合回路3aを介して半導
体素子4aに入力され、他方の高周波信号は、整合回路
3bを介して半導体素子4bに入力される。Next, the operation will be described. I / O terminal 1
The high-frequency signal input from a is divided into two signals by the 3 dB hybrid coupler 2 with equal amplitude and a phase difference of 90 degrees. One of the two divided high-frequency signals is input to the semiconductor element 4a via the matching circuit 3a, and the other high-frequency signal is input to the semiconductor element 4b via the matching circuit 3b.
【0004】半導体素子4a、4bがONの場合、半導
体素子4a、4bは、図6(a)に示すように、小さい
抵抗とみなすことができるため、整合回路3a、3bの
先端は小さい抵抗で接地されている。他方、半導体素子
4a、4bがOFFの場合、半導体素子4a、4bは、
図6(b)に示すように、容量とみなすことができるた
め、整合回路3a、3bの先端はキャパシタを介して接
地されている。半導体素子4a、4bをON/OFFす
ることにより、ハイブリッドカプラ2側から見た整合回
路3a、3bのインピーダンスが異なり、反射位相が変
化する。When the semiconductor elements 4a and 4b are ON, the semiconductor elements 4a and 4b can be regarded as having a small resistance as shown in FIG. 6A, so that the tips of the matching circuits 3a and 3b have a small resistance. Grounded. On the other hand, when the semiconductor elements 4a and 4b are OFF, the semiconductor elements 4a and 4b
As shown in FIG. 6B, the matching circuits 3a and 3b are grounded via capacitors because they can be regarded as capacitors. By turning on / off the semiconductor elements 4a and 4b, the impedances of the matching circuits 3a and 3b viewed from the hybrid coupler 2 side differ, and the reflection phase changes.
【0005】整合回路3a、3bで反射した高周波信号
は、ハイブリッドカプラ2に再度入力され、ハイブリッ
ドカプラ2内で、整合回路3aからの高周波信号と整合
回路3bからの高周波信号は合成され、入出力端子1b
から出力される。このように、半導体素子4a、4bを
ON/OFFさせることにより、入出力端子1bから出
力される高周波信号の位相を変化させることが出きる。The high-frequency signals reflected by the matching circuits 3a and 3b are input to the hybrid coupler 2 again, where the high-frequency signal from the matching circuit 3a and the high-frequency signal from the matching circuit 3b are combined and input / output. Terminal 1b
Output from Thus, by turning on / off the semiconductor elements 4a and 4b, the phase of the high-frequency signal output from the input / output terminal 1b can be changed.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上述し
た従来の移相器においては、半導体素子4a、4bをO
Nにした場合の半導体素子4a、4bで発生する損失
と、半導体素子4a、4bをOFFにした場合の半導体
素子4a、4bで発生する損失とが異なるために、移相
切替時に振幅変化が大きいという問題点があった。However, in the conventional phase shifter described above, the semiconductor elements 4a and 4b are
Since the loss that occurs in the semiconductor elements 4a and 4b when N is different from the loss that occurs in the semiconductor elements 4a and 4b when the semiconductor elements 4a and 4b are turned off, the amplitude change is large at the time of phase shift switching. There was a problem.
【0007】この発明は上記のような問題点を解決する
ためになされたもので、移相切替時の振幅変化を小さく
することができる移相器を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a phase shifter capable of reducing an amplitude change at the time of phase shift switching.
【0008】この発明に係る移相器は、ハイブリッドカ
プラと、前記ハイブリッドカプラの第一の端子に接続さ
れた第一の半導体素子と、前記ハイブリッドカプラの第
一の端子に対してアイソレートされる第二の端子に接続
された第二の半導体素子とを備え、前記ハイブリッドカ
プラの半導体素子が接続されていない第三と第四の端子
を入出力端子にした移相器において、前記第一と第二の
半導体素子に抵抗をそれぞれ並列接続し、半導体素子を
ON/OFFさせた場合の損失を等しくしたことを特徴
とするものである。[0008] A phase shifter according to the present invention is isolated from a hybrid coupler, a first semiconductor element connected to a first terminal of the hybrid coupler, and a first terminal of the hybrid coupler. A second semiconductor device connected to a second terminal, wherein the semiconductor device of the hybrid coupler is not connected to the third and fourth terminals as an input / output terminal, the phase shifter, wherein the first and the A resistor is connected in parallel to the second semiconductor element, and the loss when the semiconductor element is turned on / off is equalized.
【0009】また、前記抵抗にキャパシタを直列接続
し、当該直列接続体を前記第一と第二の半導体素子にそ
れぞれ並列接続したことを特徴とするものである。Further, a capacitor is connected in series to the resistor, and the series-connected body is connected in parallel to the first and second semiconductor elements, respectively.
【0010】さらに、前記半導体素子として、ダイオー
ドまたはFETを用いたことを特徴とするものである。Further, the invention is characterized in that a diode or an FET is used as the semiconductor element.
【0011】[0011]
【発明の実施の形態】実施の形態1.図1は、この発明
の実施の形態1に係る移相器を示す構成図である。図1
において、1a、1bは入出力端子、2はハイブリッド
カプラ、3a、3bは整合回路、4a、4bは半導体素
子、5a、5bは抵抗である。また、図2は、例えば半
導体素子4aに順バイアスを印加したON時と逆バイア
スを印加したOFF時の半導体素子4aと抵抗5aの高
周波等価回路図である。なお、半導体素子4aと抵抗5
aが接続されるハイブリッドカプラ2の端子とはアイソ
レーションされる端子に接続される半導体素子4bと抵
抗5bも同様な等価回路が形成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a configuration diagram showing a phase shifter according to Embodiment 1 of the present invention. FIG.
, 1a and 1b are input / output terminals, 2 is a hybrid coupler, 3a and 3b are matching circuits, 4a and 4b are semiconductor elements, and 5a and 5b are resistors. FIG. 2 is a high-frequency equivalent circuit diagram of the semiconductor element 4a and the resistor 5a when the semiconductor element 4a is ON when a forward bias is applied and when the semiconductor element 4a is OFF when a reverse bias is applied. Note that the semiconductor element 4a and the resistor 5
The semiconductor device 4b and the resistor 5b connected to the terminal isolated from the terminal of the hybrid coupler 2 to which a is connected form a similar equivalent circuit.
【0012】次に動作について説明する。入出力端子1
aから入力した高周波信号は、3dBハイブリッドカプ
ラ2にて等振幅、90度位相差で2分配される。2分配
された一方の高周波信号は、整合回路3aを介して半導
体素子4aと抵抗5aに入力され、他方は整合回路3b
を介して半導体素子4bと抵抗5bに入力される。Next, the operation will be described. I / O terminal 1
The high-frequency signal input from a is divided into two signals by the 3 dB hybrid coupler 2 with equal amplitude and a phase difference of 90 degrees. One of the two divided high-frequency signals is input to the semiconductor element 4a and the resistor 5a via the matching circuit 3a, and the other is supplied to the matching circuit 3b.
Is input to the semiconductor element 4b and the resistor 5b via the.
【0013】半導体素子4a、4bがONの場合、半導
体素子4a、4bは、図2(a)に示すように、小さい
抵抗とみなすことができるため、整合回路3a、3bの
先端は小さい等化抵抗と半導体素子4a、4bに並列接
続した抵抗5a、5bで接地されている。他方、半導体
素子4a、4bがOFFの場合、半導体素子4a、4b
は、図2(b)に示すように、容量とみなすことができ
るため、整合回路3a、3bの先端はキャパシタと半導
体素子4a、4bに並列接続した抵抗5a、5bを介し
て接地されている。半導体素子4a、4bをON/OF
Fすることにより、ハイブリッドカプラ2側から見た整
合回路3a、3bのインピーダンスが異なり、反射位相
が変化する。When the semiconductor elements 4a and 4b are ON, the semiconductor elements 4a and 4b can be regarded as having a small resistance as shown in FIG. 2A. It is grounded by a resistor and resistors 5a and 5b connected in parallel to the semiconductor elements 4a and 4b. On the other hand, when the semiconductor elements 4a and 4b are OFF, the semiconductor elements 4a and 4b
Can be regarded as a capacitance, as shown in FIG. 2 (b). Therefore, the tips of the matching circuits 3a and 3b are grounded via capacitors and resistors 5a and 5b connected in parallel to the semiconductor elements 4a and 4b. . ON / OF the semiconductor elements 4a and 4b
By performing F, the impedances of the matching circuits 3a and 3b viewed from the hybrid coupler 2 side differ, and the reflection phase changes.
【0014】整合回路3a、3bで反射した高周波信号
は、ハイブリッドカプラ2に再度入力され、ハイブリッ
ドカプラ2内で、整合回路3aからの高周波信号と整合
回路3bからの高周波信号は合成され、入出力端子1b
から出力される。The high-frequency signals reflected by the matching circuits 3a and 3b are input again to the hybrid coupler 2, where the high-frequency signal from the matching circuit 3a and the high-frequency signal from the matching circuit 3b are combined and input and output. Terminal 1b
Output from
【0015】ここで、半導体素子4a、4bをON/O
FFさせた場合、ハイブリッドカプラ2からみた整合回
路3a、3bの反射位相が変化するために、入出力端子
1bから出力される高周波信号の位相を変化させること
ができる。また、半導体素子4a、4bがON状態での
移相器の損失と、半導体素子4a、4bがOFF状態で
の移相器の損失とが等しくなるように、抵抗5a、5b
の値を設定することにより、移相切り替え時の損失変動
を低減することが可能になる。Here, the semiconductor elements 4a and 4b are turned on / off.
When the FF is performed, since the reflection phases of the matching circuits 3a and 3b as viewed from the hybrid coupler 2 change, the phase of the high-frequency signal output from the input / output terminal 1b can be changed. Also, the resistors 5a, 5b are set so that the loss of the phase shifter when the semiconductor elements 4a, 4b are ON and the loss of the phase shifter when the semiconductor elements 4a, 4b are OFF are equal.
By setting the value, it is possible to reduce the loss fluctuation at the time of phase shift switching.
【0016】実施の形態2.上述した実施の形態1で
は、半導体素子4a、4bに並列に抵抗5a、5bを接
続して、移相切り替え時の振幅差を低減するようにした
ものであるが、半導体素子4a、4bのバイアス電圧が
高い場合に、抵抗5a、5bに流れる電流により、消費
電流が増加してしまう。このような場合に抵抗5a、5
bに電流が流れないようにして、移相切り替え時の損失
差を低減することができる実施の形態を示す。Embodiment 2 In the first embodiment, the resistors 5a and 5b are connected in parallel to the semiconductor elements 4a and 4b to reduce the amplitude difference at the time of phase shift switching. When the voltage is high, current consumption increases due to current flowing through the resistors 5a and 5b. In such a case, the resistors 5a, 5
An embodiment will be described in which a current can be prevented from flowing through b to reduce a loss difference at the time of phase shift switching.
【0017】図3は、このような場合の移相器の構成図
である。図3において、図1に示す実施の形態1と同一
部分は同一符号を付してその説明は省略する。新たな符
号として、6a、6bはキャパシタである。FIG. 3 is a configuration diagram of the phase shifter in such a case. 3, the same parts as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. As new symbols, 6a and 6b are capacitors.
【0018】ここで、半導体素子4a、4bをON/O
FFさせた場合、ハイブリッドカプラ2からみた整合回
路3a、3bの反射位相が変化するために、入出力端子
1bから出力される高周波信号の位相を変化させること
ができる。また、半導体素子4a、4bがON状態での
移相器の損失と、半導体素子4a、4bがOFF状態で
の移相器の損失とが等しくなるように、抵抗5a、5b
の値を設定することにより、移相切り替え時の損失変動
を低減することが可能になる。また、抵抗5a、5bと
直列にキャパシタ6a、6bを接続したことにより、抵
抗5a、5bに電流が流れることが無く、消費電力は増
加しない。Here, the semiconductor elements 4a and 4b are turned ON / O.
When the FF is performed, since the reflection phases of the matching circuits 3a and 3b as viewed from the hybrid coupler 2 change, the phase of the high-frequency signal output from the input / output terminal 1b can be changed. Also, the resistors 5a, 5b are set so that the loss of the phase shifter when the semiconductor elements 4a, 4b are ON and the loss of the phase shifter when the semiconductor elements 4a, 4b are OFF are equal.
By setting the value, it is possible to reduce the loss fluctuation at the time of phase shift switching. Further, since the capacitors 6a and 6b are connected in series with the resistors 5a and 5b, no current flows through the resistors 5a and 5b, and power consumption does not increase.
【0019】実施の形態3.上述した実施の形態1及び
2では、半導体素子4a、4bとしてダイオードを用い
たものであるが、ダイオード以外の半導体素子を用いて
も同様の効果を得ることができる。Embodiment 3 In the first and second embodiments described above, diodes are used as the semiconductor elements 4a and 4b. However, similar effects can be obtained by using semiconductor elements other than diodes.
【0020】図4は、半導体素子としてFETを用いた
場合の実施の形態3に係る構成図である。図4におい
て、図3に示す実施の形態2と同一部分は同一符号を付
してその説明は省略する。新たな符号として、7a、7
bは半導体素子として用いられるFETであり、実施の
形態2と同様な効果を奏する。FIG. 4 is a configuration diagram according to a third embodiment in which an FET is used as a semiconductor element. 4, the same components as those of the second embodiment shown in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. As new codes, 7a, 7
b is an FET used as a semiconductor element, and has the same effect as in the second embodiment.
【0021】なお、上記各実施の形態では、ハイブリッ
ドカプラ2、整合回路3a、3b、半導体素子4a、4
bまたは7a、7b、抵抗5a、5bを個別に組み合わ
せた例について記しているが、上記のすべて、または一
部を半導体基板上に一体化して作成しても同様の効果が
得られる。In each of the above embodiments, the hybrid coupler 2, the matching circuits 3a and 3b, the semiconductor elements 4a and 4
Although an example in which b or 7a, 7b and resistors 5a, 5b are individually combined is described, the same effect can be obtained by integrally forming all or a part of the above on a semiconductor substrate.
【0022】[0022]
【発明の効果】以上のように、この発明によれば、各半
導体素子に抵抗をそれぞれ並列接続し、各半導体素子を
ON/OFFさせた場合の損失を等しくなるようにした
ので、移相切替時の損失変動を低減でき、振幅変化を小
さくすることができる。As described above, according to the present invention, a resistor is connected in parallel to each semiconductor element, and the loss when each semiconductor element is turned ON / OFF is made equal, so that the phase shift switching is performed. The loss fluctuation at the time can be reduced, and the amplitude change can be reduced.
【0023】また、前記抵抗にキャパシタを直列接続し
た直列接続体を各半導体素子にそれぞれ並列接続したの
で、各半導体素子のバイアス電圧が高い場合に、抵抗に
電流が流れないようにして、移相切り替え時の損失差を
低減することができる。In addition, since a series connection body in which a capacitor is connected in series with the resistor is connected in parallel to each semiconductor element, when a bias voltage of each semiconductor element is high, current does not flow through the resistor, and phase shift is performed. The loss difference at the time of switching can be reduced.
【0024】さらに、前記半導体素子として、ダイオー
ドまたはFETを用いて移相器を構成することができ
る。Further, a phase shifter can be constituted by using a diode or an FET as the semiconductor element.
【図1】 この発明の実施の形態1に係る移相器を示す
構成図である。FIG. 1 is a configuration diagram showing a phase shifter according to Embodiment 1 of the present invention.
【図2】 図1の例えば半導体素子4aに順バイアスを
印加したON時と逆バイアスを印加したOFF時の半導
体素子4aと抵抗5aの高周波等価回路図である。FIG. 2 is a high-frequency equivalent circuit diagram of the semiconductor element 4a and the resistor 5a in FIG. 1 when the semiconductor element 4a is ON when a forward bias is applied and when the reverse bias is applied OFF.
【図3】 この発明の実施の形態2に係る移相器を示す
構成図である。FIG. 3 is a configuration diagram showing a phase shifter according to Embodiment 2 of the present invention.
【図4】 この発明の実施の形態3に係る移相器を示す
構成図である。FIG. 4 is a configuration diagram showing a phase shifter according to Embodiment 3 of the present invention.
【図5】 従来例に係る移相器を示す構成図である。FIG. 5 is a configuration diagram illustrating a phase shifter according to a conventional example.
【図6】 図5の例えば半導体素子4aに順バイアスを
印加したON時と逆バイアスを印加したOFF時の半導
体素子4aの高周波等価回路図である。6 is a high-frequency equivalent circuit diagram of the semiconductor element 4a shown in FIG. 5, for example, when the semiconductor element 4a is ON when a forward bias is applied, and when the semiconductor element 4a is OFF when a reverse bias is applied.
1a,1b 入出力端子、2 ハイブリッドカプラ、3
a,3b 整合回路、4a,4b 半導体素子(ダイオ
ード)、5a,5b 抵抗、6a,6b キャパシタ、
7a,7b 半導体素子(FET)。1a, 1b input / output terminal, 2 hybrid coupler, 3
a, 3b matching circuit, 4a, 4b semiconductor element (diode), 5a, 5b resistor, 6a, 6b capacitor,
7a, 7b Semiconductor element (FET).
フロントページの続き (72)発明者 中原 和彦 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 高木 直 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 Fターム(参考) 5J012 HA05 Continuing on the front page (72) Inventor Kazuhiko Nakahara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Nao Takagi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. F term in the company (reference) 5J012 HA05
Claims (3)
の半導体素子と、 前記ハイブリッドカプラの第一の端子に対してアイソレ
ートされる第二の端子に接続された第二の半導体素子と を備え、前記ハイブリッドカプラの半導体素子が接続さ
れていない第三と第四の端子を入出力端子にした移相器
において、 前記第一と第二の半導体素子に抵抗をそれぞれ並列接続
し、半導体素子をON/OFFさせた場合の損失を等し
くしたことを特徴とする移相器。1. A hybrid coupler, a first semiconductor element connected to a first terminal of the hybrid coupler, and a second terminal isolated from the first terminal of the hybrid coupler. A phase shifter having third and fourth terminals, to which the semiconductor element of the hybrid coupler is not connected, as input / output terminals, wherein the first and second semiconductor elements have a resistance. Are connected in parallel, and the loss when the semiconductor element is turned ON / OFF is equalized.
該直列接続体を前記第一と第二の半導体素子にそれぞれ
並列接続したことを特徴とする請求項1に記載の移相
器。2. The phase shifter according to claim 1, wherein a capacitor is connected in series to the resistor, and the series connection is connected in parallel to the first and second semiconductor elements, respectively.
はFETを用いたことを特徴とする請求項1または2に
記載の移相器。3. The phase shifter according to claim 1, wherein a diode or a FET is used as the semiconductor element.
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JP2000094375A JP3647712B2 (en) | 2000-03-30 | 2000-03-30 | Phase shifter |
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JP2000094375A JP3647712B2 (en) | 2000-03-30 | 2000-03-30 | Phase shifter |
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JP3647712B2 JP3647712B2 (en) | 2005-05-18 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1363398A1 (en) * | 2002-01-10 | 2003-11-19 | Mitsubishi Denki Kabushiki Kaisha | Phase shifting circuit and phase shifter |
KR100450690B1 (en) * | 2002-06-26 | 2004-10-01 | 주식회사 아모텍 | Circuit for Compensating Passband Flatness Using Reflection Wave Generator |
KR100500663B1 (en) * | 2002-11-18 | 2005-07-12 | 한국전자통신연구원 | Switched coupler type digital phase shifter using quadrature generator |
KR100536189B1 (en) * | 2002-07-30 | 2005-12-14 | 국방과학연구소 | Wideband 180°-bit phase shifter |
JP2010016551A (en) * | 2008-07-02 | 2010-01-21 | Mitsubishi Electric Corp | Phase shift circuit |
-
2000
- 2000-03-30 JP JP2000094375A patent/JP3647712B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1363398A1 (en) * | 2002-01-10 | 2003-11-19 | Mitsubishi Denki Kabushiki Kaisha | Phase shifting circuit and phase shifter |
EP1363398A4 (en) * | 2002-01-10 | 2008-03-12 | Mitsubishi Electric Corp | Phase shifting circuit and phase shifter |
KR100450690B1 (en) * | 2002-06-26 | 2004-10-01 | 주식회사 아모텍 | Circuit for Compensating Passband Flatness Using Reflection Wave Generator |
KR100536189B1 (en) * | 2002-07-30 | 2005-12-14 | 국방과학연구소 | Wideband 180°-bit phase shifter |
KR100500663B1 (en) * | 2002-11-18 | 2005-07-12 | 한국전자통신연구원 | Switched coupler type digital phase shifter using quadrature generator |
JP2010016551A (en) * | 2008-07-02 | 2010-01-21 | Mitsubishi Electric Corp | Phase shift circuit |
Also Published As
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JP3647712B2 (en) | 2005-05-18 |
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