JP2001284801A - Method of manufacturing multilayer printed board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a multilayer printed wiring board wherein surface flatness of the board can be improved. SOLUTION: This manufacturing method comprises a process wherein a first metal layer on an insulating board 11 is selectively etched and a plurality of first bumps 21 are formed, a process for forming a first insulating resin layer 31 on the first bumps 21, a process wherein a second metal layer 33 is fixed with pressure on the first insulating resin layer 31 and tips of the first bumps 21 are connected with the second metal layer 33 penetrating the first insulating resin layer 31, a process wherein the second metal layer 33 is selectively etched and a plurality of second bumps 41 are formed, a process for forming a second insulating resin layer on the second bumps 41, and a process wherein a third metal layer is fixed with pressure on the second insulating resin layer and tips of the plurality of second bumps are connected with the facing third metal layer penetrating the second insulating resin layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed circuit board, and more particularly to a method for manufacturing a multilayer printed circuit board in which interlayer connections are made by bumps.

[0002]

2. Description of the Related Art In recent semiconductor integrated circuits, the terminal size has been reduced, and the arrangement of bonding pads has been increased from peripheral arrangement to area array arrangement. Along with this, the mounting method has changed from wire bonding mounting to ball
The trend has shifted to flip chip mounting using grid arrays (BGA). In order to respond to these trends, it is necessary to further improve the quality of a printed circuit board for mounting a semiconductor chip. For this purpose, the flatness of the printed circuit board surface, which greatly affects the connection reliability between the semiconductor chip and the printed circuit board, is important. This is because in flip-chip mounting, the solder bumps (solder balls) arranged on the bonding pads arranged on the surface of the semiconductor chip are directly attached to the printed board. This is because, since there is no object that allows such a height, a part where connection failure occurs in some places occurs. In particular, as the integration density of LSI chips has increased, the space between bonding pads has become extremely narrow, and the formed solder bumps have also become smaller. Therefore, a printed circuit board with higher flatness has been demanded.

For this reason, in the case of a multilayer printed circuit board in which laser vias or photo vias are used for interlayer connection, via hole openings are filled with a conductive paste or plating. On the other hand, in a multilayer printed circuit board using bumps (conductive projections used for electrical connection) for interlayer connection, the hole filling step is not required, and future progress is expected. The concept of using bumps for interlayer connection is disclosed in, for example,
No. 1789, and Japanese Unexamined Patent Publication No. Hei.
1601, JP-A-6-342977, JP-A-7-74466, JP-A-7-86711, JP-A-8-78845, JP-A-8-1253
No. 44, for example. According to the techniques described in these publications, a multilayer printed circuit board is manufactured through the following steps. (A) a step of forming a bump at a predetermined position on the insulating substrate by a printing method or a plating method;
A step of embedding a bump from an insulating resin material, (c) a step of inserting and exposing the tip of the bump from the insulating resin material, and laminating and placing a metal foil thereon, and (d) a laminate in which a metal foil is laminated. Pressurizing to connect the tip of the bump to the metal foil surface to form a penetrating conductor wiring portion, and (e) forming a predetermined wiring pattern by etching the metal foil. Through these steps, as described above, it is not necessary to form a via hole for interlayer connection, and thus a hole filling step for flattening the surface is not required.

[0004]

However, in the techniques described in the above publications, the bumps are formed by printing or plating a metal or a conductive paste, so that the controllability of the bump height is poor. Further, there is a problem that the metal foil overlaid thereon is pushed up unevenly, or the tip of the bump penetrating from the metal foil has an uneven height.
In particular, when the number of wiring layers increases, height variations accumulate, and the flatness of the multilayer printed circuit board surface further decreases,
There is a possibility that it may be difficult to secure connection reliability between the semiconductor chip and the multilayer printed board.

As a method of reducing the height variation of the bump, a leveling process such as polishing the tip of the bump has been proposed.
In the case of a fine bump having a size smaller than 0 μm, it is difficult to apply the leveling process.

[0006] The present invention has been made in view of the above,
It is an object of the present invention to provide a method for manufacturing a multilayer printed circuit board that can highly planarize the surface of the board.

Another object of the present invention is to improve the flatness of each layer even in a multilayer printed circuit board in which interlayer connection is performed by bumps, and to achieve excellent flatness as a whole even if the number of layers is increased. An object of the present invention is to provide a method for manufacturing a multilayer printed circuit board.

[0008]

In order to solve the above-mentioned problems, a method of manufacturing a multilayer printed board according to the present invention comprises the steps of (a) providing a supporting substrate having a first metal layer on one main surface of an insulating substrate; Preparing and selectively etching the first metal layer to form a plurality of first bumps; and (b) forming a first insulating resin layer on the first metal layer; (C)
Crimping a second metal layer on the first insulating resin layer and connecting the tips of the plurality of first bumps to the opposing second metal layer through the first insulating resin layer; It is intended to have. Here, the step of forming the plurality of first bumps can be easily performed using a known photolithography technique. That is, an etching mask corresponding to a desired shape of the plurality of first bumps is formed on the first metal layer, and the first metal layer is etched using the etching mask to form the plurality of first bumps. A bump may be formed. For example, a desired etching mask can be formed by applying a resist film or the like on the first metal layer and exposing and developing the resist film. Then, after forming the plurality of first bumps by predetermined etching, the etching mask may be removed. The etching may be wet etching or dry etching such as ion milling.

In the method of manufacturing a multilayer printed board according to the present invention, the plurality of first bumps are formed by etching the first metal layer on the insulating substrate, so that the originally formed plurality of first bumps are formed. Height can be controlled to be constant. Therefore, according to the present invention, the height of the completed first bump is equivalent to the thickness variation (1 to 2 μm) of the first metal layer provided on the insulating substrate. This value is about one digit smaller than the variation in bump height (10 to 30 μm) due to the conventional printing method or plating method. Therefore, the resulting multilayer printed circuit board is
The flatness is much improved than before.

In the present invention, the method may further include the step of selectively etching the first metal layer and etching the remaining metal layer to form a first wiring pattern. Thus, the first wiring pattern can be formed together with the first bump from the first metal layer provided on the insulating substrate. Then, the method may further include a step of selectively etching the second metal layer to form a plurality of second bumps. And
The method may further include the step of selectively etching the second metal layer and etching the remaining metal layer to form a second wiring pattern. Further, in the present invention, the first insulating resin layer and the second metal layer may be integrated in advance. Thereby, a plurality of first
After the bumps are formed, the second metal layer can be formed in one step together with the formation of the first insulating resin layer. Further, in the present invention, the support substrate may be a circuit substrate on which a wiring pattern is formed in advance. This means that the present invention can be applied as long as the first metal layer is provided on a circuit board on which a wiring pattern has been formed in advance. Further, in the present invention, a step of forming a second insulating resin layer on the second metal layer, and a step of crimping the third metal layer on the second insulating resin layer to form tips of the plurality of second bumps And connecting the second insulating resin layer to the opposing third metal layer through the second insulating resin layer. Further, the method may further include a step of forming a third wiring pattern by etching the third metal layer.

Further, in the present invention, the first metal layer is a first copper layer located on the uppermost layer, an intermediate layer below the first copper layer and made of nickel or a nickel alloy, A step of forming a plurality of first bumps, wherein the step of forming the plurality of first bumps includes the step of forming the first copper layer such that a surface of the nickel or nickel alloy intermediate layer is formed. It may be performed by etching until it is exposed. As described above, by using the metal layer having a three-layer structure including the first copper layer, the intermediate layer made of nickel or the nickel alloy, and the second copper layer, the intermediate layer made of nickel or the nickel alloy is used as the intermediate layer. Function as an etching stop layer when etching the first copper layer for bump formation. That is, if the etching rate of the first copper layer is selected to be sufficiently higher than the etching rate of nickel or nickel alloy as the intermediate layer, the etching of the first copper layer is automatically performed when the intermediate layer is exposed. Stop. Accordingly, highly accurate etching can be performed without using any endpoint monitoring. Then, by removing the intermediate layer and patterning the second copper layer, it becomes easy to form a new wiring pattern on the same surface as the bump formation surface. In this case, after the step of forming the plurality of first bumps, the method may further include a step of removing an intermediate layer made of nickel or a nickel alloy whose surface is exposed. Then, after the step of removing the intermediate layer, the method may further include a step of forming a first wiring pattern by etching the second copper layer. Similarly, the second metal layer is a first copper layer located on the uppermost layer, an intermediate layer under the first copper layer and made of nickel or a nickel alloy, and a second layer under the intermediate layer. May have a three-layer structure composed of a copper layer. Thereby, a bump can be formed and a wiring pattern can be formed using the second metal layer. For this reason, a multilayer printed board with extremely high flatness can be easily manufactured. In this case, the second
The step of forming a plurality of second bumps can be further provided by etching the first copper layer constituting the metal layer until the surface of the intermediate layer made of nickel or nickel alloy is exposed. After the step of forming the plurality of second bumps, the intermediate layer made of nickel or a nickel alloy constituting the second metal layer may be removed. Further, after the step of removing the intermediate layer, the method may further include a step of forming a second wiring pattern by etching the second copper layer constituting the second metal layer. Also in this case, the step of forming the second insulating resin layer on the second metal layer and the step of pressing the third metal layer on the second insulating resin layer by pressing A step of penetrating the two insulating resin layers and connecting to the opposing third metal layer. Then, if the method further includes a step of forming the third wiring pattern by etching the third metal layer, the third wiring pattern can be obtained.

In the present invention, the first and second insulating resin layers may use an adhesive. Thereby, when the multilayer printed circuit board is manufactured, the bonding between the layers becomes tight, and the reliability is improved.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. In the following drawings,
The same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the dimensional relationships and ratios of the respective members are different from actual ones. Therefore, specific dimensions of each member should be determined in consideration of the following description. In addition, it is needless to say that dimensional relationships and ratios are different between drawings.

(First Embodiment) FIGS. 1 to 3 are process sectional views for explaining a method of manufacturing a multilayer printed circuit board according to a first embodiment of the present invention.

(A) First, as shown in FIG. 1A, a support substrate 15 having a first metal layer 13 on one main surface of an insulating substrate 11 is prepared. Here, the first metal layer 13
Is for forming bumps and wiring patterns in a later step. As the first metal layer 13,
Copper (Cu) is preferable, and its thickness is 10 μm to 150 μm.
μm is preferred. This is because if it is less than 10 μm, the height as a bump becomes insufficient, while if it exceeds 150 μm, the accuracy of bump formation is reduced. As the support substrate 15 having such a copper layer, a copper-clad laminate is preferable. Specifically, for example, paper, glass cloth,
Copper-clad phenol board, copper-clad paper epoxy board composed of glass mat, base material such as synthetic fiber and thermosetting resin,
Examples include a copper-clad paper polyester substrate, a copper-clad glass epoxy substrate, a copper-clad glass polyimide substrate, and a copper-clad glass Teflon (registered trademark) substrate. Examples of the form in which the base materials are not combined include a copper-clad polyimide substrate, a copper-clad polyester substrate, and a copper-clad polyetherimide substrate. Further, as another form, a laminated plate in which a metal plate is used as a base and a copper foil or the like is interposed via an insulating resin layer, for example, an aluminum-based copper-clad substrate, an iron-based copper-clad substrate, a stainless steel-based copper-clad substrate, a silicon steel-based copper Stretched boards, copper-based copper-clad boards, 42-Alois-based copper-clad boards, and the like can also be used. Also, the support substrate 15
In addition to a hard board, a flexible substrate may be used. Specifically, the first metal layer 13 has a thickness of 60
A copper-clad laminated substrate having a base material thickness of 0.2 mm and a copper layer of μm is prepared. In this laminated substrate, a copper layer is formed on both main surfaces of an insulating substrate, but the copper layer on the lower surface is not shown in FIGS. 1 to 3.

(B) Subsequently, a resist film is applied on the first metal layer 13, and the resist film is patterned by photolithography to form an etching mask for forming bumps. Thereafter, using the etching mask, the first metal layer 13 is selectively etched for a certain time. That is, as shown in FIG. 1B, a relatively thin first metal layer 13 is formed on the bottom as the first remaining metal layer 23.
Of the plurality of first bumps 21 composed of convex portions while leaving a part of
To form After the formation of the plurality of first bumps 21, the etching mask is unnecessary, so that it is removed. Here, the amount of selectively etching the first metal layer 13 is as follows.
The thickness of the first remaining metal layer 23 remaining at the bottom of the concave portion is 1 to
It is preferable that about 18 μm remain. this is,
If the thickness of the first remaining metal layer 23 is less than 1 μm, when a wiring pattern is formed using the first remaining metal layer 23 later,
This is because a defect such as a pinhole appears, which is not preferable. Further, when the thickness of the first remaining metal layer 23 exceeds 15 μm, the accuracy of forming the wiring pattern is reduced.
The etching of the copper as the first metal layer 13 is performed by immersing the entire substrate in the etching solution using an aqueous solution of copper (II) chloride as an etching solution. At this time, the etching amount is adjusted by adjusting the immersion time. The shape of the plurality of first bumps 21 to be formed may be, for example, any vertical shape such as a cone, a column, or a trapezoid, or any planar shape such as a circle, a polygon, or a cross. The dimensions may be arbitrary. However, a plurality of first bumps 21
From the viewpoint of the etching accuracy, the height of the first bump 21 is preferably 10 μm or more and 100 μm or less, and more preferably 30 μm or more and 60 μm or less. As a resist film serving as an etching mask, a film resist film, a liquid resist film, or the like can be used. Further, in etching of solder, nickel, gold foil, or the like, a generally used etching resist film for a printed circuit board may be used. Here, an etching mask is formed using an etching resist film as a resist film. And the copper which is the first metal layer 13 is:
The plurality of first bumps 21 are selectively formed by 45 μm etching while leaving the remaining metal layer 32 of 15 μm. Therefore, the height of the first bump 21 is 45 μm. The etching mask is removed after the bumps are formed.

(C) Subsequently, a resist film is applied to the entire surface of the first remaining metal layer 23 so as to cover the plurality of first bumps 21, and this resist film is patterned by photolithography to form a wiring pattern. An etching mask is formed. The first wiring pattern 25 is formed as shown in FIG. 1C by etching the first remaining metal layer 23 using this etching mask. After that, the etching mask is peeled and removed. Thereby, the insulating substrate 11
On the upper side, the first wiring pattern 25 is formed on the same main surface side as the main surface on which the plurality of first bumps 21 are formed. As the resist film used here, various resist films can be used as described above. The etching of the first remaining metal layer 23 is also performed using an aqueous solution of copper (II) chloride as an etching solution. Specifically, an etching resist film is laminated on both surfaces of the substrate 15, and a wiring pattern is formed on the etching resist film to form an etching mask. Then, the first wiring pattern 25 is formed by further etching the copper that is the first remaining metal layer 23. After forming the first wiring pattern 25, the etching resist film is peeled and removed.

(D) Subsequently, on the substrate 15 on which the plurality of first bumps 21 and the first wiring patterns 25 are formed, FIG.
As shown in (d), the plurality of first bumps 21 and the second metal layer 33 are connected by laminating and compressing the first insulating resin layer 31 and the second metal layer 33. As the insulating resin used here, for example, polycarbonate resin, polysulfone resin, polyetherimide resin, thermoplastic polyimide resin, polyethylene tetrafluoride resin, hexafluoropolypropylene resin, polyetheretherketone resin, vinyl chloride resin, A thermoplastic resin such as a polyethylene resin may be used. In the so-called B-stage state, a thermosetting resin capable of forming required insulating properties and adhesiveness, for example, an epoxy resin, a bismaleimide triazine resin, a polyimide resin, a phenol resin, a polyether resin, a melamine resin, or an uncured resin. Vulcanized (raw rubber) butadiene rubber, butyl rubber, natural rubber, neoprene (registered trademark) rubber, silicone rubber and the like can also be used. further,
These may be a copolymer system or a mixed system, a form in which an inorganic oxide such as glass cloth or mat, or an organic substance such as paper is combined, or a system in which an inorganic oxide powder is added or contained. And the formation of the insulating resin layer,
For example, it can be performed on the substrate surface on which the plurality of first bumps 21 and the first wiring patterns 25 are formed by a screen printing method, a casting roller coating method, a spin coating method, or the like. Furthermore, these insulating resin layers may be those that function as an adhesive in advance, and as the adhesive,
A prepreg, an adhesive sheet, an adhesive film, an adhesive with a copper foil, an adhesive generally used for a printed circuit board or a semiconductor device, or the like may be arbitrarily selected. Substrate 15
And the first insulating resin layer 31 and the second metal layer 33
For press bonding, for example, using a press machine such as a laminating press machine, a mechanical press machine, a laminator, a flip chip bonder, a thermocompression bonding machine, an ultrasonic bonding device, and other general laminating, bonding, crimping, and bonding devices. May be.
In the first embodiment of the present invention, the first insulating resin layer 31
Prepreg having a thickness of 40 μm and a second metal layer 33
After previously bonding and laminating a copper layer having a thickness of 60 μm,
This laminate is placed on the substrate 15 on which the plurality of first bumps 21 and the first wiring patterns 25 are formed, and a bonding pressure of 4.
At the same time, pressure bonding is performed under the conditions of 0 MPa, a processing temperature of 170 ° C., and an atmospheric pressure of 100 Pa, and the first
The bump 21 and the second metal layer 33 are connected.

(E) Subsequently, as shown in FIG.
The plurality of second bumps 4 are formed on the second metal layer 33 in the same manner as the formation of the first bumps 21 on the first metal layer 13.
Form one. Here, an etching resist film is laminated on the surface of the second metal layer 33, and then an etching mask is formed in a shape to be a bump by a photolithography technique. Then, the second metal layer 33 is selectively etched by 45 μm using this etching mask. Thereafter, the etching resist film is peeled and removed. In this step, the second metal layer 33 is not etched, and the second remaining metal layer 43 remains.

(F) Subsequently, as shown in FIG.
The second wiring pattern 45 is formed by the second remaining metal layer 43 in the same manner as the formation of the first wiring pattern 25 on the first metal layer 13 described above. Here, an etching resist film is laminated so as to cover the second bump 41 and the second remaining metal layer 43, and then an etching resist film is formed in a shape to be a wiring pattern by a photolithography technique. 43 is etched.
Then, the etching resist film is peeled off to form a second wiring pattern 45 on the same main surface as the main surface on which the plurality of second bumps 41 are formed.

(G) Subsequently, as shown in FIG.
Formation of First Insulating Resin Layer 31 and First Bump 2
After forming the insulating resin layer 35 and the third metal layer 51 on the plurality of second bumps 41 and the second wiring patterns 45 in the same manner as the connection between the first and second metal layers 33, The insulating resin layer 35 and the third metal layer 51 are pressure-bonded, and the plurality of second bumps 41 and the third metal layer 51 are connected. Here, the third metal layer 51 is for forming the outermost wiring pattern layer of the multilayer printed circuit board. Therefore, since the third metal layer 51 does not need to form bumps as in the case of the second metal layer 33, it is sufficient that the third metal layer 51 has a sufficient thickness for forming a wiring pattern. The thickness of the third metal layer 51 is preferably, for example, 1 to 18 μm. This is because if the thickness is less than 1 μm, defects such as pinholes appear when the wiring pattern is formed, which is not preferable. On the other hand, if the thickness exceeds 15 μm, the accuracy of forming the wiring pattern decreases. Here, a prepreg having a thickness of 40 μm is formed as the insulating resin layer 35 and a copper layer having a thickness of 12 μm is formed as the third metal layer 51. And a plurality of second bumps 41 and third metal layer 5
1 is connected.

(H) Subsequently, as shown in FIG.
Applying a resist film on the third metal layer 51, patterning the resist film by photolithography to form an etching mask for the wiring pattern, and etching the third metal layer 51 using the etching mask; Thus, a third wiring pattern 55 is formed. Here, an etching resist film is laminated on the surface of the copper layer that is the third metal layer 51, and then an etching mask is formed in a shape to be a wiring pattern by a photolithography technique.
The third wiring pattern 55 is obtained by etching the metal layer 51 of FIG. After that, the etching mask is peeled and removed.

Through the above steps, a multilayer printed circuit board having a three-layer structure as shown in FIG. As a result of measurement of the obtained multilayer printed board by a non-contact shape measuring instrument, the flatness of the surface of the multilayer printed board manufactured according to the first embodiment of the present invention was 10.48 cm
At × 10.48 cm, the maximum roughness was 1.5 μm. 1,681 bumps are arranged in this area.

For comparison, a multilayer printed circuit board having the same area where bumps were formed by a printing method was manufactured, and its flatness was measured. The layer structure has a three-layer structure as in the first embodiment of the present invention, and has the same number of bumps. As a result of the measurement, the flatness of the surface of the multilayer printed board on which the bumps were formed by the printing method was unevenness of 5.3 μm at the maximum.

As can be seen from the flatness measurement results as described above, the multilayer printed circuit board manufactured by applying the present invention has higher flatness than the multilayer printed circuit board manufactured by the conventional method. In addition, since the flatness of 1.5 μm unevenness according to the first embodiment of the present invention is sufficiently lower than the height of bumps of a recent semiconductor chip used for flip-chip mounting, for example, a semiconductor integrated circuit by flip-chip mounting is used. Can be improved in reliability.

(Second Embodiment) FIGS. 4 to 6 are process sectional views for explaining a method of manufacturing a multilayer printed circuit board to which the present invention is applied in a second embodiment.

(A) First, as shown in FIG. 4A, a support substrate 60 having a first metal layer 69 having a three-layer structure on one main surface of an insulating substrate 61 is prepared. The first metal layer 69 having the three-layer structure includes the first copper layer 6 located on the uppermost layer.
3. An intermediate layer 65 made of nickel or a nickel alloy is provided below the first copper layer 63, and a second copper layer 67 is provided below the intermediate layer 65. Here, the first
Since the copper layer 63 is for forming a bump, its thickness is preferably 10 to 150 μm. This is because if the thickness is less than 10 μm, the height as a bump is insufficient, while if it exceeds 150 μm, the accuracy of bump formation is reduced. The intermediate layer 65 made of nickel or a nickel alloy serves as an etching stop layer when bumps are formed. Therefore, the thickness may be extremely thin as long as there is no permeation or leakage of the etching solution.
A thickness of 04-1.5 μm is sufficient. But 0.4
If the thickness is less than μm, defects such as pinholes may occur, and this may not be sufficient as an etching stop layer during copper etching.
On the other hand, with respect to the upper limit, even if the thickness exceeds 1.5 μm, there is no problem in the function as an etching stop layer. Therefore, the cost is disadvantageous. Therefore, the upper limit thickness is preferably about 1.5 μm. The second copper layer 67 is for forming a wiring pattern later. For this reason, the thickness is preferably 1 to 18 μm. This is because when the thickness is less than 1 μm, defects such as pinholes appear.
If the thickness exceeds 5 μm, the accuracy of forming the wiring pattern is reduced. Therefore, for example, a copper layer 63 having a thickness of 45 μm as the uppermost layer, an intermediate layer 65 made of a nickel-phosphorus alloy having a thickness of 0.1 μm thereunder, and a copper layer 67 having a thickness of 6 μm below therebelow. A copper-clad laminate having a base material thickness of 0.2 mm and one metal layer (three-layer metal layer) 69 is prepared.

(B) Subsequently, a resist film is applied on the first copper layer 63 of the support substrate 60, and the resist film is patterned by photolithography to form an etching mask for forming bumps. After that, using the etching mask, the first copper layer 63 is etched to form a plurality of first bumps 71. At this time, the etching of the first copper layer 63 automatically stops when the intermediate layer 65 is exposed. Thereafter, the resist film serving as an etching mask is peeled and removed, and only the intermediate layer 65 made of nickel or a nickel alloy is selectively removed with a predetermined nickel etching solution. Also in the etching of the intermediate layer 65 made of nickel or a nickel alloy, the etching automatically stops when the second copper layer 67 is exposed. Thus, as shown in FIG. 4B, the plurality of first bumps 71 are formed with the second copper layer 67 remaining as it is and the surface thereof is exposed. The shape of the plurality of first bumps 71 formed here may be, for example, any vertical shape such as a cone, a column, or a trapezoid, or any planar shape such as a circle, a polygon, or a cross. Although the dimensions may be arbitrary, the height is preferably from 10 μm to 100 μm, and more preferably from 30 μm to 60 μm, from the viewpoint of the accuracy of the bump etching process. As the resist film used here, various resist films can be used as in the first embodiment. The first copper layer 63 is etched using an aqueous solution of copper (II) chloride as an etchant, as in the first embodiment described above. Does not require control. Because, as described above, since the intermediate layer 65 made of nickel or a nickel alloy serving as an etching stop layer is provided under the first copper layer 63, even if the intermediate layer 65 is immersed in the etching solution for a somewhat longer time, This is because the underlying second copper layer 67 is not etched.

(C) Subsequently, a resist film is applied to the entire surface of the exposed second copper layer 67 so as to cover the plurality of first bumps 71, and the resist film is patterned by photolithography. Then, an etching mask for a wiring pattern is formed. Then, by etching the second copper layer 67 using this etching mask, FIG.
As shown in (c), a first wiring pattern 75 is formed. After that, the etching mask is peeled and removed. As the resist film used here, various resist films can be used as in the first embodiment. Also,
The etching of the second copper layer 67 is also preferably performed using an aqueous solution of copper (II) chloride as an etching solution. Thereby, the first wiring pattern 75 is formed on the insulating substrate 61 on the same main surface side as the main surface on which the first bumps 71 are formed. In the second embodiment of the present invention, an etching resist film is laminated on both surfaces of the substrate 60, and then the resist film is patterned into a shape to be a wiring pattern by a photolithography technique to form an etching mask. Then, using this etching mask, the second
The first wiring pattern 75 is formed by etching the copper layer 67 of FIG. After forming the first wiring pattern 75, the etching mask is peeled and removed.

(D) Subsequently, as shown in FIG.
On the plurality of first bumps 71 and the first wiring patterns 75,
A first insulating resin layer 81 is formed, and a second metal layer (three-layer metal layer) 99 having a three-layer structure is further formed thereon to form a plurality of first bumps 71 and at least a second copper layer. Crimping is performed so that 97 is connected. The second metal layer 99 having a three-layer structure includes
It comprises a first copper layer 93, an intermediate layer 95 made of nickel or a nickel alloy, and a second copper layer 97. Here, as the insulating resin layer, various resin materials and adhesive materials can be used as in the first embodiment. Further, since the first copper layer 93 is for forming a bump in the same manner as the formation of the first bump 71, the thickness is preferably 10 to 150 μm. The intermediate layer 95 made of nickel or a nickel alloy serves as an etching stop layer.
A thickness of 04-1.5 μm is sufficient. Further, the second copper layer 97 is for forming a wiring pattern later,
The thickness is preferably 1 to 18 μm. In the second embodiment of the present invention, the first copper layer 9
3, a copper layer 93 having a thickness of 45 μm and a thickness of 0.1
an intermediate layer 95 made of a nickel-phosphorous alloy having a thickness of μm, and a second metal layer 9 formed of three layers of a copper layer 97 having a thickness of 6 μm below
9 and an adhesive having a thickness of 35 μm are laminated in advance,
The adhesive layer 81 is arranged so as to be in contact with the plurality of first bumps 71 to form a laminated structure, which is press-bonded under the conditions of a bonding pressure of 3.3 MPa, a processing temperature of 177 ° C., and an atmospheric pressure of 100 Pa, to form and integrate. Thus, the plurality of first bumps 71 penetrate the adhesive layer (insulating resin layer) 81 and face the second bumps 71.
Is connected to the metal layer 97.

(E) Subsequently, a resist film such as an etching resist film is applied on the first copper layer 93, and the resist film is patterned by photolithography to form an etching mask for forming bumps. I do. Thereafter, the first copper layer 93 is etched using this etching mask to form a plurality of second bumps 101. At this time, the etching of the first copper layer 93 automatically stops when the intermediate layer 95 is exposed. Thereafter, the resist film serving as an etching mask is peeled off, and only the intermediate layer 95 made of nickel or a nickel alloy is selectively etched away with a nickel etching solution. As a result, as shown in FIG.
A plurality of second bumps 101 are formed in a state where the second copper layer 97 remains as it is and its surface is exposed. At this time, the etching of the first copper layer 93 and the intermediate layer 95, the used resist film, and the like may be the same as those in the step of forming the first bump 71 described above.

(F) Then, the entire surface of the exposed second copper layer 97 is covered so as to cover the plurality of second bumps 101.
Apply a resist film such as an etching resist film,
This resist film is patterned by a photolithography technique to form an etching mask for a wiring pattern. Then, by etching the second copper layer 97 using this etching mask, the second wiring pattern 105 is formed as shown in FIG. After that, the etching mask is peeled and removed. As the resist film used here, various resist films other than the etching resist film can be used. Also, the etching of the second copper layer 97 is preferably performed using a copper (II) chloride aqueous solution as an etching solution. Thereby, the second wiring pattern 105 is obtained on the same main surface side as the main surface on which the plurality of second bumps 101 are formed.

(G) Subsequently, as shown in FIG.
After the second insulating resin layer 85 and the third metal layer 111 are formed on the plurality of second bumps 101 and the second wiring patterns 105, they are press-bonded to form the plurality of second bumps 101 and the third metal layer 111. Connect. Here, the third metal layer 111
Is for forming the outermost wiring pattern layer of the multilayer printed circuit board. Therefore, the third metal layer 111
Since there is no need to form a bump, it is sufficient that the bump has a thickness sufficient to form a wiring pattern. Third metal layer 111
Is preferably 1 to 18 μm, for example. If the thickness is less than 1 μm, defects such as pinholes appear when a wiring pattern is formed, which is not preferable.
If the thickness exceeds 15 μm, the accuracy of forming the wiring pattern is reduced. In the second embodiment of the present invention, the third
The second metal layer with a 12 μm thick copper layer to be
The adhesive layer 85 and the second bump 101 are disposed so as to be in contact with each other by using an adhesive having a thickness of 35 μm to become the insulating resin layer 85 to form a laminated structure. Crimping is performed under pressure of 100 Pa to form and integrate. Thus, the plurality of second bumps 101 and the copper layer that is the second metal layer 85 are connected.

(H) Subsequently, as shown in FIG.
A resist film such as an etching resist film is applied on the third metal layer 111, and the resist film is patterned by a photolithography technique to form an etching mask for a wiring pattern, and the third metal layer is formed via the etching mask. Third by etching 111
The wiring pattern 115 is formed. After that, the resist film is peeled off.

Through the above steps, a multilayer printed circuit board having a three-layer structure as shown in FIG. 6H is completed. About the obtained multilayer printed circuit board, the flatness was measured using a non-contact shape measuring instrument, and as a result, the flatness of the surface of the multilayer printed circuit board manufactured according to the second embodiment of the present invention was: In an area of 10.48 cm × 10.48 cm, the maximum roughness was 0.8 μm. Further, for comparison, a multilayer printed circuit board having bumps formed by a printing method in the same area was manufactured, and its flatness was measured. The layer structure has a three-layer structure and the same number of bumps as in the second embodiment of the present invention. As a result of the measurement, the flatness of the surface of the multilayer printed board on which the bumps were formed by the printing method was unevenness of up to 6.6 μm.

As can be seen from the above-described flatness measurement results, the multilayer printed circuit board manufactured by applying the second embodiment of the present invention has a flatter flatness than the multilayer printed circuit board manufactured by the conventional method. It can be seen that is high. Further, since the flatness of 0.8 μm unevenness according to the second embodiment of the present invention is sufficiently lower than the height of the bump of a recent semiconductor chip used for flip chip mounting, for example, the semiconductor integrated circuit by flip chip mounting is used. Can be improved in reliability.

(Other Embodiments) The embodiments to which the present invention is applied have been described above. However, it should be understood that the description and drawings constituting a part of the disclosure of the above embodiments limit the present invention. should not do. From the disclosure of other embodiments described below, various alternative embodiments, examples, and operation modes will be apparent to those skilled in the art.

First, in each of the above-described embodiments, a three-layer structure is shown as the number of layers on which the wiring patterns are formed. However, it goes without saying that the number of layers may be any number.

In the first embodiment, an example has been described in which a bump and a wiring pattern are formed on the same main surface side by selectively etching one metal layer (first metal layer) twice. In the second embodiment, a three-layer metal layer using an intermediate layer serving as an etching stop layer is used.
The example in which the bump and the wiring pattern are formed on the same main surface side has been described. However, these methods are not limited to the case where they are performed independently of each other. That is, the first layer selectively etches one metal layer (the first metal layer) twice to form bumps and wiring patterns on the same main surface side, and the second layer is etched. A bump and a wiring pattern may be formed on the same main surface side using a three-layer metal layer using an intermediate layer serving as a stop layer.

Further, in each embodiment, the formation of the bumps and the formation of the wiring patterns are performed on the same main surface using the same metal layer (first metal layer or three-layer metal layer). These may be performed by another metal layer. For example, a bump may be formed by using a circuit board on which a wiring pattern has been formed in advance as an insulating substrate, and forming a metal layer for bump formation thereon. At this time, if copper is used for the metal layer for forming the bumps, the wiring pattern formed in advance is preferably a metal that is not selectively etched with respect to the etching of copper, such as nickel or a nickel alloy.

[0041]

As described above, according to the present invention, it is possible to manufacture a multilayer printed circuit board having excellent surface flatness. In particular, even in the case of a multilayer printed board in which interlayer connection is performed by bumps, the flatness of each layer is extremely good, so that even when the number of layers is increased, a multilayer printed board with excellent overall flatness is manufactured. It is possible.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view (part 1) for describing a method for manufacturing a multilayer printed circuit board according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 2) for explaining the method for manufacturing the multilayer printed circuit board according to the first embodiment of the present invention.

FIG. 3 is a process sectional view (part 3) for describing the method for manufacturing the multilayer printed circuit board according to the first embodiment of the present invention.

FIG. 4 is a process cross-sectional view (part 1) illustrating a method for manufacturing a multilayer printed circuit board according to the second embodiment of the present invention.

FIG. 5 is a process sectional view (part 2) for describing the method for manufacturing the multilayer printed circuit board according to the second embodiment of the present invention.

FIG. 6 is a process sectional view (part 3) for describing the method for manufacturing the multilayer printed circuit board according to the second embodiment of the present invention.

[Explanation of symbols]

 11, 61 Insulating substrate 13, 69 First metal layer 15, 60 Support substrate 21, 71 First bump 41, 101 Second bump 23 First remaining metal layer 43 Second remaining metal layer 25, 75 First wiring pattern 45, 105 Second wiring pattern 55, 115 Third wiring pattern 31, 81 First insulating resin layer 35, 85 Second insulating resin layer 33, 99 Second metal layer 51, 111 Third metal layer 63, 93 first copper layer 65, 95 middle layer 67, 97 second copper layer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tetsuya Enomoto 48 Wadai, Tsukuba, Ibaraki Prefecture F-term in Hitachi Chemical Co., Ltd. F-term (reference) 5E317 AA21 AA24 BB12 BB15 CC13 CC25 CD25 CD27 GG03 GG17 5E346 AA43 CC16 CC32 CC37 CC41 FF24 GG08 GG22 HH07 HH31

Claims (19)

[Claims] 1. A supporting substrate having a first metal layer on one main surface of an insulating substrate is prepared, and the first metal layer is selectively etched to form a plurality of first bumps. Forming a first insulating resin layer on the first metal layer; pressing a second metal layer on the first insulating resin layer to form a tip of the plurality of first bumps; And a step of penetrating the first insulating resin layer and connecting to the opposing second metal layer. 2. The multi-layer printing method according to claim 1, further comprising the step of selectively etching the first metal layer and etching a remaining metal layer to form a first wiring pattern. Substrate manufacturing method. 3. The method according to claim 1, further comprising the step of selectively etching the second metal layer to form a plurality of second bumps. 4. The method according to claim 1, further comprising the step of selectively etching the second metal layer and etching a remaining metal layer to form a second wiring pattern. The method for producing a multilayer printed circuit board according to claim 1. 5. The multilayer printed circuit board according to claim 1, wherein the first insulating resin layer and the second metal layer are integrated in advance. Production method. 6. The circuit board according to claim 1, wherein the support board is a circuit board on which a wiring pattern is formed in advance.
6. The method for manufacturing a multilayer printed circuit board according to any one of items 5 to 5. 7. A step of forming a second insulating resin layer on the second metal layer; and pressing a third metal layer on the second insulating resin layer to form a plurality of second bumps. 7. The method according to claim 1, further comprising: connecting a tip to the opposing third metal layer by penetrating the second insulating resin layer. 8. Manufacturing method of printed circuit board. 8. The method according to claim 7, further comprising etching the third metal layer to form a third wiring pattern. 9. The method according to claim 9, wherein the first metal layer is a first copper layer located on an uppermost layer, an intermediate layer under the first copper layer, and an intermediate layer made of nickel or a nickel alloy. A step of forming the plurality of first bumps is performed until the surface of the intermediate layer made of nickel or nickel alloy is exposed. The method according to claim 1, wherein the method is performed by etching. 10. The method according to claim 9, further comprising, after the step of forming the plurality of first bumps, a step of removing an intermediate layer made of nickel or a nickel alloy exposing the surface. Of manufacturing a multilayer printed circuit board. 11. After the step of removing the intermediate layer, the first copper layer is further etched by etching the first copper layer.
The method for manufacturing a multilayer printed circuit board according to claim 10, further comprising a step of forming a wiring pattern. 12. The second metal layer includes a first copper layer located on an uppermost layer, an intermediate layer below the first copper layer, and an intermediate layer made of nickel or a nickel alloy, A certain second
The method for manufacturing a multilayer printed circuit board according to any one of claims 9 to 11, wherein the method has a three-layer structure including a copper layer. 13. The method according to claim 1, wherein the first metal layer comprises the first metal layer.
13. The method according to claim 9, further comprising the step of forming a plurality of second bumps by etching the copper layer until the surface of the intermediate layer made of nickel or nickel alloy is exposed. 2. The method for manufacturing a multilayer printed circuit board according to claim 1. 14. The method according to claim 13, further comprising, after the step of forming the plurality of second bumps, a step of removing an intermediate layer made of nickel or a nickel alloy constituting the second metal layer. A method for manufacturing a multilayer printed circuit board according to the above. 15. The method according to claim 15, further comprising, after the step of removing the intermediate layer, a step of forming a second wiring pattern by etching a second copper layer constituting the second metal layer. The method for manufacturing a multilayer printed circuit board according to claim 14. 16. A step of forming a second insulating resin layer on the second metal layer, and pressing a third metal layer on the second insulating resin layer to form a plurality of second bumps. The method according to any one of claims 9 to 15, further comprising: connecting a tip to the opposing third metal layer by penetrating the second insulating resin layer. Manufacturing method of printed circuit board. 17. Etching the third metal layer,
17. The method according to claim 16, further comprising the step of forming a third wiring pattern. 18. The method according to claim 1, wherein the first insulating resin layer is an adhesive. 19. The method according to claim 7, wherein the second insulating resin layer is an adhesive.