JP2001267497A - Variable capacity element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where a lower power source voltage of a portable electronic apparatus causes narrower voltage width applicable to a variable capacity element, resulting in insufficient capacity change coefficient. SOLUTION: With an MOS type capacitor employed as a variable capacity element, a second conductive type diffusion region 15 is provided which covers a first conductive type high-concentration diffusion region 3 constituting a substrate electrode except for the vicinity of the end of a gate insulating film 5, so that a variable resistor is formed within the substrate electrode to enhance the capacitor change coefficient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance element mounted on a temperature-compensated crystal oscillator of an indirect compensation type, a voltage-controlled crystal oscillator, or the like.

[0002]

2. Description of the Related Art A variable capacitance element mounted on a crystal oscillator is typically a variable capacitance diode or a MOS type capacitor, and is a voltage control type variable element utilizing the voltage dependence of a depletion layer width. It is a capacitive element. Of these, M
FIG. 6 shows an example of the OS type capacitor.

FIG. 6A shows an example of a cross section of a conventional MOS capacitor. FIG.
As shown in (a), a gate insulating film 5 is formed on the surface of a first conductivity type semiconductor substrate 1 made of a first conductivity type low concentration diffusion layer.
And the gate electrode 7 is selectively formed.

Then, a high-concentration diffusion region 3 of the first conductivity type is formed in a peripheral portion adjacent to the gate insulating film 5 of the semiconductor substrate 1 of the first conductivity type. The semiconductor substrate 1 of the first conductivity type and the high-concentration diffusion region 3 of the first conductivity type are substrate electrodes of a MOS capacitor.

In this MOS type capacitor, the thickness of the depletion layer 9 formed on the surface of the semiconductor substrate 1 of the first conductivity type changes according to the intensity of the electric field from the gate electrode 7. MOS is inversely proportional to the sum of
The capacitance value of the mold capacitor changes.

FIG. 6 (b) shows a cross section of another conventional MOS type capacitor. FIG.
As shown in (b), a low-concentration diffusion region 11 of the second conductivity type is selectively formed on the surface of the semiconductor substrate 1 of the first conductivity type. Then, the gate insulating film 5 and the gate electrode 7 are selectively formed on the low concentration diffusion region 11 of the second conductivity type.

Further, the second conductive type low concentration diffusion region 11
A high-concentration diffusion region 13 of the second conductivity type is formed in a peripheral portion adjacent to the gate insulating film 5 of FIG. The low concentration diffusion region 11 of the second conductivity type and the high concentration diffusion region 13 of the second conductivity type
Are substrate electrodes of the MOS capacitor.

In the structure shown in FIG. 6B, the potential of the substrate electrode can be applied independently of the potential of the semiconductor substrate 1, so that the potential of the gate electrode 7 matches the potential of the substrate electrode. Even in the case of a MOS capacitor having such a characteristic that there is a maximum change point of the capacitance value in the vicinity, the change range of the capacitance value can be used to the maximum.

By the way, the maximum capacitance and the minimum capacitance of the variable capacitance element in the voltage range to be used are respectively Cmax
And Cmin, the capacity change rate is (Cmax−C
min) / Cmax = 1−Cmin / Cmax.
It is desirable that the variable capacitance element has a large capacitance change rate,
For that purpose, it is necessary to increase Cmax independently of Cmin, or to decrease Cmin independently of Cmax.

In the case of a variable capacitance diode, Cmax is determined substantially only by the area, so that Cmax is independent of Cmin.
It is almost impossible to increase x alone, but M
In the case of an OS-type capacitor, it is possible to increase only Cmax independently of Cmin by reducing the thickness of the gate insulating film. However, there are limitations due to restrictions such as dielectric strength.

In the case of Cmin, only Cmin can be reduced independently of Cmax by reducing the impurity concentration to make the depletion layer easily stretchable. However, the semiconductor substrate, which is a starting material for manufacturing the variable capacitance element, is not intrinsic, and contains impurities having a certain level of concentration variation. The variable capacitance element must be manufactured with a higher concentration than that of the variable capacitance element. Therefore, there is a limit in reducing only Cmin.

[0012] Despite such limitations, when mounted on a temperature-compensated crystal oscillator or a voltage-controlled crystal oscillator, a capacitance change rate that has no practical problem has been ensured until now.

[0013]

However, the power supply of electronic equipment has recently been reduced in voltage, and the voltage width that can be applied to the variable capacitance element has been reduced as compared with before.

For this reason, there is a problem that a sufficient capacitance change rate cannot be secured with the conventional variable capacitance element.

[Object of the Invention] An object of the present invention is to provide a variable capacitance element having a larger capacitance change rate than a conventional variable capacitance element.

[0016]

To achieve the above object, the configuration of the variable capacitance element according to the present invention is as follows.

That is, a first semiconductor layer composed of a low-concentration diffusion region of the first conductivity type, a gate insulating film provided on the surface of the first semiconductor layer, a gate electrode provided on the gate insulating film, A second semiconductor layer, which is formed of a one-conductivity-type high-concentration diffusion region, is adjacent to the gate insulating film and is in contact with the first semiconductor layer, and includes the gate insulating film and the second semiconductor layer; A two-terminal MOS variable capacitance element serving as an output terminal and forming a depletion layer in the first semiconductor layer by applying a control voltage to the gate insulating film; An insulating layer for limiting a contact area between the layer and the second semiconductor layer is provided.

Further, a depletion layer forming region is included in a contact region between the first semiconductor layer and the second semiconductor layer.

Further, the contact region is limited to the vicinity of the depletion layer forming region by the insulating layer.

The first semiconductor layer is a low-concentration diffusion region of the first conductivity type constituting a substrate electrode of the MOS variable capacitance element, and the second semiconductor layer is formed in the low-concentration diffusion region of the first conductivity type. A high-concentration diffusion region of the first conductivity type, wherein the insulating layer is interposed between the low-concentration diffusion region of the first conductivity type and the high-concentration diffusion region of the first conductivity type. And

Further, the insulating layer is a diffusion region of the second conductivity type.

The insulating layer constitutes a support substrate of the MOS type variable capacitance element comprising a semiconductor layer of the first conductivity type, and the first semiconductor layer is formed in the semiconductor layer of the first conductivity type and a gate insulating film. The second semiconductor layer is a low-concentration diffusion region of the second conductivity type provided only in a region opposed to the second conductivity type. It is a high-concentration diffusion region of the second conductivity type provided adjacently.

The semiconductor layer of the first conductivity type is a diffusion region of the first conductivity type.

According to the present invention, in the second semiconductor layer, which is one terminal of the variable capacitor, the contact area with the first semiconductor layer is limited by the insulating layer, and the contact area is variable by the depletion layer. As a result, the contact area acts as a variable resistor. In addition, the direction of increase and decrease of the variable capacitance value changed by the control voltage and the direction of increase and decrease of the variable resistance value changed by the same control voltage are opposite to each other, thereby increasing the capacity change rate.

That is, a variable capacitor and a variable resistor are connected in series, and when the variable capacitor is Cmax, the resistance value of the variable resistor is minimized. When the variable capacitor is Cmin, the resistance of the variable resistor is changed. When the value is maximized, the ratio between the maximum capacitance and the minimum capacitance when the impedance is converted into capacitance is increased, so that the capacitance change rate is increased.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the variable capacitance element according to the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described. FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a configuration of a variable capacitance element according to the embodiment.

[Explanation of First Embodiment: FIGS. 1, 2 and 3] The variable capacitance element in the first embodiment is a MOS capacitor, and as shown in the sectional view of FIG. The gate insulating film 5 and the gate electrode 7 are selectively formed on the surface of the semiconductor substrate 1 of the first conductivity type constituted by the low-concentration diffusion region of the first conductivity type. This semiconductor substrate 1 of the first conductivity type constitutes the first semiconductor layer of the present invention.

Then, in a region adjacent to the gate insulating film 5 in a region in contact with the semiconductor substrate 1 of the first conductivity type,
A first conductivity type high concentration diffusion region 3 which is a semiconductor layer is formed. The semiconductor substrate 1 of the first conductivity type and the high-concentration diffusion region 3 of the first conductivity type are substrate electrodes of a MOS capacitor.

Then, between the high-concentration diffusion region 3 of the first conductivity type and the semiconductor substrate 1 of the first conductivity type, except for the gate insulating film 5 side, the diffusion region of the second conductivity type acting as an insulating layer. 15 are interposed.

The operation of the MOS capacitor of the present invention shown in FIG. 1 is basically the same as that of the conventional MOS capacitor shown in FIG. Therefore, the thickness of the depletion layer 9 formed on the surface of the semiconductor substrate 1 of the first conductivity type changes, and the thickness of the depletion layer 9 and the thickness of the gate insulating film 5 are inversely proportional to the thickness of the MOS type capacitor. The capacitance value changes.

At this time, transmission of the carrier carrying the AC signal between the semiconductor substrate 1 of the first conductivity type and the high-concentration diffusion region 3 of the first conductivity type causes the diffusion region 15 of the second conductivity type to be an obstacle. Therefore, the side where the diffusion region 15 of the second conductivity type does not exist,
That is, it is performed only in the depletion layer forming region near the end of the gate insulating film 5.

As is apparent from FIG. 1, the first conductivity type semiconductor substrate 1 and the first conductive type
The contact area with the high-concentration diffusion region 3 of the conductivity type changes depending on the thickness of the depletion layer 9, and the contact area decreases as the thickness of the depletion layer 9 increases.

Since this reduction in the contact area increases the degree of inhibition of carrier transmission, if expressed by an equivalent circuit,
A decrease in the contact area corresponds to an increase in the resistance value of the variable resistor.

Since the decrease in the contact area means that the thickness of the depletion layer 9 increases, the capacitance value of the MOS type capacitor decreases. That is, the capacitance value and the resistance value change in the same control voltage in opposite directions to each other.

Therefore, the MOS type capacitor of the present invention shown in FIG. 1 can be represented by an equivalent circuit as shown in FIG.

[Explanation of Equivalent Circuit: FIG. 2] As shown in FIG. 2, the variable capacitor according to the present invention is equivalent to a series connection of a variable capacitor 17 and a variable resistor 19. In FIG. 2, the direction of the arrow indicating that it is variable is reversed, which indicates that the direction of change of each value with respect to the control voltage is reversed. FIG. 3 shows such electric characteristics.

[Explanation of Electric Characteristics: FIG. 3] The electric characteristics shown in FIG. 3 are based on the M type having a P-type semiconductor substrate and a P-type gate electrode.
It is an example of an OS type capacitor. Among them, FIG.
FIG. 2 shows the gate electrode voltage with respect to the semiconductor substrate potential.
Shows the relationship between the variable resistor 19 and the resistor R shown in FIG.

As the gate voltage increases from the negative value to the positive value, the contact area between the semiconductor substrate 1 and the high-concentration diffusion region 3 decreases, so that the resistance R monotonously increases.

On the other hand, FIG. 3B shows the relationship between the voltage of the gate electrode based on the potential of the semiconductor substrate and the capacitance C, which is an electrical characteristic generally called a CV curve. The frequency is in the 10 MHz band.

FIG. 3B shows two CV curves, each of which has a CV of only the variable capacitor 17 shown in FIG.
3 shows a curve 21 and a CV curve 23 in a case where a variable capacitor 17 and a variable resistor 19 are connected in series.

The CV curve 21 of only the variable capacitor 17 is
That is, this is a CV curve of the MOS capacitor in the conventional example. As the gate voltage increases from a negative value to a positive value, the thickness of the depletion layer 9 increases.
Decreases monotonically.

In the case where the variable capacitor 17 and the variable resistor 19 exhibiting the above-described behavior are connected in series, when the variable capacitor 17 has a control voltage at which the variable capacitor 17 takes the maximum value, that is, Cmax, the variable resistor 19 has the minimum value (hereinafter, referred to as Cmax). Rmin), and when the variable capacitor 17 has a control voltage that takes the minimum value, that is, Cmin, the variable resistor 19 takes a maximum value (hereinafter, referred to as Rmax).

If this is expressed by impedance,
By the control voltage, the minimum impedance Rmin + 1 /
From jωCmax, the maximum impedance Rmax + 1
/ JωCmin.

When this is compared with the change without the variable resistor 19, that is, the change from the minimum impedance 1 / jωCmax to the maximum impedance 1 / jωCmin, Rmin <Rmax holds.
It is clear that the impedance change is larger in the case where there is.

A large change in impedance means a large change in the amount of transmission of the AC signal, and the capacity change rate is substantially increased. Therefore, in the series connection of the variable capacitor 17 and the variable resistor 19 according to the present invention, a steep CV curve 23 as shown in FIG. 3B is obtained.

As is clear from the above description, a portion serving as a variable resistor is provided on a part of the substrate electrode of the MOS capacitor, and the capacitance value and the resistance value for the same control voltage are:
By adopting a configuration in which the increasing / decreasing directions change in opposite directions, the capacitance change rate of the variable capacitance element can be increased.

In the example shown in FIG. 1, the semiconductor substrate 1 itself is the substrate electrode. However, as shown in FIG. 6B in the conventional example, the semiconductor substrate 1 is selectively formed on the surface of the semiconductor substrate 1 of the first conductivity type. It is also possible to configure the present invention using the low-concentration diffusion region 11 of the second conductivity type as a substrate electrode. This is shown in FIG. 4 as a second embodiment.

[Explanation of Second Embodiment: FIG. 4] As shown in the sectional view of FIG. 4, the surface of the semiconductor substrate 1 of the first conductivity type is
The low concentration diffusion region 11 of the second conductivity type is selectively formed.
Then, on the low concentration diffusion region 11 of the second conductivity type,
The gate insulating film 5 and the gate electrode 7 are selectively formed.

Further, the low concentration diffusion region 11 of the second conductivity type
Is formed in a portion adjacent to the gate insulating film 5 in a region in contact with the gate insulating film 5. The low-concentration diffusion region 11 of the second conductivity type and the high-concentration diffusion region 13 of the second conductivity type are substrate electrodes of the MOS capacitor. That is, in the case of the second embodiment, the low-concentration diffusion region 11 of the second conductivity type corresponds to the first semiconductor layer of the present invention, and similarly, the high-concentration diffusion region 13 of the second conductivity type corresponds to the second semiconductor layer. Equivalent to.

Then, the second conductive type high-concentration diffusion region 13
Except for the gate insulating film 5 side, a first conductivity type diffusion region 25 acting as an insulating layer is interposed between the first conductivity type low concentration diffusion region 11 and the second conductivity type low concentration diffusion region 11.

The operation of the MOS capacitor of the second embodiment shown in FIG. 4 is the same as that of the MOS capacitor of the first embodiment shown in FIG. 1, and it is clear that the capacitance change rate is large.

Next, a third embodiment of the present invention will be described.
FIG. 5 is a sectional view showing the configuration of the variable capacitance element according to the third embodiment of the present invention.

[Explanation of Third Embodiment: FIG. 5] As shown in the sectional view of FIG. 5, a surface of a first conductivity type semiconductor substrate 1 which serves as a support substrate of a MOS capacitor and also functions as an insulating layer, The gate insulating film 5 and the gate electrode 7 are selectively formed.

Then, in the semiconductor substrate 1 of the first conductivity type,
In addition, the low-concentration diffusion region 11 of the second conductivity type is formed only in a portion below the gate insulating film 5, that is, only in a region facing the gate insulating film 5.

Further, in the semiconductor substrate 1 of the first conductivity type,
In addition, a shallow high-concentration diffusion region 13 of the second conductivity type is formed adjacent to the side surface of the low-concentration diffusion region 11 of the second conductivity type. The low-concentration diffusion region 11 of the second conductivity type and the second
The conductive high-concentration diffusion region 13 is the substrate electrode of the MOS capacitor. That is, also in the third embodiment, the low-concentration diffusion region 11 of the second conductivity type corresponds to the first semiconductor layer of the present invention, and the high-concentration diffusion region 13 of the second conductivity type similarly corresponds to the second semiconductor layer. Equivalent to.

In the third embodiment shown in FIG.
The contact between the low-concentration diffusion region 11 of the conductivity type and the high-concentration diffusion region 13 of the second conductivity type is limited to the vicinity of the end of the insulating film 5, that is, the vicinity of the formation region of the depletion layer 9.

Therefore, the operation as the variable capacitor in the third embodiment shown in FIG. 5 is substantially the same as the operation as the variable capacitor in the second embodiment shown in FIG.

The third embodiment shown in FIG. 5 has a simple structure and is easier to manufacture than the first and second embodiments.

[0059]

As described above, a portion serving as a variable resistor is provided at a part of the substrate electrode of the MOS capacitor so that the capacitance value and the resistance value change with opposite polarities with respect to the same control voltage. With this structure, a variable capacitance element having a large capacitance change rate can be provided.

Therefore, when applied to a temperature-compensated crystal oscillator, the temperature compensation range can be expanded, and when applied to a voltage-controlled crystal oscillator, the frequency variable width can be increased, and the effect is very large. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a variable capacitance element according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram illustrating a variable capacitance element according to the present invention.

FIG. 3 is a graph showing electric characteristics of a variable capacitance element according to the present invention.

FIG. 4 is a cross-sectional view illustrating a configuration of a variable capacitance element according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a configuration of a variable capacitance element according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a configuration of a variable capacitance element in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate of first conductivity type 3 high-concentration diffusion region of first conductivity type 5 gate insulating film 7 gate electrode 15 diffusion region of second conductivity type

Claims (7)

[Claims] A first semiconductor layer formed of a low-concentration diffusion region of a first conductivity type; a gate insulating film provided on a surface of the first semiconductor layer; a gate electrode provided on the gate insulating film;
A second semiconductor layer formed of a high-concentration diffusion region of a first conductivity type, adjacent to the gate insulating film and in contact with the first semiconductor layer, wherein the gate insulating film and the second semiconductor layer are respectively In a two-terminal MOS variable capacitance element serving as an input / output terminal and forming a depletion layer in the first semiconductor layer by applying a control voltage to the gate insulating film, the MOS variable capacitance element may A variable capacitance element comprising an insulating layer for limiting a contact region between a semiconductor layer and the second semiconductor layer. 2. The variable capacitance element according to claim 1, wherein a depletion layer forming region is included in a contact region between the first semiconductor layer and the second semiconductor layer. 3. The variable capacitance element according to claim 2, wherein the contact region is limited to a region near a depletion layer forming region by an insulating layer. 4. The first semiconductor layer is a low-concentration diffusion region of a first conductivity type constituting a substrate electrode of a MOS type variable capacitance element, and the second semiconductor layer is disposed in a low-concentration diffusion region of the first conductivity type. It is a high-concentration diffusion region of the first conductivity type formed, wherein the insulating layer is interposed between the low-concentration diffusion region of the first conductivity type and the high-concentration diffusion region of the first conductivity type. The variable capacitance element according to claim 1, 2 or 3, wherein 5. The variable capacitance element according to claim 1, wherein the insulating layer is a diffusion region of the second conductivity type. 6. The insulating layer constitutes a support substrate for a MOS type variable capacitance element comprising a semiconductor layer of a first conductivity type.
The semiconductor layer is a low-concentration diffusion region of the second conductivity type provided only in a region facing the gate insulating film in the semiconductor layer of the first conductivity type, and the second semiconductor layer is formed of the first conductivity type. 4. The variable capacitance according to claim 1, wherein the variable capacitance is a high-concentration diffusion region of the second conductivity type provided in the semiconductor layer and adjacent to a side surface of the low-concentration diffusion region of the second conductivity type. element. 7. The variable capacitance element according to claim 6, wherein the first conductivity type semiconductor layer is a first conductivity type diffusion region.