JP2001257342A - Compound semiconductor device - Google Patents

Abstract

(57) Abstract: A compound semiconductor device has a structure in which there is no step near the gate of the compound semiconductor device and which has the same function as a recess, realizes flattening near the gate, and realizes a gate pattern. Improved accuracy, reduced gate capacitance,
An attempt is made to reduce damage and threshold variation due to recess etching. SOLUTION: A source electrode 28 and a drain electrode 29 formed in contact with an oxidized In conductive layer 27 selectively provided on an n-InAlAs electron supply layer 24, and n-InAlA
Gate electrode 3 directly formed in contact with s electron supply layer 24
4 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a HEMT (hig
electron mobility trans
istor), MESFET (metal semimic)
conductorfield effect tran
The present invention relates to an improvement of a compound semiconductor device including a semiconductor device using a compound semiconductor as a material, such as a semiconductor device.

[0002]

2. Description of the Related Art Among semiconductor devices such as HEMTs and MESFETs, HEMTs, in particular, have low noise, and therefore have an amplifier or a microwave band or a millimeter wave band.
It is used for signal processing circuits in optical communication.

FIG. 8 is a sectional side view showing a conventional example of a HEMT which is one of the compound semiconductor devices. In FIG. 8, 1 is an InP substrate, 2 is an i-InAlAs buffer layer, and 3 is an i-InAlAs buffer layer. InGaAs channel layer, 4 is n-InA
1As electron supply layer, 5 is an n ⁺ -InGaAs cap layer, 5A is a recess, 6 is a SiN surface protective layer, 7 is a gate electrode, 8 is a source electrode, and 9 is a drain electrode.

As is apparent from the drawing, the portion where the gate electrode 7 is formed has a structure in which the cap layer 5 is carved to form a recess 5A, and the electron supply layer 4 is exposed at the bottom.

The recess structure is considered to be a very important part because it greatly affects the threshold value and the high frequency characteristics of the HEMT depending on the accuracy of the formation.

To form a recess structure, a cap layer 5 is formed.
Must be etched with high precision, and
It is known that the occurrence of a step causes a problem of reliability, or that a parasitic capacitance is generated in the vicinity of the gate electrode 7 so that high-frequency characteristics are reduced.

By the way, in general compound semiconductor devices, GaAs is often used as a material. For example, a compound semiconductor device using a material containing In such as a HEMT using InAlAs / InGaAs,
There is an advantage that the operation speed is higher than that of a normal GaAs-based compound semiconductor device.

However, a compound semiconductor containing In is
For example, in the case of forming a recess, there is a problem that the selective etching is difficult, or a property that it easily reacts with a metal electrode or an insulating layer. In particular, the oxide insulating layer is formed on a semiconductor material containing In. When a typical SiO ₂ layer is formed, a conductive layer is generated at the interface, and insulation failure occurs.

Therefore, in order to solve the above problems, it is necessary to improve the reliability by eliminating the step due to the recess and to suppress the increase in the capacitance at the gate.

In order to eliminate the recess, it is sufficient that the cap layer is not formed. However, in that case, the source resistance remarkably increases and the high frequency characteristics deteriorate.

The above problems can be solved by reducing the thickness of the cap layer and reducing the source resistance. By the way, thin the cap layer, and
Means for forming the source electrode and the drain electrode by alloying is considered, but in this case, a problem arises in that alloying proceeds to the channel and the breakdown voltage is reduced.

[0012]

SUMMARY OF THE INVENTION In the present invention, there is provided a structure in which there is no step near the gate of a compound semiconductor device and which has a function equivalent to that of a recess, realizes flattening near the gate, and improves the accuracy of the gate pattern. It seeks to achieve improvements, reduce gate capacitance, and suppress damage and threshold variations due to recess etching.

[0013]

In general, a compound semiconductor containing In easily reacts with an oxide film, so that there are many process restrictions as compared with a compound semiconductor containing no In, and the reliability of device operation is high. In order to avoid this, it is preferable to use an insulating layer containing no oxygen, such as SiN, as the insulating film.

Incidentally, In ₂ O ₃ which is an oxide of In
Is often used as a transparent electrode because it is conductive. However, this In ₂ O ₃ is formed by depositing an insulating layer such as SiO ₂ containing oxygen on a compound semiconductor layer containing In such as InAlAs or InGaAs. Depending on
It can be created at that interface.

Therefore, SiN and SiO _{2 are used} as insulating films.
By selectively using (a) and (b), a conductive layer and an insulating layer can be separately formed on a compound semiconductor layer containing In.

By applying the above knowledge, for example, HE
In the case of MT, I usually appears at the bottom of the recess.
The portion of the electron supply layer made of the n-containing compound semiconductor is Si
An N layer should be formed and insulated, and a conductive layer could be formed on the surface by forming an SiO ₂ layer in a portion corresponding to the cap layer.

However, when an SiO ₂ layer was used, it was found that problems such as a change in the degree of oxidation of In occurred due to the pretreatment, and that the state of In oxide at the interface could not be stably realized.

FIG. 1 is a HEM for explaining the principle of the present invention.
It is a principal part cut-away side view showing T, In the figure, 11 is I
nP substrate, 12 is an i-InAlAs buffer layer, 13 is an i-InGaAs channel layer, 14 is n-InAlAs
An electron supply layer, 15 is a SiN insulating layer, 16 is an In oxide conductive layer, 17 is a source electrode, 18 is a drain electrode, and 19 is S
An iN surface protection layer 20 indicates a gate electrode.

The HEMT shown has an uppermost layer of n-InAl.
Since it is the As electron supply layer 14 and contains In, In oxide is easily generated.

Therefore, the oxidation is usually avoided by avoiding the place where the recess is to be formed, that is, the vicinity of the gate, so that the oxidation
An n conductive layer 16 is generated. At this time, an insulating layer 15 made of SiN, which is a hardly oxidizable material, is formed near the gate.
, The Schottky breakdown voltage at the gate is maintained.

FIG. 2 is a diagram for explaining characteristics relating to the compound semiconductor device according to the present invention.
(B) shows the relationship between the thickness of the n-type conductive layer and the resistance value.
3 shows an energy band diagram in the case where a conductive layer is interposed.

From FIG. 2A, it is observed that the resistance is lower when the thickness of the In oxide layer is about 50 [Å], and according to FIG. Is In
There is also an effect of lowering the barrier between AlAs and the electrode, so that the source electrode and the drain electrode can be formed non-alloy, and the electric field concentration effect as in the case of using an alloy electrode can be reduced.

As described above, in the compound semiconductor device according to the present invention, (1) a compound semiconductor layer containing In (for example, n-InAl
In oxide oxide selectively formed on the As electron supply layer 24)
Electrodes (for example, source electrode 28 and drain electrode 29) formed in contact with a conductive layer (for example, oxidized In conductive layer 27)
And an electrode (for example, a gate electrode 34) directly formed in contact with the In-containing compound semiconductor layer, or

(2) In the above (1), the electrodes formed in contact with the In oxide conductive layer selectively formed on the In-containing compound semiconductor layer are the source electrode and the drain electrode, and Wherein the electrode directly formed in contact with the compound semiconductor layer containing is a gate electrode,
Or

(3) In the above (2), the surface of the In oxide-containing conductive layer and the surface of the compound semiconductor layer containing In in contact with the gate electrode are on the same plane.

By adopting the above-described means, a flat field-effect semiconductor device having no step and having the same action as that of the conventional recess can be realized. Because of the good performance, it is possible to improve the accuracy in forming a gate pattern, reduce the gate capacitance, and suppress damage due to recess etching, threshold variation, and the like.

[0027]

FIG. 3 and FIG. 4 are cutaway side views of a main part of a HEMT in a key step of a process for manufacturing a HEMT according to a first embodiment of the present invention. The description will be made with reference to the drawings such as FIG.

See FIG. 3A. 3- (1) MBE (Molecular Beam Epitax)
The buffer layer 22, the channel layer 23, and the electron supply layer 24 are grown on the substrate 21 by applying the y) method.

Examples of main data relating to the substrate 21 and the like are as follows. About substrate 21 Material: About InP buffer layer 22 Material: i-InAlAs Thickness: 300 [nm] About channel layer 23 Material: i-InGaAs Thickness: 25 [nm] About electron supply layer 24 Material: n-InAlAs Impurity concentration : 3 × 10 ¹⁸ [cm ^-3 ] Thickness: 25 [nm]

3- (2) Plasma CVD (plasma CVD)
The insulating layer 25 made of SiN having a thickness of 500 [Å] is obtained by applying an apour deposition method.
To form

3- (3) A portion corresponding to a normal recess is covered with a resist layer 26 by applying a resist process in lithography technology.

3- (4) The insulating layer 25 is etched using the resist layer 26 as a mask by applying a dry etching method using a CF ₄ -based gas as an etching gas. Remove.

As a result, only the vicinity of the gate, which corresponds to a normal recess, is covered with the insulating layer 25 made of SiN. To etch the insulating layer 25, a wet etching method using buffered hydrofluoric acid as an etchant may be applied.

3- (5) dipped in NH ₄ OH solution to expose n-InAlA
The portion of the electron supply layer 24 made of s is made into an In-rich state by alkali treatment.

3- (6) The oxidized In conductive layer 27 having a thickness of one atomic layer or more is formed by natural oxidation in the atmosphere.

In order to form the oxidized In conductive layer 27, means such as oxygen plasma treatment and anodic oxidation may be employed in addition to natural oxidation. InO _{x is} intentionally formed by a vacuum deposition method or a sputtering method. A conductive layer may be formed, or an In layer of about 2 to 3 atomic layers may be formed by a vacuum evaporation method, and oxidized by the same means as described above. However,
The layer thickness is such that no step is formed on the surface, for example, 100
[Å] The following is desirable.

3- (7) A mask made of a two-layer resist having openings in portions where a source electrode is to be formed and a drain electrode is to be formed by applying a resist process in lithography. Is formed and then the thickness is 100 [Å] / 50 [Å] / 3 by applying the vacuum evaporation method and the lift-off method.
A source electrode 28 and a drain electrode 29 made of AuGe / Ni / Au of 000 [Å] are formed.

In this case, as the two-layer resist, a resist having a higher sensitivity in the lower layer than in the upper layer is preferably used.

3- (8) By applying the plasma CVD method, a thickness of 5
An insulating layer 30 made of 00 [Å] SiN is formed.

At this time, the substrate temperature is set at 300 ° C. to 35 ° C.
When set to 0 [° C], the alloying reaction occurs spontaneously,
Ohmic oxide conductive layer 27 and electron supply layer 24
Contact can be made.

Referring to FIG. 4A, 4- (1) an opening 31A is formed in a portion where a gate electrode is to be formed by applying a resist process in lithography technology.
The resist layers 31, 32 and 33 having 32A and 33A are formed.

In this case, good results can be obtained if the sensitivity in the three resist layers is 32>33> 31.

4- (2) The insulating layer 30 and the insulating layer 2 are formed by applying a dry etching method in which the etching gas is a CF ₄ -based gas.
By performing etching of No. 5, an opening 25A having the same pattern as the opening 31A is formed to expose a part of the electron supply layer 24.

FIG. 4 (B) 4- (2) By applying the vacuum evaporation method and the lift-off method,
A gate electrode 34 made of Al having a thickness of 5000 [Å] is formed.

Since the gate electrode 34 has no In oxide conductive layer 27 immediately below and around the gate electrode 34, the Schottky breakdown voltage is sufficiently maintained.

FIG. 5 and FIG. 6 show H in the process steps when manufacturing the HEMT according to the second embodiment of the present invention.
It is a principal part cut-away side view showing EMT, and it demonstrates below, referring these figures. Note that the same symbols as those used in FIGS. 3 and 4 represent the same parts or have the same meanings.

Referring to FIG. 5A, 5- (1) a buffer layer 22, a channel layer 23 and an electron supply layer 24 are grown on a substrate 21 by applying the MBE method.

The main data relating to the substrate 21 and the like may be exactly the same as the HEMT of the first embodiment.

5- (2) n-InAlA immersed in an NH ₄ OH solution and exposed
The surface of the electron supply layer 24 made of s is made into an In-rich state by alkali treatment.

5- (3) The oxidized In conductive layer 27 having a thickness of one atomic layer or more is formed by natural oxidation in the atmosphere.

In order to form the oxidized In conductive layer 27, as in the first embodiment, other than natural oxidation, means such as oxygen plasma treatment and anodic oxidation may be employed. Then, an InO _x conductive layer may be intentionally formed, or an In layer of about 2 to 3 atomic layers may be formed by a vacuum deposition method, and may be oxidized by the same means as described above. However, the layer thickness must be such that no step is formed on the surface.

5- (4) An insulating layer 25 made of SiN having a thickness of 500 [Å] is formed on the entire surface of the oxidized In conductive layer 27 by applying the plasma CVD method.

5- (5) An opening 26 is formed in a portion corresponding to a normal recess by applying a resist process in lithography technology.
A resist layer 26 having A is formed.

5- (6) The insulating layer 25 is etched using the resist layer 26 as a mask by applying a dry etching method using a CF ₄ -based gas (for SiN) as an etching gas. The resist layer 26 is removed. In this case, the oxidation I
The n conductive layer 27 is naturally removed.

As a result, the insulating layer 25 made of SiN near the gate, which is a portion corresponding to a normal recess, is formed.
Since the In conductive oxide layer 27 is removed in the same pattern as the opening 26A, an opening 27A is generated, and a part of the electron supply layer 24 is exposed at the bottom. The insulating layer 2
In order to etch No. 5, a wet etching method using buffered hydrofluoric acid as an etchant may be applied.

Referring to FIG. 5B, 5- (7) a mask made of a two-layer resist having openings in portions where a source electrode is to be formed and a drain electrode is to be formed by applying a resist process in lithography technology. Then, a dry etching method using a CF ₄ -based gas (for SiN) as an etching gas is applied to form a source electrode contact window and a drain electrode contact window.

5- (8) The thickness is 100 [Å] / 50 [Å] / 3000 by applying the vacuum evaporation method and the lift-off method.
[Å] A source electrode 28 and a drain electrode 29 made of AuGe / Ni / Au are formed.

6 (A) 6- (1) By applying the plasma CVD method, a thickness of 5
An insulating layer 30 made of 00 [Å] SiN is formed.

At this time, the substrate temperature is set at 300 ° C. to 35 ° C.
When set to 0 [° C], the alloying reaction occurs spontaneously,
Ohmic oxide conductive layer 27 and electron supply layer 24
Contact can be made.

6- (2) By applying a resist process in lithography technology, an opening 31A is formed in a portion where a gate electrode is to be formed.
The resist layers 31, 32 and 33 having 32A and 33A are formed.

6- (3) By applying a dry etching method using an etching gas of CF ₄ -based gas, the insulating layer 30 is etched to form an opening 30A having the same pattern as the opening 31A, thereby forming an electron. A part of the supply layer 24 is exposed.

6 (B) 6- (2) By applying the vacuum evaporation method and the lift-off method,
A gate electrode 34 made of Al having a thickness of 5000 [Å] is formed.

FIG. 7 is a fragmentary side view showing the HEMT at a key point in the process of manufacturing the HEMT according to the third embodiment of the present invention. Hereinafter, referring to these drawings, FIG. explain. Note that the same symbols as those used in FIGS. 3 and 4 represent the same parts or have the same meanings.

In the third embodiment, H shown in FIG.
When manufacturing an EMT, a buffer layer 22 on a substrate 21,
The channel layer 23 and the electron supply layer 24 are grown, and then the insulating layer 25 is formed only near the gate corresponding to the recess,
Next, the exposed portion of the electron supply layer 24 is
Until the n conductive layer 27 is formed, and then the source electrode 28 and the drain electrode 29 are formed on the oxidized In conductive layer 27, exactly the same steps as in Embodiment 1 can be employed. explain.

The resist in the lithography technology
By applying the process, a resist film having an opening in a portion where a gate electrode is to be formed is formed. Drying using CF ₄ gas as an etching gas
By applying the etching method, the insulating layer 25 is etched using the resist layer as a mask to form a gate electrode contact window. By applying the vacuum deposition method and the lift-off method, a gate electrode 34 made of Al having a thickness of 5000 [Å] is formed.
To form By applying the plasma CVD method, an insulating layer 30 made of SiN having a thickness of 500 [全面] is formed on the entire surface. By applying a normal lithography technique, the insulating layer 30 is etched to form a pad opening corresponding to each electrode to form an electrode lead-out portion (not shown).

In the present invention, many other modifications can be realized without being limited to the above-described embodiment and without departing from the scope described in the claims.

For example, the material of the insulating layer which can be used in the present invention is SiON, AlN, Al
₂ O _{3 and the} like.

The compound semiconductor containing In includes:
InAlAs, InGaAs, In used in the embodiment
P, of course, InGaP, InAs, InGaAs
P, InAlP, InN, InAlN, InGaN, I
nSb, InAlSb, InAlAsSb, InAlG
Many materials such as aN, InAlAsN, and InAlGaAsN can be applied.

[0069]

In the compound semiconductor device according to the present invention, an electrode formed in contact with an In oxide conductive layer selectively formed on a compound semiconductor layer containing In and a compound semiconductor layer containing the In And an electrode formed directly on the substrate.

By adopting the above configuration, it is possible to realize a flat field-effect semiconductor device having no step and having the same operation as that of forming a conventional recess. Because of the good performance, it is possible to improve the accuracy in forming a gate pattern, reduce the gate capacitance, and suppress damage due to recess etching, threshold variation, and the like.

[Brief description of the drawings]

FIG. 1 is a fragmentary side view showing a HEMT for explaining the principle of the present invention.

FIG. 2 is a diagram for explaining characteristics related to the compound semiconductor device according to the present invention.

FIG. 3 is a cutaway side view showing a main part of the HEMT at a key step in the process of manufacturing the HEMT according to the first embodiment of the present invention.

FIG. 4 is a fragmentary side view showing the HEMT at a key step in the process of manufacturing the HEMT according to the first embodiment of the present invention;

FIG. 5 is a cutaway side view of a main part of the HEMT at a key step in the process of manufacturing the HEMT according to the second embodiment of the present invention.

FIG. 6 is a cutaway side view showing a main part of the HEMT at a key step in the process of manufacturing the HEMT according to the second embodiment of the present invention.

FIG. 7 is a fragmentary side view showing the HEMT at a key step in the process of manufacturing the HEMT according to the third embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part showing a conventional example of a HEMT which is one of the compound semiconductor devices.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Substrate 22 Buffer layer 23 Channel layer 24 Electron supply layer 25 Insulating layer 26 Resist layer 27 In oxide conductive layer 28 Source electrode 29 Drain electrode 30 Insulating layer 31-33 Resist layer 34 Gate electrode

Claims (3)

[Claims] An electrode formed in contact with an In oxide conductive layer selectively formed on a compound semiconductor layer containing In and an electrode formed directly in contact with the compound semiconductor layer containing In. A compound semiconductor device characterized by the above-mentioned. 2. An electrode formed in contact with an In oxide conductive layer selectively formed on a compound semiconductor layer containing In is a source electrode and a drain electrode and is directly in contact with the compound semiconductor layer containing In. 2. The compound semiconductor device according to claim 1, wherein the formed electrode is a gate electrode. 3. The semiconductor device according to claim 1, wherein said I oxide layer is in contact with an In oxide conductive layer and a gate electrode.
3. The compound semiconductor device according to claim 2, wherein the surfaces of the compound semiconductor layer containing n are on the same plane.