JP2001255561A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device wherein it is possible to maintain a potential irrespective of a holding time length, and also the maintained potential is not changed by variation in a potential of a scanning line. SOLUTION: A potential of a signal line is taken into a digital storage circuit by a scanning line signal, and is held for a certain period. Then, as long as the digital storage circuit is in the holding state, a high voltage or a low voltage is applied to a pixel electrode, and a potential holding characteristic at the pixel electrode is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a digital gradation display type liquid crystal display device.

[0002]

2. Description of the Related Art As a conventional digital gradation active matrix type liquid crystal display device, the one described in "Flat Panel Display 91 pages 173 to 180" published by Nikkei BP is standard.

FIG. 2 shows an example of a conventional liquid crystal display device. An active matrix liquid crystal display device can be roughly divided into a pixel matrix portion, a signal line driver circuit, and a scan line driver circuit. Hereinafter, the operation will be described with reference to the drawings.

In a pixel matrix, signal lines and scanning lines are arranged in a matrix, and pixel TFTs are arranged at intersections thereof.
The gate of the pixel TFT is connected to the scanning line, the source is connected to the signal line, and the drain is connected to the pixel electrode. In general, a liquid crystal capacitance between a pixel electrode and a counter electrode cannot have a large value, and therefore, a storage capacitor for holding electric charges is arranged near the pixel electrode. When a voltage exceeding the threshold voltage of the TFT is applied to the scanning line and the TFT is turned on, TF
The drain and source of T are short-circuited, the voltage of the signal line is applied to the pixel electrode, and the liquid crystal and the storage capacitor are charged. When the TFT is turned off, the drain is open,
The charge stored in the liquid crystal and the storage capacitor is held until the next time the TFT is turned on.

FIG. 3 shows an example of a signal line driving circuit of four gradations. Here, the case of four gradations will be described, but the basic operation is the same even when the number of gradations is different. The digital gradation signal is supplied from input terminals 302 and 303 to shift registers 310 and 31.
1 is input. Outputs of the shift registers 310 and 311 are input to shift registers 312 and 313 and latch circuits 314 and 315 of the next stage, and the latch circuits hold data for a certain period. This holding period is determined by the horizontal synchronization signal input to the input terminal 304. The output signal of the latch circuit is input to the decoder 316, and the 2-bit digital signal is converted into four voltage selection signals by the decoder. One of the switch transistors 317 to 320 is selected by the voltage selection signal, and the potential of one of the gray scale voltage lines 305 to 308 is transmitted to the signal line 309.

FIG. 4 shows an example of a scanning line driving circuit. The scanning line driving circuit includes a shift register and NAND circuits 403 and 40.
4. It is composed of inverter type buffers 405 and 406, inputs a start pulse synchronized with a vertical synchronization signal and a clock synchronized with a horizontal synchronization signal, and sequentially drives scanning lines.

[0007]

The above-mentioned conventional liquid crystal display device has the following two problems. The first problem is that when the TFT is in an off state, a leak current flows between the drain and the source, and the electric charge of the pixel is discharged and the potential fluctuates. General N-channel TF
FIG. 5 shows the drain current and gate voltage characteristics of T. FIG.
As can be seen from the graph, even when the gate voltage is negative, current flows through the drain. This current causes the discharge of electric charges. Although the description has been given of the N-channel TFT, the same applies to the P-channel TFT.

Usually, the writing period of the pixel is 100 Hz or less, and the holding time is 10 msec or more. In general, a storage capacitor is provided in parallel with the liquid crystal in order to keep the storage time as long as possible. However, the total capacity of the liquid crystal and the storage capacitor can be only 0.1 pF to 0.2 pF. Assuming that the holding time of the pixel is 16.6 msec (60 Hz), the voltage applied to the liquid crystal is 5 V, the holding ratio is 99%, and the capacitance is 0.2 pF, the allowable leak current of the TFT is 5 × (1−0.99). × 0.2 pF / 16.6 msec
= 0.6 pA, and it is difficult to realize this value including the variation in the operating temperature range and the TFT, so that the electric charge of the pixel is discharged and the image quality is deteriorated.

The second problem is that in the operation of the TFT, when the scanning line potential changes from a high potential to a low potential or from a low potential to a high potential, the drain potential is reduced by the capacitance between the gate and drain of the TFT. Is drawn in the direction in which the scanning line potential changes by ΔV shown in FIG. ΔV = V × Cgd / (Cgd + Clc + Cstg) Here, V is the fluctuation width of the scanning line potential Cgd is the capacitance between the gate and the drain of the TFT Clc is the capacitance of the liquid crystal Cstg is the capacitance of the storage capacitor As shown in (2), the potential of the pixel electrode shifted below the center, causing deterioration of the liquid crystal.

The liquid crystal display device of the present invention solves these two problems. The purpose of the liquid crystal display device is to be able to hold data regardless of the length of the holding time, and to reduce the number of scanning lines. An object is to provide a liquid crystal display device in which a holding potential does not change due to a change in potential.

[0011]

According to the liquid crystal display device of the present invention, a gray scale display method is a time gray scale method, a voltage applied to a pixel is binary only, and one pixel has
It has one digital storage circuit, and its output is connected to a pixel electrode.

[0012]

According to the present invention, the potential of the signal line is taken into the digital storage circuit by the signal of the scanning line, and the potential is held for a certain period. Since the pixel electrode is connected to the output of the digital storage circuit, a high potential or a low potential of the digital storage circuit is applied as long as the storage circuit is in a holding state.

[0013]

FIG. 1 shows an embodiment of the present invention. The time gray scale method is a method in which black and white are temporally switched to produce a halftone as shown in FIG. The operation of the signal line driving circuit of this embodiment will be described. The time-modulated digital gray scale signal is input to a shift register 109 from an input terminal 102, and the output of the shift register 109 is input to a shift register 110 and a latch circuit 111 of the next stage. Is held. This holding period is determined by the horizontal synchronization signal input to the input terminal 103. Outputs of the latch circuits 111 and 112 are buffer circuits 113, 114, 115 and 116 of an inverter type.
Are output to the signal lines 106 and 107 via the. The data of the signal line is converted into digital storage circuits 117, 118, 119, and 120 arranged near each pixel electrode by a scanning line signal.
Get absorbed in. This storage state is held until the next scanning line signal is received. FIG. 8 is an example of a pixel area and a digital storage circuit. This digital storage circuit has a TFT 807,
This is a combination of two inverters 808 and TFTs 809 and 810. When the TFT 806 is turned on, the storage circuit and the signal line 802 are short-circuited and data is taken in.

Since the output of the storage circuit is directly connected to the pixel electrode, the potential of the pixel electrode is fixed to one of the high potential side and the low potential side of the power supply potential of the storage circuit. As described above, since the potential of the pixel is not stored in the capacitor as in the conventional example and is held by the data of the storage circuit instead of holding the potential, the potential change due to the leak current of the pixel TFT and the potential change due to the TFT off are not caused. It does not occur and the image quality can be improved.

Since the liquid crystal element 811 is deteriorated when a DC voltage is applied for a long period of time, in this embodiment, the counter electrode is set to have the same amplitude as the output amplitude of the digital memory circuit.
In addition, the liquid crystal is driven at a specific frequency (such as a vertical synchronization frequency) so that the voltage applied to the liquid crystal becomes zero on average. This relationship is shown in FIG.

FIG. 9 shows a second example of the storage circuit. TFT
An inverter is constituted by 908 and 910 and resistors 907 and 909, and a storage circuit is constituted. In this example,
The operation is the same as that of the above-described embodiment, but it is possible to use only one polarity of the TFT in the pixel matrix.

[0017]

As described above, according to the present invention, the gray scale display method is the time gray scale display method, and the potential can be given to one pixel electrode by one digital storage device. In addition, there is an effect that the potential of the pixel electrode can be kept constant, and thereby an effect that the image quality is improved.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a signal line driving circuit of a liquid crystal display device of the present invention.

FIG. 2 shows a block diagram of an active matrix liquid crystal display device.

FIG. 3 shows an example of a conventional signal line driving circuit.

FIG. 4 illustrates an example of a scanning line driver circuit.

FIG. 5 shows drain current and gate voltage characteristics of a TFT.

FIG. 6 shows retention characteristics of a pixel.

FIG. 7 shows an operation of a time gray scale.

FIG. 8 shows an embodiment of a pixel and a digital storage circuit.

FIG. 9 shows an embodiment of a pixel and a digital storage circuit.

FIG. 10 shows counter electrode and liquid crystal voltage characteristics.

[Explanation of symbols]

Clock input terminal: 101 Start pulse input terminal: 102 Horizontal synchronization signal input terminal: 103 Scan line: 104, 10
5 signal lines: 106, 10
7 Counter electrode connection terminal: 108 Shift register: 109, 11
0 Latch circuit: 111, 11
2 Inverter type buffer: 113 to 11
6 Digital storage circuit: 117-12
0 liquid crystal: 121-12
4 Pixel matrix: 200 Signal line: 201 to 20
3 scanning lines: 204-20
6 TFT: 207-21
0 liquid crystal: 211-21
4 Retention capacity: 215 to 21
8 Clock input terminal: 301 Start pulse input terminal: 302, 30
3 horizontal synchronization signal input terminal: 304 gradation voltage terminal: 305 to 30
8 Signal line connection terminal: 309 Shift register: 310-31
3 Latch circuit: 314, 31
5 Decoder: 316 TFT: 317-32
0 Clock input terminal: 401 Start pulse input terminal: 402 NAND: 403, 40
4 Inverter type buffer: 405, 40
6. Scanning line connection terminals: 407, 40
8 Scanning line: 801 Signal line: 802 Storage circuit power supply terminal: 803, 80
4 Counter electrode terminal: 805 TFT: 806 to 81
0 Liquid crystal: 811 Scan line: 901 Signal line: 902 Storage circuit power supply terminal: 903, 90
4 Counter electrode terminal: 905 TFT: 906, 90
8,910 Liquid crystal: 911 Resistor: 907, 90
9

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[Procedure amendment]

[Submission date] January 22, 2001 (2001.1.2)
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G09G 3/20 641 G09G 3/36 3/36 G02F 1/136 500 H01L 29/786 H01L 29/78 614

Claims (3)

[Claims] At least one pixel electrode provided on a first substrate having a first insulating surface, at least one signal line, at least one scanning line, and connection with the signal line and the scanning line At least one thin film transistor, a digital storage circuit connected to the thin film transistor and the pixel electrode, and a counter electrode provided on a second substrate having a second insulating surface. A display device comprising an inverter including two thin film transistors and two resistors. 2. A signal line driving circuit is connected to the signal line, wherein the signal line driving circuit is connected to at least one shift register, at least one latch circuit connected to the shift register, and the latch circuit. 2. The display device according to claim 1, comprising at least one buffer circuit. 3. The liquid crystal display device according to claim 1, wherein the display device is a liquid crystal display device in which a liquid crystal is held between the first substrate and the second substrate. Display device.