JP2001237739A - Path selection system and path selection circuit for cdm demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small circuit scale for use with many fingers and to also improve sample selection accuracy. SOLUTION: A maximum detecting circuit 15 detects samples which become maximum from among the correlation peak detection output received from a matched filter 14, and a best-16 detection circuit 16 selects higher rank samples which are higher than the number of fingers out of the maximum samples. Thereby the data which are ultimately unnecessary despite their large value can be previously eliminated and as the samples to remain, only the number of samples is necessary by the number of paths for a synthesis ratio calculation part 17 to calculate a synthesis ratio. As a result, the circuit scale can be reduced significantly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CDM (Code Division) used in digital satellite broadcasting for mobile terminals and CDMA digital cellular radio systems, for example.
(Multiple: code spread division multiplexing) The present invention relates to a path selection method and a path selection circuit of a demodulation circuit.

[0002]

2. Description of the Related Art Recently, digital satellite broadcasting technology for next-generation mobile terminals has been actively developed. Among them, a CDM system which is hardly affected by a transmission path environment and capable of multiplex transmission of a large amount of information is used. Promising.

[0003] The CDM system is one of spread spectrum systems in which a plurality of information signals are spread-modulated in the same frequency band with mutually different codes, multiplexed and transmitted.
On the receiving side, a desired information signal can be extracted by despreading with an arbitrary code. In particular, since it is highly resistant to multipath, it is characterized in that reception strength can be secured by RAKE combining a plurality of paths with a plurality of fingers on the receiving side.

In a conventional CDM demodulation circuit, a plurality of fingers use RAKE as a path selection method for a received signal.
When performing combining, RAKE combining is performed after an operation of removing data that is not meaningful as a path due to intersymbol interference while leaving a number of samples about several times the number of fingers to be combined. S to find the ratio
RAKE combining is performed while leaving data for paths necessary for calculating the / I ratio (signal power / interference power ratio).

[0005] However, in this path selection method, when the number of fingers used increases, the number of samples to be left inevitably increases. As a result, when the speed of the spreading code is high, the operating frequency of the matched filter also increases,
It is necessary to perform processing for determining whether input data is a sample to be left in parallel. For this reason, it is necessary to prepare the same number of comparison circuits (comparators) as the number of remaining samples, and the circuit scale becomes very large. Also, post-processing is required to remove samples due to intersymbol interference, and there is a possibility that samples other than the pass remain even after the post-processing.

[0006]

As described above, in the conventional path selection method of the CDM demodulation circuit, the number of samples to be retained increases as the number of fingers used increases. When the operating frequency is high, in order to perform the sample selection determination processing in parallel, it is necessary to prepare comparison circuits for the number of samples to be left.
There is a disadvantage that the circuit scale becomes very large. Further, post-processing for removing samples due to inter-symbol interference is required, and there is a problem that even after the post-processing, samples other than valid paths may remain.

An object of the present invention is to provide a path selection method and a path selection circuit of a CDM demodulation circuit which can use a large number of fingers with a small circuit scale and can improve the sample selection accuracy.

[0008]

In order to achieve the above object, a path selection method of a CDM demodulation circuit according to the present invention detects a correlation peak by despreading a received signal using a spreading code of a pilot channel. A combination ratio for each finger is obtained for all or some of the samples having the maximum peak detection value, and a selection path for each finger is determined based on the combination ratio.

More specifically, a matched filter for detecting a correlation peak by despreading a signal with a spreading code of a pilot channel, and a maximum detecting means for detecting a sample having a maximum detected peak value from an output of the matched filter. And a combination ratio calculation unit for calculating a combination ratio for each finger for all or a part of the maximum detection sample obtained by the maximum detection unit, and based on the combination ratio obtained by the combination ratio calculation unit. It is configured to determine a finger selection path.

In the path selection method and the path selection circuit having the above-described configuration, the maximum sample is detected from the correlation peak detection output from the matched filter, and the higher-order sample having the number of fingers or more is selected therefrom. However, even if the value is large, the data that is eventually unnecessary can be removed in advance, and the number of samples that need to be saved is only the number of passes required for calculating the synthesis ratio, which greatly reduces the circuit scale. It is possible to reduce the size.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 1 shows an example of a CDM transmission format to which the present invention can be applied.

FIG. 1A shows an example of a transmission frame format of digital satellite broadcasting for mobile terminals. In this format, a pilot channel for measuring a delay profile and selecting a path and transmitting data are used. Are modulated by a spreading code, multiplexed, and transmitted. The data in the CW period of the pilot channel is all 1, which is modulated only by the spreading code, and a delay profile can be obtained by the correlation output of the matched filter using the spreading code. For example, as each parameter, a chip rate of 16.384 MH
In the case of z, a spreading factor of 64, a symbol rate of 256 ksps, and a number of symbols of 32, the CW period is 125 μsec, but if there is a despread output for such a period, one CW period
Only the matched filter output in the period can sufficiently estimate the transmission path.

FIG. 1B shows an example of a transmission frame format of a pilot channel used in a downlink channel in a CDMA digital cellular radio system. In this format, pilot symbols are repeated in radio frame units. It is to be transmitted. For example, the radio frame period is 625 μs
If there is a despread output in this period, the transmission path estimation can be sufficiently performed only by the matched filter output in one radio frame period. Also, in this format,
Since the pilot symbols are transmitted continuously, it is possible to collectively obtain a despread output for each of a plurality of frames.

FIG. 2 is a block diagram showing a configuration of a path selection circuit of a CDM demodulator employing the path selection method of the present invention. Here, a description will be given assuming that RAKE combining of six fingers is performed, and that data of 16 paths is used for calculating the S / I ratio.

In FIG. 2, a signal received by an antenna 11 is supplied to a tuner 12. This tuner 12
Extracts the CDM signal in the transmission band from the received signal, converts the frequency to the baseband, and outputs the complex digital signal I,
Get Q. The I and Q signals are used to remove noise components outside the transmission band, such as overshoot and ringing, by a roll-off filter 13, and the output is a matched filter 14.
And supplied to the RAKE combining unit 18.

The matched filter 14 detects the correlation peak by despreading the baseband digital CDM signals I and Q with the spreading code of the pilot channel, and the correlation peak detection signal is supplied to the local maximum detection circuit 15.
The maximum detection circuit 15 converts the correlation peak detection signal into data that can compare the magnitudes of the delayed waves by a voltage approximation value calculation circuit that obtains, for example, a combined output of I and Q, and then outputs the maximum detection pulse when the data is maximum. The maximum detection pulse is supplied to the vest 16 detection circuit 16.

Each time the maximum detection pulse is output from the maximum detection circuit 15, the best 16 detection circuit 16 sequentially compares the data originally included only in the detection timing, and finally determines the upper 16 data. , And the upper 16 data obtained here are supplied to the combination ratio calculator 17. The combining ratio calculation unit 17 recognizes the upper 16 data as path data, and calculates a delay amount, a phase correction amount, and a combining ratio for each finger based on these data. The information provided is R
It is supplied to the AKE synthesizing unit 18.

The RAKE synthesizing section 18 generates a 6-finger RA based on the information given from the synthesizing ratio calculating section 17.
KE synthesis is performed. Here, assuming that the received power value of the i-th path is Ri based on the power values of the 16 paths,
The S / I ratio SIRi of the i-th path is

[0020]

(Equation 1)

(Where n = 16). This S
RAKE for 6 paths starting from the one with the largest / I ratio
In the case of maximal ratio combining, (SI
Ri) ^1/2Weight (synthesis ratio)
Is performed by

In the above configuration, the details of the local maximum detection circuit 15 and the vest 16 detection circuit 16 which characterize the present invention will be described below.

FIG. 3 shows a specific configuration of the maximum detection circuit 15. The I and Q inputs from the matched filter 14 are output after being delayed by one sample by a one-sample delay element 151. IQ synthesis circuit 152
Synthesized by The IQ synthesized signal S1 is delayed by one sample by the one-sample delay element 153 (S2), supplied to one input terminal A of the comparator 154, and
The signal is directly supplied to the other input terminal B of the comparator 154.

The comparator 154 has an A <B judgment output and an A> B judgment output, and the A <B judgment output S3 is supplied to one input terminal J of the JK flip-flop 155.
> B determination output S4 is supplied to the other input terminal K of JK flip-flop 155. A> B determination output is AN
It is also supplied to one input terminal A of the D gate 156. The other input terminal B of the AND gate 156 is supplied with the Q output S5 of the JK flip-flop 155,
The ND operation output S6 is supplied to the subsequent best 16 detection circuit 16 together with the one-sample delay output of the I and Q inputs.

The operation of the maximum detection circuit 15 having the above configuration will be described with reference to a timing chart shown in FIG.

First, I and Q from the matched filter 14
As a result of combining the inputs by the IQ combining circuit 152, FIG.
Is obtained, the output S2 of the one-sample delay element 153 becomes as shown in FIG. In this case, the output S3 of A <B of the comparator 154 is as shown in FIG.
As shown in FIG. 4 (c), when S1> S2, the output becomes "H", and the A> B output S4 of the comparator becomes S as shown in FIG.
It becomes "H" when 1 <S2. This comparator 154
Are supplied to the input terminals J and K of the JK flip-flop 155, respectively.

In the JK flip-flop 155, the J input is activated when the input value is in the increasing state, the Q output S5 is set at the rising edge of the sample clock CK, and the K input is activated when the input value is in the decreasing state. , The Q output S5 is reset at the rise of the sample clock CK. As a result, the JK flip-flop 15
5 shows a Q output S5 as shown in FIG.
The logical product of the output S5 and the output S4 of the comparator 154 is A
By calculating with the ND gate 156, FIG.
As shown in FIG. 7, when the input value is maximum, the maximum pulse output S6 of "H" can be obtained.

The one-sample delay element 151 is for aligning the timing of the input I and Q signals with the maximum detection pulse S6.

FIG. 5 is a block diagram showing a specific configuration of the basic unit 16A used in the vest 16 detecting circuit 16. As shown in FIG. As the input signal to the basic unit 16A, the output P of the one-sample delay element 151 in FIG. 3 is used in order to compare the magnitude of samples. In the present embodiment, R
Since 16-pass data is used to calculate the S / I ratio for obtaining the AKE combining ratio, the best 16 is left. The basic unit 16A shown in FIG. 5 is for holding one piece of data, and in order to hold the best 16 data, it is necessary to use 16 of these units 16A and connect them in multiple stages. Upper unit SELU
t and Dout are connected to SELin and Din of the next unit. In addition, SELin of the highest order unit is at “L” level, and D
in is fixed to the value “0”.

In the basic unit 16A, the register 1
Data 0 is set in 61 as an initial value. The data held in this register 161 is supplied to one input terminal A of the comparator 162 and the first selector 16
3 and then to the lower unit. On the other hand, the other input terminal B of the comparator 162 and the first selector 163 are supplied with input data to the unit. The comparator 162 compares the register holding data supplied to the input terminals A and B with the input data, and determines that A <B
At this time, the output is set to “H”. The output of the comparator 162 is supplied as a switching control signal to the first selector 163 and to the OR gate 165.

The first selector 163 selectively derives register holding data and input data in response to a switching control signal from the comparator 162, and its output data is output together with output data from the upper stage to the second selector 163. 16
4 is supplied. The second selector 164 receives the output data from the upper stage and the first data in response to the switching control signal from the upper stage.
The output data of the selector 163 is selectively derived, and the output data is supplied to the register 161 and held. The OR gate 165 performs a logical OR operation on the switching control signal output from the comparator 162 and the switching control signal from the upper stage, and the output is sent to the lower unit.

That is, the 16 basic units 16
A executes path selection in slot units, but sets all initial data of the register 161 to 0 before processing for one slot. In operation, the data stored in each register 161 and newly input data are compared by the comparator 162, and when the input value is large, the output of the comparator 162 becomes "H". The first selector 163 is switched using the comparison result as a switching control signal. As a result, the input data is stored in the register 16.
When the data is larger than the held data, the first selector 163
Input data is output to the output of.

The output of the comparator 162 is ORed with the switching control signal from the upper unit by the OR gate 165 and output to the lower unit as a switching control signal. The switching control signal from the upper unit is supplied to the second selector 164, and when this switching control signal is "H", the register holding data of the upper unit is output. The output data of the second selector 164 is returned to the input of the register 161, and the data held in the register 161 is rewritten.

In the above configuration, the relationship between the input data, the original data held in the register 161 and the data written in the register 161 is as shown in FIG. Eventually,
Of the input data, 16 data from the maximum are left in the order of the data size. Although not shown, I output data, Q output data, and timing data are also left along with the P output data.

FIG. 7 is an example of a delay profile oversampled at four times the chip rate. In FIG. 7, the horizontal axis is the sample number, and the vertical axis is the matched filter output (I ² + Q ² ), which indicates the power value. FIG.
In this example, the maximum 16 points are detected 23 times.

The effect of the above embodiment will be described in comparison with the case of the conventional system.

FIG. 8 shows the configuration of a conventional path selection circuit having no local maximum detection circuit. In FIG. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals.
In this case, since no maximum detection circuit is provided, the best 1
Instead of 6, a vest 66 detection circuit 21 for detecting the vest 66 is required, and a vest 16 extraction circuit 22 is required as post-processing for extracting the vest 16 from the vest 66.

In FIG. 7, the dotted line is written so as to include the vest 16, but the vest 16 is included in data above the dotted line. In order to obtain an equivalent processing result by the conventional method without the maximum detection circuit, it is necessary to keep all data above the dotted line. In the example shown in FIG. 7, the number of data is 66, so it is necessary to keep the best 66 data.

In the conventional method, since only the magnitude relation of data is compared, it is necessary to compare all input data with the held register value.

Further, in the conventional system, post-processing for extracting the vest 16 described below is required.

The best one is selected from the remaining 66 data, and three samples before and after the sample are deleted as data due to intersymbol interference by the same path as this sample. Attention is paid to the next largest data in the remaining data, and three samples before and after that are deleted. This operation is repeated to extract 16 data.

When the above post-processing is performed, there is a sample larger than the other peaks at the fourth sample from the largest peak, but this remains as path data under the above processing conditions after the post-processing. There's a problem. In order to prevent this, it is conceivable to employ a method in which the number of samples to be deleted is, for example, four before and after the sample. However, in this case, there is a problem that a nearby effective path may be deleted.

On the other hand, in the method according to the present invention, since each local maximum value is detected by the local maximum detecting circuit 15, the best 16 can be detected thereafter, and complicated processing as in the conventional system is unnecessary. Become. Moreover, even when a sample larger than the other peaks is present, it does not remain as path data, and the accuracy of path selection is improved.

Therefore, in the path selection circuit having the above configuration, since the maximum detection circuit 15 is provided, data can be directly left in as many registers as necessary for the calculation of the S / I ratio. There is an advantage that the circuit can be significantly simplified. Also, since only data necessary for calculating the S / I ratio can be extracted, there is an advantage that no special post-processing is required. Further, since the magnitude comparison only needs to be performed when the input has the maximum value, the circuit is simplified as compared with the conventional method, and the amount of S / I calculation is greatly reduced, so that the power consumption is significantly reduced. There is an effect that it can be achieved.

In the above embodiment, the vest 16 is detected by the vest 16 detecting circuit 16, but the present invention is not limited to this, and the present invention is similarly applicable to other vests. It is possible.

[0046]

As described above, according to the present invention, a path selection method and a path selection circuit of a CDM demodulation circuit capable of using a large number of fingers with a small circuit scale and improving sample selection accuracy are provided. can do.

[Brief description of the drawings]

FIG. 1 is a diagram showing a CDM transmission format according to the present invention.

FIG. 2 is a CDM adopting a path selection method according to the present invention.
FIG. 2 is a block diagram showing a configuration of an embodiment of a path selection circuit of the demodulation device.

FIG. 3 is an exemplary block diagram showing a specific configuration example of a local maximum detection circuit according to the embodiment;

FIG. 4 is a timing chart illustrating the operation of the local maximum detection circuit shown in FIG. 3;

FIG. 5 is a block diagram showing a specific configuration example of a basic unit used in the vest 16 detection circuit of the embodiment.

FIG. 6 is a diagram showing a relationship between input data of a vest 16 detection circuit shown in FIG. 5, original data held in a register, and data written in the register.

FIG. 7 is a characteristic diagram showing an example of a delay profile oversampled at four times the chip rate for explaining the processing operation of the embodiment.

FIG. 8 is a block diagram showing a configuration of a path selection circuit of a CDM demodulation device using a conventional path selection method.

[Description of Signs] 11 Antenna 12 Tuner 13 Roll-off filter 14 Matched filter 15 Maximum detection circuit 151 Single sample delay element 152 IQ synthesis circuit 153 Single sample delay element 154 Comparator 155 JK flip-flop 156 AND gate 16 Best 16 detection circuit 16A Basic unit 161 Register 162 Comparator 163 First selector 164 Second selector 165 OR gate 17 Synthesis ratio calculation unit 18 RAKE synthesis unit 21 Best 66 detection circuit 22 ... Best 16 extractor

Claims (4)

[Claims] 1. A CDM demodulator for use in a CDM (Code Division Multiple) demodulation circuit which selects the same CDM signal from a received signal received through a plurality of paths by a plurality of fingers and RAKE-combines the same. In the path selection method of the circuit, the received signal is despread by a spreading code of a pilot channel to detect a correlation peak, a sample whose peak detection value is maximized is selected, and a synthesis ratio of the selected sample to each finger is determined. C and determining a finger selection path based on the synthesis ratio.
Path selection method for DM demodulation circuit. 2. The path selection method for a CDM demodulation circuit according to claim 1, wherein the samples for which the combination ratio is obtained are a part of the samples having the maximum value. 3. A CDM (Code Division Multiple) demodulation circuit for selecting the same CDM signal from received signals received through a plurality of paths by a plurality of fingers and performing RAKE combining. In a path selection circuit of the circuit, a matched filter for despreading the received signal with a spreading code of a pilot channel to detect a correlation peak, and a maximum detection for detecting a sample whose peak detection value is a maximum from an output of the matched filter. Means, and a composition ratio calculating means for calculating a composition ratio of the maximum detection sample obtained by the maximum detection means with respect to the finger, wherein the plurality of fingers are provided based on the composition ratio obtained by the composition ratio calculating means. A path selection circuit for a CDM demodulation circuit, wherein the path selection circuit determines a selected path. 4. The path selection circuit of a CDM demodulation circuit according to claim 3, wherein said synthesis ratio calculation means obtains a synthesis ratio for said finger only for a part of said maximum detection samples.