JP2001235524A - Semiconductor integrated circuit device and its test method, ram/rom test circuit and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a load on the user side is heavy, because a complicated user test pattern capable of confirming passage through all signal wires connected to a RAM/ROM core is required to be inputted firm connection to the RAM/ROM core in an ACIC-LSI. SOLUTION: A user logic circuit 1 is connected to a logic circuit 50b by a selector circuit 3 when scan test is executed, and the logic circuit 50b is connected to a user logic circuit 6 by a selector 50a, to thereby compose a scan test path detouring around the RAM/ROM core, and to test the scan test path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a test method therefor, and a RAM or ROM (hereinafter referred to as R
The present invention relates to a RAM / ROM test circuit for testing AM / ROM) and a test method thereof.
SIC (Application Specific IC) -L
The scan path and the RAM / ROM cut-out test path provided around the RAM / ROM core and the user logic built in the SI allow the user logic and the RAM / ROM
The present invention relates to a test circuit and a test method thereof capable of confirming connection with a ROM core.

[0002]

2. Description of the Related Art In an ASIC-LSI, a test mode for testing the inside of an LSI includes a test mode mainly for an LSI maker and a test mode mainly for a user. LSI manufacturers manufacture LSIs,
Providing LSI development tools
It is the side that develops the LSI by performing logic design based on the tools supplied by the I maker.

In these two test modes, a test mode mainly handled by an LSI maker replaces a flip-flop existing in the LSI with a scan flip-flop to form a scan path, and outputs a scan path from an external pin scan-in signal SI. , A scan test that performs a scan path test through a scan path inside the LSI to a scan-out signal SO of an external pin, and a special block cutout test that tests a special block supplied from an LSI maker such as a RAM / ROM. included. The test mode that the user is mainly responsible for is the user logic that tests the user logic path from the input from the external pin, through the user logic, to the output to the external pin according to the user test pattern, as in normal operation. Test included.

By the way, a special block cutout test mainly performed by an LSI maker is performed in a special block included in an ASIC-LSI (in the following description, a special block is referred to as a RAM).
/ ROM) is individually cut out and an external test pin is directly tested from an external test pin, and a test pattern generator and a test analyzer are incorporated in a RAM / ROM cut out test circuit and connected to an external test pin. B that can perform self-test of RAM / ROM inside LSI
old-In Self Test (hereinafter BIST)
However, the RAM / ROM cutout test of the present case will be described as a test using BIST.

[0005] Incidentally, the three test modes described above,
That is, in the scan test mainly performed by the LSI maker, the RAM / ROM cutout test, and the user logic test mainly performed by the user, the scan test is performed between flip-flops in the user logic in which the user can freely configure the logic. This is to check the connection. As is well known, a scan path in which the scan test is performed is configured by using flip-flops (memory elements) included in a logic circuit as a serial shift register, thereby using a shift operation during the test. The test is facilitated by enabling access to the flip-flop from outside the logic circuit and by enabling the sequential circuits constituting the logic circuit to be treated as a combinational circuit.

[0006] The RAM / ROM cut-out test is R
The operation check is performed by cutting out only the AM / ROM, and the user logic test is to check the connection of all the wirings used in the normal operation. Hereinafter, a conventional RAM / ROM test circuit which facilitates these tests will be described.

FIG. 4 is a block diagram of a conventional RAM / ROM test circuit. In FIG. 1, reference numeral 1 denotes a user logic circuit having a logic block 10 designed by a user, and output signal lines of flip-flops 10a, 10b, 10c receiving the output thereof being connected to a RAM / ROM 5. RAM /
A RAM / ROM extraction test circuit connected to the ROM 5 is a selector circuit for switching between a signal line supplied from the user logic circuit 1 and a test signal line supplied from the RAM / ROM extraction test circuit 2 by a test mode control signal. And the selectors 30a, 30b, 30c corresponding to the flip-flops 10a, 10b, 10c of the user logic circuit 1. 4 stores data based on the information of the signal supplied from the selector circuit 3,
RAM / ROM core to hold, 5 is the RAM / ROM
RAM / RO having a core 4 and the selector circuit 3 and usually supplied as a special block from an LSI maker
M and 6 are user logic circuits which are supplied with signals supplied from the RAM / ROM 5 to the flip-flop 60a and are connected to a logic block 60 designed by the user. 100 is a user logic circuit 1,
This is an ASIC-LSI having a RAM / ROM 5 and a user logic circuit 6, and the RAM / ROM cut-out test circuit 2 is provided outside the ASIC-LSI 100.

The conventional RAM / R configured as described above
In the OM test circuit, the normal operation and each test mode ((a) user logic test, (b) scan test, (c) RAM / ROM cutout test)
This will be described with reference to FIGS. 5, 6, 7, and 8. FIGS. 5, 6, 7 and 8 show the signal flow in the normal operation and each test mode based on the basic configuration of the conventional RAM / ROM test circuit of FIG.

First, the operation during normal operation will be described with reference to FIG. The user logic circuit 1 is a block that is logic-designed so that a user can realize a desired function. During normal operation, the signal is ASIC
Input from the external pin DI of the LSI 100, pass through the logic block 10, and output the last flip-flop 10
a, 10b, and 10c are output to the selector circuit 3 of the RAM / ROM 5. The selectors 30 a, 30 b, and 30 c constituting the selector circuit 3 select a signal supplied from the user logic circuit 1 based on a test mode control signal input by a user or the like and output the signal to the RAM / ROM core 4. The RAM / ROM core 4 performs each processing of storing and holding by the signal supplied from the selector circuit 3,
/ ROM signal is output. The user logic circuit 6
Like the user logic circuit 1, the block is a block designed by the user, and the RAM / ROM signal supplied from the RAM / ROM core 4 is fetched into the user logic circuit 6 by the first-stage flip-flop 60a. Are output from the external pin DO through the logic block 60.

Next, the operation in the (a) user logic test will be described with reference to FIG. However, since each circuit performs the same processing as that in the normal operation, the description is omitted. In a user logic test, the selectors 30a and 30 constituting the selector circuit 3 are controlled by a test mode control signal.
b, 30c are set so as to select the signal of the user logic circuit 1. As a result, the user test pattern signal is input from the external pin DI and the logic block 10
Performs a predetermined process, selects an output signal of the logic block 10 by the selectors 30a, 30b, 30c, inputs the selected signal to the RAM / ROM core 4, supplies the output signal to the logic block 60, and And outputs a user test result pattern signal from the external pin DO.

Then, a normal operation is performed by comparing a test expected value pattern signal derived in advance from a user test pattern signal input from an external pin DI with a user test result pattern signal actually output from the user logic circuit 6. Can be used to check the connection of all the wires used.

Next, the operation in the (b) scan test will be described with reference to FIG. User logic circuit 1
Is a block designed by the user, and a flip-flop existing inside the user logic circuit 1 in the scan test is replaced with a scan flip-flop. First, test data is input as a scan-in signal SI1 from an external pin DI to a scan path in the user logic circuit 1 and passed through the scan path to be temporarily supplied to a user from flip-flops 10a, 10b, and 10c as final-stage scan flip-flops. It is output serially outside the logic circuit 1. That is, the scan path supplied from the user logic circuit 1 is R
Since the signal cannot pass through the AM / ROM core, the selector circuit 3 outputs a test result as a scan-out signal SO1 to the outside of the user logic circuit 1 without inputting the signal to the RAM / ROM core 4.

Since the user logic circuit 6 cannot receive the signal provided from the RAM / ROM core 4 in the scan test, the scan-out signal SO1 from the user logic circuit 1 is used as the scan-in signal SI2 in the ASIC. -RA within the LSI 100
The data is input via a scan path not connected to the M / ROM core 4. This test data is taken into the user logic circuit 6 by a flip-flop 60a as a scan flip-flop in the first stage of the user logic circuit 6, passes through a scan path inside the logic block 60 thereafter, and outputs a test result as a scan-out signal SO2. I do. Therefore, by verifying the test results, the user logic circuit 1
And connection between the flip-flops in the user logic circuit 6 can be confirmed.

Finally, referring to FIG. 8, (c) RAM / R
The operation in the OM cutout test will be described. RAM
/ ROM cutout test circuit 2 is ASIC-LSI 1
00, which has a dedicated input / output pin connected to the RAM / ROM 5 and outputs a test signal. The selector circuit 3 controls the RAM / RO by the test mode control signal.
Select the signal supplied from the M-cutout test circuit 2,
Output to RAM / ROM core 4. The RAM / ROM core 4 performs each process according to the signal supplied from the selector circuit 3 and outputs a RAM / ROM test signal to the RAM / ROM cut-out test circuit 2.

As described above, the operation of the RAM / ROM 5 can be confirmed by comparing the test signal input to the RAM / ROM core 4 with the RAM / ROM test signal actually output by the RAM / ROM core 4.

[0016]

SUMMARY OF THE INVENTION Conventional RAM / ROM
The test circuit is configured as described above, and has, in addition to the normal operation, test modes of (a) a user logic test, (b) a scan test, and (c) a RAM / ROM cutout test. The above test makes it easy to find manufacturing defects of LSI manufacturers and design errors by users.

However, the scan test and R
In the AM / ROM cutout test, a scan path could not be formed inside the RAM / ROM core, and the connection between the user logic circuit and the RAM / ROM core could not be confirmed. Therefore, the connection was confirmed by the user logic test. Had to do. Therefore, there is a problem that the burden on the user at the time of the test is large, such as a need to create a complicated user test pattern that allows the user to confirm that the signal passes through all the signal lines connected to the RAM / ROM core. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. A scan path and an RA provided around a RAM / ROM core and user logic are provided.
Provided are a semiconductor integrated circuit device, a test method thereof, a RAM / ROM test circuit, and a test method thereof, which enable connection confirmation between a user logic and a RAM / ROM core by using an M / ROM cut-out test path and can reduce a user's test load. The purpose is to do.

[0019]

According to a first aspect of the present invention, there is provided a first logic unit for inputting an input signal to the present semiconductor integrated circuit device, wherein the first logic unit receives an input signal. A memory unit that receives an output signal of the logic unit as an input, a second logic unit that receives an output signal of the memory unit as an input, and outputs the output signal of the semiconductor integrated circuit device, and a memory unit that is provided in the memory unit. A third logic unit having an input and an output having the same number of bits as the input signal and the output signal of the memory unit main body, and a test signal provided in the memory unit, wherein the test signal is replaced with the output of the first logic unit. A first switching unit that enables input to the memory unit main body and enables input of the output of the first logic unit to the third logic unit instead of the memory unit main unit, and is provided in the memory unit;
A semiconductor integrated circuit device comprising: a second switching unit that enables an output of the third logic unit to be input to the second logic unit instead of an output of the memory unit main body. As a result, a signal path bypassing the memory unit main body can be formed inside the memory unit, and a semiconductor integrated circuit device capable of performing a test without creating a complicated test pattern passing through the memory unit is realized.

The invention according to claim 2 of the present invention provides:
2. The method for testing a semiconductor integrated circuit device according to claim 1, wherein said first switching unit inputs an output signal of said first logic unit to said third logic unit,
The first and second switching units may be configured to input the output signal of the third logic unit to the second logic unit.
A test method for a semiconductor integrated circuit device, wherein a second switching means is set and a scan path formed by the first to third logic units is tested. As a result, a signal path bypassing the memory unit main body can be formed inside the memory unit, and a test method for a semiconductor integrated circuit device that enables a test without creating a complicated test pattern passing through the memory unit is realized.

The invention according to claim 3 of the present invention provides:
2. The method for testing a semiconductor integrated circuit device according to claim 1, wherein said first switching means inputs said test signal to said memory unit main body, and said second switching means outputs said test signal to said memory unit main body. The first and second switching units are set so that an output signal is input to the second logic unit, and a response of the memory unit body to the test signal is output as an output of the second switching unit. A test method for a semiconductor integrated circuit device, characterized in that the memory unit is tested by taking out the memory unit. As a result, a test method for a semiconductor integrated circuit device that can cut out and test a memory section in which a signal path bypassing the memory section main body can be formed inside the memory section is realized.

The invention according to claim 4 of the present invention provides:
A first selector that switches between the first signal and the second signal by a test mode control signal, and outputs a signal selected by the switching as a third signal; and a third selector that is supplied from the first selector. And a RAM / ROM core that stores and holds data based on information obtained from the signal of the first selector and outputs the fourth signal as a fourth signal, and stores the third signal supplied from the first selector in the RAM / ROM core. Is converted into a signal having the same number of bits as the fourth signal output from
A logic circuit that outputs a fifth signal, and the RAM
A RAM / ROM test, comprising: a second selector for switching and outputting a fourth signal supplied from a / ROM core and a fifth signal supplied from the logic circuit by a test mode control signal. Circuit. As a result, a scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. A RAM / ROM test circuit capable of checking the connection between the user logic circuit and the RAM / ROM core without increasing the burden on the user is realized.

[0023] The invention described in claim 5 of the present invention provides:
5. The RAM / ROM test circuit according to claim 4, wherein said first signal is supplied from a first user logic circuit. As a result, a scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. A RAM / ROM test circuit capable of checking the connection between the user logic circuit and the RAM / ROM core without increasing the burden on the user is realized.

Further, the invention according to claim 6 of the present invention provides:
5. The RAM / ROM test circuit according to claim 4, wherein said second signal is supplied from a RAM / ROM cut-out test circuit. Accordingly, a scan test using a scan path and a RAM / ROM can be performed without requiring a user logic test for inputting a complicated user test pattern.
RAM / ROM using cut-out path through core
The cutout test can be performed, and the user logic circuit and the RAM / RAM can be used without increasing the burden on the user side.
RAM / ROM that can check connection with ROM core
A test circuit is realized.

The invention according to claim 7 of the present invention provides:
5. The RAM / ROM test circuit according to claim 4, wherein said first selector outputs said first signal supplied from a first user logic circuit to said RAM / ROM during a normal operation.
The first signal supplied from the first user logic circuit is connected to the logic circuit at the time of a scan test when connected to the ROM core, and the first signal supplied from the RAM / ROM cut test circuit at the time of the RAM / ROM cut test. A RAM / ROM test circuit for connecting the second signal to the RAM / ROM core. As a result, a scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. A RAM / ROM test circuit capable of checking the connection between the user logic circuit and the RAM / ROM core without increasing the burden on the user is realized.

According to an eighth aspect of the present invention, in the RAM / ROM test circuit according to the fourth aspect, the logic circuit is configured to control the fifth signal to reflect a change in the third signal. Generating a RAM /
This is a ROM test circuit. As a result, a scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. R that can check the connection between the user logic circuit and the RAM / ROM core without increasing the burden on the user side
An AM / ROM test circuit is realized.

According to a ninth aspect of the present invention, in the RAM / ROM test circuit according to the fourth aspect, the second selector is supplied from the RAM / ROM core during normal operation. 4 is connected to a second user logic circuit, and at the time of a scan test, the fifth signal supplied from the logic circuit is connected to the second user logic circuit, and at the time of a RAM / ROM cutout test, A RAM / ROM test circuit, wherein the fourth signal supplied from the RAM / ROM core is connected to a RAM / ROM cut-out test circuit. As a result, a scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. A RAM / ROM test circuit capable of confirming the connection between the user logic circuit and the RAM / ROM core without increasing the burden on the user is realized.

Further, the invention according to claim 10 of the present invention provides:
5. The method for testing a RAM / ROM test circuit according to claim 4, wherein in a scan test mode, a test signal is input to a first user logic circuit, and the first selector, the logic circuit, and the second Selector, second
Output through a user logic circuit of the RAM
/ Configure a scan test path that bypasses the ROM core,
This is a test method for a RAM / ROM test circuit, which tests the scan test path. Thus, the RAM can enable connection confirmation between the user logic circuit and the RAM / ROM core by a scan test using a scan path without requiring a user logic test for inputting a complicated user test pattern.
The test method of the / ROM test circuit is realized.

[0029] The invention according to claim 11 of the present invention provides:
5. A method for testing a RAM / ROM test circuit according to claim 4, wherein said RAM / ROM test circuit performs a RAM / ROM cutout test.
From the AM / ROM extraction test circuit, the signal passes through the first selector, the RAM / ROM core, and the second selector, and returns to the RAM / ROM extraction test circuit.
A test method for a RAM / ROM test circuit, comprising forming a cut-out test path passing through the RAM / ROM core and testing the cut-out test path. As a result, a RAM / ROM core that enables connection confirmation between a user logic circuit and a RAM / ROM core by a scan test using a scan path without requiring a user logic test for inputting a complicated user test pattern is required. A test method for a RAM / ROM test circuit capable of confirming the connection of the RAM / ROM core is realized by the cut-out path that passes through the RAM / ROM core corresponding to the scan path, which is cut out alone.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG.
RAM / ROM as a basic configuration of the first embodiment of the present invention
It is a block diagram of a test circuit. The first embodiment corresponds to the first to eleventh aspects of the present invention.

Referring to FIG. 1, reference numeral 1 denotes a user logic circuit (first logic circuit) having a logic block 10 designed by a user, the output signal lines of flip-flops 10a, 10b and 10c receiving the output thereof being connected to a RAM / ROM 50. , A RAM / ROM connected to the RAM / ROM 50 through a dedicated input / output test signal line
The cutout test circuit 3 and the test mode control signal send the signal line (first signal) supplied from the user logic circuit 1 and the test signal line (test signal, second signal) supplied from the RAM / ROM cutout test circuit 2. Signal)
And the test mode control signal causes R
A selector circuit (first switching means) for switching between a signal line (third signal) output to the AM / ROM core 4 and a signal line (third signal) output to the logic circuit 50b;
Flip-flop 10a, 1 of user logic circuit 1
It comprises selectors 3a, 3b, 3c corresponding to 0b, 10c.

A RAM / R 4 stores and holds data based on information of a signal supplied from the selector circuit 3.
The OM core (memory unit main body) and 50b are connected to the signal line bypassing the RAM / ROM core 4 by the RAM / ROM core 4
A logic circuit (third logic unit) for performing adjustment according to the difference in the number of bits between the input signal and the output signal of the input / output signal, and a signal line (fourth signal) supplied from the RAM / ROM core 4 by the test mode control signal ) And a logic circuit 50b for switching between a signal line (fifth signal) bypassing the RAM / ROM core 4 (second switching means), 50
Is a RAM / ROM (memory section) as a special block having the selector circuit 3, the RAM / ROM core 4, the logic circuit 50b, and the selector 50a. The signal 6 supplied from the RAM / ROM 50 is supplied to the flip-flop 60a. A user logic circuit (second logic unit) that is input and connected to the logic block 60 designed by the user. Reference numeral 101 denotes an ASIC-LSI having a user logic circuit 1, a RAM / ROM 50, and a user logic circuit 6;
The M cutout test circuit 2 uses the ASIC-LSI 101
Is provided outside.

The RAM of the present invention constructed as described above
In the ROM test circuit, two test modes ((x) scan test, (y) R, in which the wiring connection between the user logic circuit and the RAM / ROM can be newly confirmed.
2 and 3 for the AM / ROM cutout test)
This will be described with reference to FIG.

FIG. 2 shows a scan test using a scan path based on the basic configuration of the RAM / ROM test circuit of FIG. 1. FIG. 2A shows the scan path. FIG. 3 shows a cut-out test path in a RAM / ROM cut-out test based on the basic configuration of the RAM / ROM test circuit in FIG. 1, and FIG. 3B shows a cut-out test path.

First, the operation in the (x) scan test will be described with reference to FIG. User logic circuit 1
Is a block designed by the user, and a flip-flop existing inside the user logic circuit 1 in the scan test is replaced with a scan flip-flop.

First, when test data is input to the scan path (A) as the scan-in signal SI, a predetermined process is performed through the scan path (A) inside the user logic circuit 1, and the processing is performed as a scan flip-flop at the final stage. Of the flip-flops 10a, 10b, 10c
It is output to the selector circuit 3. The selector circuit 3 selects the scan path (A) supplied from the user logic circuit 1 according to the test mode control signal. At this time, the selector circuit 3 sets the scan path (A) to the logic circuit 50.
b. As a result, the scan path (A) becomes RA
Bypass the M / ROM core 4.

The logic circuit 50b adjusts the number of bits according to the difference in the number of bits between the input signal and the output signal of the RAM / ROM core 4. That is, the scan path (A) supplied from the selector circuit 3 is a signal corresponding to, for example, an address signal, a write data signal, a write enable signal, and a read enable signal in the RAM / ROM, and the scan path (A) output from the logic circuit 50b. A) is a signal corresponding to a read data signal, and generally has a different number of bits. Therefore, the logic circuit 50b adjusts the number of bits of the input signal and the output signal. In addition, the logic circuit 5
0b reflects the change of the input signal on the output signal.

The selector 50a selects the scan path (A) supplied from the logic circuit 50b according to the test mode control signal. The user logic circuit 6, like the user logic circuit 1, is a block designed by a user. Similarly to the user logic circuit 1, in the scan test, flip-flops inside the circuit are replaced with scan flip-flops.
Therefore, the scan path (A) supplied from the selector 50a is taken into the user logic circuit 6 by the flip-flop 60a as the first-stage scan flip-flop, passes through the scan path (A) in the subsequent logic block 60, and The test result is output as the scan-out signal SO.

As described above, by comparing the test expected value derived from the test signal input from the SI with the test result output from the SO, the scan path bypassing the RAM / ROM core 4 inside the RAM / ROM 50 (A) Wiring connection confirmation, that is, the wiring connection between the RAM / ROM 50 and the user logic circuits 1 and 6 can be confirmed.

Next, referring to FIG. 3, (y) RAM / RO
The operation in the M cutout test will be described. RAM /
The ROM cutout test circuit 2 cuts out output test data via an external input terminal and outputs it to the test path (B) in order to perform a cutout test of the RAM / ROM 50.
The selector circuit 3 uses the test mode control signal to
The cut test path (B) supplied from the M / ROM cut test circuit 2 is selected and connected to the RAM / ROM core 4. The RAM / ROM core 4 performs each processing of storage and holding based on the test data obtained from the cut-out test path (B), and outputs the RAM / ROM core test result to the cut-out test path (B) via an external output terminal. Output.

The selector 50a selects the cut-out test path (B) supplied from the RAM / ROM core 4 according to the test mode control signal, and connects it to the RAM / ROM cut-out test circuit 2. The RAM / ROM cutout test circuit 2 obtains a RAM / ROM core test result through the cutout test path (B) supplied from the selector 50a.

As described above, RAM / ROM derived from the test signal output from the RAM / ROM extraction test circuit 2
A test expected value obtained in the ROM cutout test circuit 2 and a RAM actually output from the RAM / ROM core 4
By comparing the / ROM core test results,
Not only the AM / ROM core 4 but also a selector 50 newly provided in this embodiment so as to realize a scan path test.
a, the connection of the wiring of the cut-out test path (B) passing through can be checked.

As described above, the RA according to the first embodiment
According to the M / ROM test circuit and the test method thereof, the RAM / ROM can be scanned by the scan path and the extraction path passing through the RAM / ROM core by the RAM / ROM extraction test without imposing a special burden on the user side. It is possible to check the connection of all the wirings connected to.

In the first embodiment, the RAM / ROM 50 supplied from the LSI maker includes the selector circuit 3, the logic circuit 50b, and the selector 50a. However, these may be included in the user logic circuit. .

In the first embodiment, the RAM / RO
The M cutout test was explained using BIST,
It may be a test by an external cutout test.

In the first embodiment, the RAM / RO
Although the M cutout test circuit is provided outside the ASIC-LSI, it may be provided inside the ASIC-LSI.

In the first embodiment, the ASIC-L
Although the SI has been described as an example, the present invention may be applied to a semiconductor integrated circuit device having a logic circuit in a preceding stage and a subsequent stage in addition to a semiconductor memory.

In the first embodiment, the ASIC-
Although the case where the special block included in the LSI is a memory has been described as an example, the present invention may be applied to a special block that cannot form a scan path even if it is other than a memory and that has a logic circuit in the preceding and subsequent stages. .

Further, in the first embodiment, the number of the flip-flops of the user logic circuit 1 and the number of the selectors of the selector circuit 3 are both three, but any number may be provided as long as they are the same number.

[0050]

As described above, according to the semiconductor integrated circuit device according to the first aspect of the present invention, the first logic unit which receives an input signal to the semiconductor integrated circuit device, A memory unit to which an output signal of the first logic unit is input; a second logic unit to which an output signal of the memory unit is input and an output of which is an output signal of the semiconductor integrated circuit device; A third logic unit having an input and an output having the same number of bits as an input signal and an output signal of the memory unit main unit; and a test signal provided in the memory unit and replacing the output of the first logic unit. A first switching unit that enables input of the first logic unit to the third logic unit instead of the memory unit main unit, and is provided in the memory unit. And said Since so and a second switching means for enabling an output of said third logic unit to said second logic unit in place of the output of the memory unit main body,
A signal path bypassing the memory unit body can be formed inside the memory unit, and a semiconductor integrated circuit device capable of performing a connection test between the logic unit and the memory unit without creating a complicated test pattern passing through the memory unit is obtained. Has the effect.

According to a second aspect of the present invention, there is provided a method of testing a semiconductor integrated circuit device according to the first aspect of the present invention, wherein the first switching means is provided. Inputs the output signal of the first logic unit to the third logic unit, and the second switching unit outputs the output signal of the third logic unit to the second logic unit.
The first and second switching means are set so as to input to the logic section of the first section, and the scan path formed by the first to third logic sections is tested.
A test of a semiconductor integrated circuit device in which a signal path bypassing the memory unit body can be formed inside the memory unit, and a connection test between the logic unit and the memory unit can be performed without creating a complicated test pattern passing through the memory unit. There is an effect that the method can be obtained.

According to a third aspect of the present invention, there is provided a method of testing a semiconductor integrated circuit device according to the first aspect, wherein the first switching means is provided. Input the test signal to the memory unit main body, and input the output signal of the memory unit main body to the second logic unit so that the second switching unit inputs the test signal to the second logic unit. Means is set, and a response of the memory section main body to the test signal is taken out as an output of the second switching means, so that the memory section is tested. So that a connection test between the logic unit and the memory unit can be performed without creating a complicated test pattern passing through the memory unit.
This has the effect of providing a test method for a semiconductor integrated circuit device that can cut out and test only the memory section in which a signal path bypassing the memory section main body can be formed inside the memory section.

According to the RAM / ROM according to the fourth aspect of the present invention, the first signal and the second signal are switched by the test mode control signal, and the signal selected by the switching is switched to the third signal. And a third selector supplied from the first selector.
A RAM / ROM core for storing and holding data based on information obtained from the signal of
A logic circuit that converts the third signal supplied from the first selector into a signal having the same number of bits as the fourth signal output from the RAM / ROM core, and outputs the signal as a fifth signal; Since a second selector for switching and outputting the fourth signal supplied from the RAM / ROM core and the fifth signal supplied from the logic circuit by a test mode control signal is provided, a complicated user test is performed. A scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a pattern, thereby increasing the burden on the user side. That can check the connection between the user logic circuit and the RAM / ROM core without the need
/ ROM test circuit is obtained.

According to the RAM / ROM test circuit according to the invention of claim 5 of the present application, R
In the AM / ROM test circuit, the first signal is:
Since it is supplied from the first user logic circuit, a scan test using a scan path and a cutout path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. The RAM / ROM cut-out test to be used can be performed, and the RAM / ROM test circuit that can check the connection between the user logic circuit and the RAM / ROM core without increasing the burden on the user is obtained.

According to the RAM / ROM test circuit according to the invention of claim 6 of the present application, R
In the AM / ROM test circuit, the second signal is
Since it is supplied from the RAM / ROM extraction test circuit, a scan test using a scan path and an extraction path passing through the RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. The RAM / ROM cut-out test to be used can be performed, and there is an effect that a RAM / ROM test circuit that can check the connection between the user logic circuit and the RAM / ROM core without increasing the burden on the user side can be realized.

Further, according to the RAM / ROM test circuit according to the invention of claim 7 of the present application, R
In the AM / ROM test circuit, the first selector connects the first signal supplied from the first user logic circuit to the RAM / ROM core during a normal operation, and connects the first signal to the RAM / ROM core during a scan test. The first signal supplied from the user logic circuit is connected to the logic circuit, and at the time of the RAM / ROM cutout test, the RAM / R
Since the second signal supplied from the OM cutout test circuit is connected to the RAM / ROM core,
A scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core can be performed without requiring a user logic test for inputting a complicated user test pattern. This has the effect of realizing a RAM / ROM test circuit capable of confirming the connection between the user logic circuit and the RAM / ROM core without increasing the burden.

Further, according to the invention of claim 8 of the present application, R
According to the AM / ROM test circuit, the RA according to claim 4 is used.
In the M / ROM test circuit, the logic circuit includes:
Since the fifth signal is generated to reflect the change of the third signal, a scan test using a scan path can be performed without requiring a user logic test for inputting a complicated user test pattern. RAM /
RAM using cutout path through ROM core /
A ROM cutout test can be performed, and the user logic circuit and RA can be tested without increasing the burden on the user side.
RAM / RO that enables connection confirmation with M / ROM core
There is an effect that an M test circuit can be obtained.

Further, according to the ninth aspect of the present invention, R
According to the AM / ROM test circuit, the RA according to claim 4 is used.
In the M / ROM test circuit, the second selector connects the fourth signal supplied from the RAM / ROM core to a second user logic circuit during a normal operation, and connects the fourth signal to a second user logic circuit during a scan test. Is connected to the second user logic circuit, and at the time of a RAM / ROM cutout test, the fifth signal is supplied to the second user logic circuit.
/ The fourth signal supplied from the ROM core is stored in RAM /
Since it was connected to the ROM cutout test circuit,
The user can perform a scan test using a scan path and a RAM / ROM extraction test using an extraction path passing through a RAM / ROM core without requiring a user logic test for inputting a complicated user test pattern. This has the effect of realizing a RAM / ROM test circuit capable of confirming the connection between the user logic circuit and the RAM / ROM core without increasing the size.

According to the test method of the RAM / ROM test circuit according to the invention of claim 10 of the present application, there is provided a method of testing the RAM / ROM test circuit of claim 4, wherein: A RAM / R for inputting a test signal to a first user logic circuit and outputting the test signal through the first selector, the logic circuit, the second selector, and a second user logic circuit;
Since the scan test path that bypasses the OM core is configured and the scan test path is tested, the scan test using the scan path does not require a user logic test for inputting a complicated user test pattern. User logic circuit and RAM / R
This has the effect of realizing a test method for a RAM / ROM test circuit that enables connection confirmation with the OM core.

According to the method for testing a RAM / ROM test circuit according to claim 11 of the present invention, there is provided a method for testing a RAM / ROM test circuit according to claim 4, wherein the RAM / ROM cut-out test is performed. Sometimes, RAM
From the / ROM extraction test circuit, through the first selector, the RAM / ROM core, and the second selector, back to the RAM / ROM extraction test circuit, and constitute an extraction test path passing through the RAM / ROM core. Then, since the cut-out test path is tested, the user logic circuit and the RAM / ROM core can be scanned by the scan test using the scan path without requiring a user logic test for inputting a complicated user test pattern. RAM that enables connection confirmation
RAM that cuts out the ROM / ROM core independently and that allows the connection of the RAM / ROM core to be checked by the cutout path that passes through the RAM / ROM core corresponding to the scan path
There is an effect that the test method of the / ROM test circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a RAM / ROM according to a first embodiment of the present invention;
FIG. 3 is a block diagram showing a basic configuration of a test circuit.

FIG. 2 is a block diagram of a RAM / ROM test circuit in a scan test according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a RAM / ROM according to the first embodiment of the present invention;
FIG. 3 is a block diagram of a RAM / ROM test circuit in a cutout test.

FIG. 4 is a block diagram showing a basic configuration of a conventional RAM / ROM test circuit.

FIG. 5 is a block diagram of a conventional RAM / ROM test circuit during normal operation.

FIG. 6 shows a RAM in a conventional user logic test.
FIG. 3 is a block diagram of a / ROM test circuit.

FIG. 7 shows a RAM / ROM in a conventional scan test.
It is a block diagram of a test circuit.

FIG. 8 is a block diagram of a RAM / ROM test circuit in a conventional RAM / ROM cutout test.

[Explanation of symbols]

 1, 6 user logic circuit 10, 60 logic block 10a, 10b, 10c, 60a flip-flop 2 RAM / ROM cutout test circuit 3 selector circuit 3a, 3b, 3c selector 4 RAM / ROM core 50 RAM / ROM 50a selector 50b logic circuit 101 ASIC-LSI A Scan path B Cutout test path

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tomoo Nakagawa 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. 2G032 AA01 AA07 AA08 AE07 5L106 DD08 DD11 9A001 BB05 HH35 JJ49 JJ50 KK54 LL05

Claims (11)

[Claims] A first logic unit for inputting an input signal to the semiconductor integrated circuit device; a memory unit for receiving an output signal of the first logic unit; and an input signal for an output signal of the memory unit A second logic unit whose output is an output signal of the semiconductor integrated circuit device; and a third logic unit provided in the memory unit and having an input and an output having the same number of bits as an input signal and an output signal of the memory unit main body. A logic unit provided in the memory unit, a test signal can be input to the memory unit main body instead of the output of the first logic unit, and the output of the first logic unit is input to the memory unit main body. A first switching means for inputting the data to the third logic unit; and a switching unit provided in the memory unit, wherein the output of the third logic unit is replaced by the second logic instead of the output of the memory unit main body. The semiconductor integrated circuit device which is characterized in that a second switching means for enabling input to. 2. The method for testing a semiconductor integrated circuit device according to claim 1, wherein said first switching unit inputs an output signal of said first logic unit to said third logic unit, The second
The first and second switching means are set so that the switching means of (1) inputs the output signal of the third logic section to the second logic section, and is formed by the first to third logic sections. A test method for a semiconductor integrated circuit device, comprising: testing a scan path to be performed. 3. The method for testing a semiconductor integrated circuit device according to claim 1, wherein said first switching means inputs said test signal to said memory unit main body, and said second switching means outputs a test signal. Setting the first and second switching means so that an output signal of the memory unit is input to the second logic unit; and a response of the memory unit to the test signal,
By taking out as an output of the second switching means,
A test method for a semiconductor integrated circuit device, wherein a test is performed on the memory unit. 4. A first selector which switches between a first signal and a second signal by a test mode control signal, and outputs a signal selected by the switching as a third signal, and a signal supplied from the first selector. A RAM / ROM core that stores and holds data based on the information obtained from the third signal and outputs the fourth signal as a fourth signal; and a third signal supplied from the first selector. A logic circuit that converts the signal into a signal having the same bit number as the fourth signal output from the RAM / ROM core and outputs the signal as a fifth signal; a fourth signal supplied from the RAM / ROM core and the logic And a second selector for switching and outputting a fifth signal supplied from the circuit by a test mode control signal. 5. The RAM / ROM test circuit according to claim 4, wherein the first signal is supplied from a first user logic circuit. 6. The RAM / ROM test circuit according to claim 4, wherein the second signal is supplied from a RAM / ROM cut-out test circuit. 7. The RAM / ROM test circuit according to claim 4, wherein said first selector outputs said first signal supplied from a first user logic circuit to said RAM during a normal operation.
/ ROM core, and connects the first signal supplied from the first user logic circuit to the logic circuit during a scan test, and supplies the first signal from the RAM / ROM cut test circuit during a RAM / ROM cut test. A RAM / ROM test circuit for connecting the second signal to the RAM / ROM core. 8. The RAM / ROM test circuit according to claim 4, wherein said logic circuit generates said fifth signal so as to reflect a change in said third signal.
M / ROM test circuit. 9. The RAM / ROM test circuit according to claim 4, wherein said second selector is connected to said RAM / RO during normal operation.
Connecting the fourth signal supplied from the M core to a second user logic circuit, and connecting the fifth signal supplied from the logic circuit to the second user logic circuit during a scan test; A RAM / ROM test circuit for connecting a fourth signal supplied from the RAM / ROM core to a RAM / ROM cut test circuit during a RAM / ROM cut test. 10. The method for testing a RAM / ROM test circuit according to claim 4, wherein a test signal is input to a first user logic circuit in a scan test mode, and wherein the first selector and the logic circuit are used. Forming a scan test path for outputting through the second selector and the second user logic circuit and bypassing the RAM / ROM core, and testing the scan test path.
Test method of test circuit. 11. The method for testing a RAM / ROM test circuit according to claim 4, wherein at the time of a RAM / ROM cut-out test, the RAM / ROM cut-out test circuit outputs the first selector and the RA.
An M / ROM core, passing through the second selector,
Returning to the M / ROM cutout test circuit, the RAM / R
An RA characterized by forming a cut-out test path passing through the OM core and testing the cut-out test path
Test method for M / ROM test circuit.