JP2001217711A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer for improving the fluctuation of a sprious reduction effect caused by an output frequency concerning the frequency synthesizer of a fractional frequency dividing system. SOLUTION: This frequency synthesizer is provided with a fixed frequency divider for frequency-dividing the output of a crystal oscillator and outputting it to a phase comparator as a reference frequency, charge pump for charging/discharging a loop filter with a current corresponding to a phase difference outputted from the phase comparator, voltage controlled oscillator (VCO) for inputting the output of the loop filter, variable frequency divider for supplying a signal variably frequency-dividing the output of the VCO to the other input terminal of the phase comparator, frequency dividing number generating means for applying an integer frequency dividing number to the variable frequency divider and controlling it, phase error compensating means for generating a current for compensating a phase error having time width generated on the basis of a phase error compensation value outputted from the frequency dividing number generating means and the output of the VCO while connecting the output to the output of the charge pump, and clock generating means for supplying a clock to the frequency dividing number generating means by inputting the output of the VCO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly, to a fractional frequency division PLL synthesizer.

[0002]

2. Description of the Related Art Fractional frequency division PLL (Phase Locked Loo
As a method for suppressing spurious components of p: phase locked loop, reference 1 (“High frequency switching synthesizer using fractional frequency division method”, IEICE Transactions C-1 Vol. J76-CI)
No.11 PP445-452), crystal oscillator, fixed frequency divider, phase comparator, charge pump, loop filter, voltage controlled oscillator, voltage controlled oscillator, frequency comparison and phase comparison A variable frequency divider that feeds back to a device, and a circuit configuration including a fraction generation unit are known.
This configuration has no effect unless the phase comparison frequency is increased. As a workaround, for example, Japanese Patent Application Laid-Open No. 9-512268 proposes a configuration as shown in FIG.

Referring to FIG. 8, a crystal oscillator 1, a fixed frequency divider 2 for dividing the output of the crystal frequency divider 1 and outputting as a reference frequency, a voltage controlled oscillator (VCO) 6, and a voltage controlled oscillator 6 A variable frequency divider 7 for dividing the frequency by the frequency division number given by the frequency dividing means, a phase comparator 3 for detecting the phase difference between the reference frequency and the output of the variable frequency divider 7, and A charge pump (CP) 4 of a type (current type) for charging / discharging the loop filter, a loop filter 5 for smoothing the phase difference signal of the phase comparator and outputting it as a signal controlled by the voltage controlled oscillator 6, Frequency division number generating means 8 for giving an integral frequency division number to frequency divider 7 for control, and a pulse width of a signal for compensating a phase error based on a phase error compensation value outputted from frequency division number generation means 8 To compensate for the phase error A phase error compensating means 9 'and a clock generating means 10' are provided. The frequency dividing number generating means 8 includes a plurality of cascade-connected integrators and a differentiator for differentiating the carry-out signal thereof. The phase error generated in the frequency divider 7 is obtained from the output of the adder included in the final stage integrator of the frequency division number generating means 8, and a phase error compensation value is output.

[0004] More specifically, the frequency dividing number generating means 8 is provided as shown in FIG.
As shown in FIG. 3, the adder 15 to 19 and the latches (flip-flops) 20 to 23 (adder 16 and latch 2)
0, adder 17 and latch 21 each constitute an integrator, adder 18 and latch 22, adder 19 and latch 23
Each constitute a differentiator), and the output of the clock generating means 10 'is connected to the clocks of the latches 20 to 23. M that determines the numerator of the fractional frequency division is input to the adder 16, and N that determines the integer frequency division value is input to the adder 15.

The output of the adder 16 is input to an adder 17 for integration, and the carry-out signal CO of the adder 17 forming an integrator is differentiated by a differentiator comprising an adder 18 and a latch 22. And the carry-out signal CO from the adder 16 are added to N by the adder 15 and output to the variable frequency divider 7. The output of the adder 17 is input to a differentiator including an adder 19 and a latch 23 to be differentiated, and the adder 19 outputs a phase error compensation value Eθ.

As described above, the frequency dividing number generating means 8 has a differentiator for outputting a phase error compensation value in addition to the configuration of n integrators, n-1 differentiators and adders. The frequency characteristics of the phase error have a biased characteristic in the high frequency range. The PLL with low-pass characteristics makes it easy to remove spurious components, allowing a wider loop bandwidth and high-speed frequency switching. Therefore, it is not necessary to particularly increase the reference frequency of the output signal dw of the fixed frequency divider, and the spurious can be sufficiently reduced at a phase comparison frequency lower than that of the above-mentioned document 1.

As shown in FIG. 10, the phase error compensating means 9 'comprises comparators 24-27, OR circuits 28, 29,
The circuit includes AND circuits 30 and 31, current sources 32 and 33, an inverter 34, adders 35 to 38, and latches (D-type flip-flops) 39 and 40. Adders 35, 3
7, the maximum value 2 ⁿ -1 of the count value and the phase error Eθ are input and (2 ⁿ -1) -Eθ is output, and the adders 36 and 38 are output.
, The load (LOAD) value of the variable frequency divider 7 and Eθ are input, and LOAD ± Eθ is output. Comparator 2
The contents of the counter of the fixed frequency divider 2 are inputted to the A terminals 4 to 27, the outputs of the adders 35 to 38 are inputted to the B terminal, and the contents of the counters of the A terminals are inputted to the comparators 24 and 26. Outputs a High level signal when is larger than the value at the B terminal, and the comparators 25 and 27 output a High level signal when the content of the counter at the A terminal is smaller than the value at the B terminal. The OR circuit 28 includes comparators 24, 2
5 as an input, and the OR circuit 29
4 and 25 are input, the AND circuit 30 receives the output of the OR circuit 28 and the signal obtained by inverting the MSB of the phase error compensation value Eθ by the inverter 34, and the AND circuit 31 outputs
The output of the R circuit 29 and the MSB of the phase error compensation value Eθ are input, the data input terminals of the flip-flops 39 and 40 receive the outputs of the AND circuits 30 and 31, and the clock input terminal receives the output of the crystal oscillator 1. Output is input.

FIG. 11 is a diagram showing a configuration of a clock generating means 10 'for providing a clock to the frequency dividing number generating means 8.
Referring to FIG. 11, the comparator 13 compares a predetermined value 2 ⁿ −9 with a count value of an up counter included in the fixed frequency divider 2.
The flip-flop 14 outputs a High signal, inputs the output of the comparator 13 to the data input terminal, and inputs the output of the crystal oscillator 1 to the clock terminal.
Output retiming. Note that, in the conventional frequency synthesizer shown in FIG.
In the configuration of the variable frequency divider 7 shown in (1), a clock is configured as an output from the crystal oscillator 1.

FIG. 9A shows a current waveform Id due to a phase error output from the charge pump 4 when the phase error compensation value Eθ = 3, and FIG. 9B shows a phase error compensation means for compensating the current waveform. 9 shows a waveform of the phase error compensation current Ic output from the reference numeral 9.

[0010]

However, in the conventional fractional frequency dividing frequency synthesizer shown in FIG. 8, when the oscillation frequency f _out of the voltage controlled oscillator 6 changes, the phase error is completely compensated. However, there is a problem that the spurious suppression amount changes.

To compensate for the phase error, Id and Ic
Is given by the following equation (1). However, f _TCXO
Is the output frequency of the crystal oscillator 1.

Id * (1 / (f _out * 2 ^M )) = 2 * Ic * (1 / f _TCXO ) (1)

The frequency f of the output signal of the voltage controlled oscillator 6
_{When out} changes, if Id and Ic are fixed, the left side and the right side of Expression (1) cannot be kept equal. That is, when the oscillation frequency f _{ou t} is changed, not completely be compensated phase error, spurious suppression amount is changed.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a frequency synthesizer having a phase error current compensating means for reducing spurious, and a spurious reduction effect by an output frequency. It is an object of the present invention to provide a frequency synthesizer of a fractional frequency division system which improves the fluctuation of the frequency.

[0015]

According to the present invention, a fixed frequency divider for dividing the output of a crystal oscillator and outputting it as a reference frequency, a voltage controlled oscillator, and an output of the voltage controlled oscillator are provided. A variable frequency divider that divides frequency by a frequency given by a frequency dividing means, a reference frequency from the fixed frequency divider and an output from the variable frequency divider are input, and a phase difference between these signals is calculated. A phase comparator for detecting and outputting, a loop filter for smoothing a phase difference signal output from the phase comparator and outputting the signal as a signal for controlling the voltage controlled oscillator, and an integer frequency divider for the variable frequency divider. A frequency dividing number generating means for giving and controlling a number, a phase locked loop is formed by controlling the voltage controlled oscillator with the output of the loop filter, and the frequency dividing number generating means comprises a plurality of cascade-connected integrators; , Carry-out of the integrator A differentiator for differentiating the signal, an adder, an output of said differentiator is input to the adder,
The adder takes the sum of the frequency division number and the integer part, supplies the result as the frequency division number of the variable frequency divider, and differentiates the integration result of the n-th stage integrator (n-1) times to obtain a phase. In a frequency synthesizer configured to output an error compensation value, a phase error having a time width generated based on a phase error compensation value from the frequency division generating means and an output of the voltage controlled oscillator is compensated. A phase error compensating unit that generates a signal for performing the operation and supplies it to the input terminal of the loop filter; and a clock generating unit that receives an output from the voltage controlled oscillator as an input and supplies a clock to the frequency division number generating unit. .

[0016]

Embodiments of the present invention will be described. A crystal oscillator (1), a fixed frequency divider (2) for dividing the output of the crystal oscillator (1) and outputting the frequency as a reference frequency;
Phase comparator with reference frequency as one input terminal (3)
A charge pump (4) for outputting a current corresponding to the phase difference signal output from the phase comparator (3), and a loop for smoothing and outputting a terminal voltage of a capacitor charged and discharged by the output current of the charge pump A filter (5), a voltage controlled oscillator (6) for inputting an output of the loop filter (5) as a control voltage, and a variable frequency divider which divides the output of the voltage controlled oscillator (6) to other components. A variable frequency divider (7) to be supplied to the input end, frequency dividing number generating means (8) for controlling the variable frequency divider (7) by giving an integer frequency dividing number, and frequency dividing generating means (8) A current for compensating for a phase error is generated having a time width generated based on the output phase error compensation value (Eθ) and the output (f _out ) of the voltage controlled oscillator (6). Phase error compensating means (connected to the output of the charge pump (4) 9) and clock generation means (10) which _receives the output (f _out ) of the voltage controlled oscillator (6) as an input and supplies a clock to the frequency division number generation means (8).

In one embodiment of the present invention, referring to FIG. 4, the frequency dividing number generating means (8) includes a plurality of cascade-connected integrators (an integrator comprising an adder 16 and a latch 20,
An integrator including an adder 17 and a latch 21; and a differentiator (adder 18) for differentiating the carry-out signal CO of the integrator.
And a latch 22), and an adder (15). The output of the differentiator is input to the adder (15), and the adder (1) is provided.
In 5), the sum of the frequency division number and the integer part (N) is obtained and supplied as the frequency division number of the variable frequency divider (7), and the integration result of the n-th stage integrator is differentiated (n-1) times Thus, the phase error compensation value Eθ is output.

In one embodiment of the present invention, referring to FIG. 5, the phase error compensating means (9) includes a counter maximum value (2 ⁿ -1) of the variable frequency divider and a frequency ^dividing number generating means ( 8) a first and third adder (35, 37) which are input with a value obtained by multiplying the phase error compensation value Eθ by a predetermined value L, a load value LOAD of the variable frequency divider (7), Second and fourth adders (36, 38) which receive as input the value obtained by multiplying the phase error compensation value Eθ by the predetermined value L from the frequency dividing number generating means (8).
And first to fourth comparators (24 to 27) for comparing the contents of the counter of the variable frequency divider (7) with the magnitudes of the outputs of the first to fourth adders (35 to 38); First
The comparison output of the second and third comparators;
The first of which receives the comparison output of the comparator
A second AND circuit (28, 29), and a first AND circuit (30) which receives as inputs the output of the first OR circuit (28) and the inverted value of the most significant bit of the phase error compensation value ) And a second AND circuit (3) which receives the output of the second OR circuit (29) and the most significant bit of the phase error compensation value as inputs.
1) a first and second latch circuit (39, 40) for latching the outputs of the first and second AND circuits (30, 31) with the output f _out of the voltage controlled oscillator (6); A first current source (32) connected between a power supply and an output terminal and controlled to be turned on and off by an output of the first latch circuit; and a second latch connected between the output terminal and a lower power supply. A second current source (33) that is turned on / off by an output of the circuit, and outputs an output signal (current) for correcting a phase error from the output terminal.

In one embodiment of the present invention, referring to FIG. 3, the clock generating means (10) includes a comparator for comparing a value of a counter constituting the variable frequency divider (7) with a predetermined value. (13) and the comparator (1
A latch circuit (14) for latching the output of (3) with the output f _out of the voltage controlled oscillator (6).

In one embodiment of the present invention, referring to FIG. 2, the variable frequency divider (7) is set to a load value when counting up to the maximum value 2 ⁿ -1 and counts up from the load value. An n-bit counter (11)
A latch circuit (12) for latching the ripple carry of the counter with the output of the voltage controlled oscillator (6).

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, a frequency synthesizer according to the present invention includes a crystal oscillator (TCXO) 1 and a fixed frequency divider 2 which divides the output of the crystal oscillator 1 and outputs the result as a reference frequency fref.
, A phase comparator 3, a charge pump (CP) 4, a loop filter 5, and a voltage-controlled oscillator (VCO) that inputs an output voltage of the loop filter 5 as a control voltage and outputs a signal having a frequency corresponding to the control voltage. ) 6, a variable frequency divider 7 for dividing the output of the voltage controlled oscillator 6 according to the frequency division number, a frequency division number generating means 8, a phase error compensating means 9, and a clock for the frequency division number generating means 8. a clock generating means 10 which gives, with a clock generator 10, the output of the output f _{ou t} and the variable frequency divider 7 of the voltage controlled oscillator 6 is inputted.

FIG. 2 shows a variable frequency divider 7 according to an embodiment of the present invention.
FIG. 3 is a diagram showing the configuration of FIG. The up counter 11 is an n-bit counter, and is configured so that a preset value LOAD (load) is read and set as a counter value each time a ripple carry is output, and up counting is restarted from the load value. The frequency division number of the variable frequency divider 2 is 2 ⁿ -LOAD, and outputs the counter contents and ripple carry.

The flip-flop (D-type flip-flop) 12 inputs the ripple carry of the up counter 11 to the data input terminal D, and outputs the output f of the voltage controlled oscillator 6.
_out is input to the clock terminal to retime the ripple carry and delay it by one cycle to perform phase matching with the compensation signal.

FIG. 3 is a diagram showing the configuration of the clock generating means 10. Referring to FIG. 3, the comparator 13 includes:
A predetermined value 2 ⁿ -9 * L is compared with a count value of an up counter 11 included in the variable frequency divider 7,
Only when they are equal, a High signal is output. The flip-flop 14 inputs the output of the comparator 13 to the data input terminal, inputs the output f _out of the voltage controlled oscillator 6 to the clock terminal, and resets the output of the comparator 13. Perform timing.

As shown in FIG. 4, the frequency dividing number generating means 8 has the same configuration as the frequency dividing number generating means 8 of the conventional example. The output of the clock generating means 10 is connected to the clocks of the latches 20 and 21, and the adder 16 determines the numerator of the fractional division by the adder 15 to 19 and the latches 20 to 23.
Is input to the adder 15, N that determines the integer frequency division value is input, the frequency division number to the variable frequency divider 7 is output from the adder 15, and the phase error compensation value Eθ is calculated from the adder 19. Output.

The frequency dividing number generating means 8 generates a frequency dividing number by adding the change of the frequency dividing number to the integral frequency dividing number N from the adder 15 every time the clock is inputted, Then, a phase error compensation value Eθ is generated by fractional frequency division such as +3, -2.

As shown in FIG. 5, the phase error compensating means 9 includes comparators 24-27, OR circuits 28, 29, A
ND circuits 30, 31, current sources 32, 33, inverter 3
4, adders 35 to 38, and latches (D-type flip-flops) 39 and 40. Adders 35, 3
7, a maximum value 2 ⁿ −1 of the count value and a value L * Eθ obtained by multiplying the phase error compensation value Eθ by an integer L are input (2 ⁿ −
1)-(L * Eθ) is output, the load (LOAD) value of the variable frequency divider 7 and L * Eθ are input to the adders 36 and 38, and LOAD ± (L * Eθ) is output. . The contents of the counter of the variable frequency divider 7 are input to terminals A of the comparators 24 to 27, and adders 35 to 38 are input to terminals B.
Is input, and the comparators 24 and 26 output the signal High when the content of the counter at the terminal A is larger than the value at the terminal B.
h level signal, and the comparators 25 and 27 output Hi when the content of the counter at the A terminal is smaller than the value at the B terminal.
gh level signal is output. The outputs of the comparators 24 and 25 are input to an OR circuit 28,
7 is inputted to the OR circuit 29, the MSB of the phase error compensation value Eθ is inputted to the inverter 34, the output of the OR circuit 28 and the output of the inverter 34 are inputted to the AND circuit 30, and the AND circuit 30 is inputted to the AND circuit 30. Is supplied with the output of the OR circuit 29 and the MSB of the phase error Eθ, and the data input terminals of the flip-flops 39 and 40
1 are input and flip-flops 39,
An output f _out of the voltage controlled oscillator 6 is input to a clock input terminal 40, and outputs Q of the flip-flops 39 and 40 are connected to current sources (constant current sources) 32 and 33.

The current source 32 and the current source 33 are controlled by control signals given from the AND circuit 30 and the AND circuit 31.
When the output state of the flip-flop 39 is active, a charging current is output. When the output Q of the flip-flop 39 is active, a charging current for phase error compensation is output from the current source 32. When the output Q of the flip-flop 40 is active, a discharge current for phase error compensation is output from the current source 33.

The phase comparator 3 performs a phase comparison at the falling edge, and the charge pump 4 uses a current type that charges and discharges the loop filter 5 based on a phase difference.

FIG. 6 is a diagram showing signal waveforms at various parts in one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIG. Hereinafter, as a representative example,
The case where the phase error compensation value Eθ = 3 will be described.

FIG. 6A shows the output of the flip-flop 14 included in the clock generating means 10, FIG. 6B shows the output of the comparator 13 included in the clock generating means 10,
FIG. 6C shows the complement of the phase error given to the phase compensator 9, FIG. 6D shows the counter contents of the up-counter included in the variable frequency divider 7, and FIG. Ripple carry of the counter of the up counter 11 included,
6F shows the output of the flip-flop 12 included in the variable frequency divider 7, FIG. 6G shows the output of the comparator 24 included in the phase error compensating means 9, and FIG. Of the comparator 25 included in FIG.
Is the output of the OR circuit 28 included in the phase error compensating means 9,
FIG. 6J shows the OR circuit 2 included in the phase error compensating means 9.
6 (k) is the output of the AND circuit 30 included in the phase error compensating means 9, FIG. 6 (l) is the output of the AND circuit 31 included in the phase error compensating means 9, and FIG. 6 (n) shows the output of the flip-flop 40 included in the phase error compensating means 9, and FIG. 6 (o) shows the phase error compensating value E.
is the MSB (most significant bit) of θ.

In the following, description will be made along the contents of the counter of the up-counter 11 of the variable frequency divider 7.

If the content of the counter of the up counter 11 is 2
^{When n−} 9 * L (L = 4 in FIG. 6), the comparator 13 outputs a High level.

The content of the up counter 11 is 2 ⁿ
When -9 * L + 1, the flip-flop 14 performs retiming of the comparator output and outputs a High level, and the fractional frequency dividing generation means 8 using this as a clock operates to output a new phase error compensation value Eθ = 3.

The content of the up counter is 2 ⁿ -3 * L
, The comparator 24 outputs a high level, and the output of the OR circuit 28 becomes a high level.

The phase error compensation value Eθ is expressed in 2's complement, and when Eθ = 3, the MSB of Eθ is at the low level, and the AND circuit 30 outputs the output of the OR circuit 28 as it is.

When the counter content of the up counter 11 is 2 ⁿ
At the time of -3 * L + 1, the flip-flop 39 retiming-outputs the output of the AND circuit 30, outputs the current source 32 to the operating state. The counter content of the up counter 11 is 2
^When it becomes ^n- 1, the up counter 11 outputs a ripple carry and reads LOAD.

When the counter content of the up counter 11 is LO
At the time of AD, the flip-flop 12 sets the up counter 1
The ripple carry-out of 1 is retimed and output, and this is used as the output signal of the variable frequency divider 7.

When the counter content of the up counter 11 is LO
When the signal becomes AD, the output of the comparator 24 becomes Low level, but the output of the comparator 25 becomes High level, so that the output of the OR circuit 28 remains at High level.

When the counter content becomes LOAD + 3 * L, the comparator 25 outputs a low level, the output of the OR circuit 28 becomes low, the AND circuit 30 becomes low, and the counter content of the up counter 11 becomes low.
When OAD + 3 * L + 1, flip-flop 39 sets
The output of the D circuit 30 is retimed, and the current source 32 is controlled to a non-operating state.

By operating as described above, the pulse width becomes 6 * L periods of the output f _out of the voltage controlled oscillator.

7A shows a current waveform due to a phase error output from the charge pump 4 when Eθ = 3, and FIG. 7B shows a phase error compensating means 9 for compensating the current waveform.
5 shows the waveform of the phase error compensation current output by the control circuit.

In FIG. 7, Id denotes the charge pump 4
And Ic is the current source 3 of the phase error compensating means 9.
Since the current values are 2, 33, and the integrated value of the current due to the phase error is compensated by the integrated value of the phase error compensation current, Id and Ic satisfying the relationship (equal sign) of the following equation (2) are set. You.

Id * (1 / (f _out * 2 ^M )) = 2 * Ic * (1 / (f _out / L)) (2)

As described above, in one embodiment of the present invention, the phase error compensating current is
_Since the signal is generated based on _out , even if the oscillation frequency changes, the above equation (2) always holds, phase error compensation power is performed, and the amount of spurious suppression does not change.

[0046]

As described above, according to the present invention,
Since the phase error compensation current is generated based on the output of the voltage controlled oscillator, even when the oscillation frequency of the voltage controlled oscillator changes, the above equation (2) is always satisfied, and the phase error is compensated. Spurious suppression does not change,
This has the effect.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a variable frequency divider according to one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a clock generation unit according to one embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a frequency division number generating means according to one embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a phase error compensating means according to one embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 7 (a) is an example of the present invention, in which Eθ = 3;
In the case of (1), a current waveform due to a phase error output from the charge pump is shown, and (b) is a diagram showing a waveform of the phase error compensation current output from the phase error compensating means in one embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional frequency synthesizer.

9A shows a current waveform due to a phase error output from a charge pump when Eθ = 3, and FIG. 9B shows a phase waveform output by a phase error compensating means when Eθ = 3. FIG. 4 is a diagram illustrating a waveform of an error compensation current.

FIG. 10 is a diagram showing a configuration of a conventional phase error compensating means.

FIG. 11 is a diagram showing a configuration of a conventional clock generating means.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Crystal oscillator 2 Fixed frequency divider 3 Phase comparator 4 Charge pump 5 Loop filter 6 Voltage controlled oscillator 7 Variable frequency divider 8 Dividing number generating means 9, 9 'Phase error compensating means 10, 10' Clock generating means 11 Up Counter 12 Flip-flop 13, 24 to 27 Comparator 14, 20 to 23, 39, 40 Flip-flop 15 to 19, 35 to 38 Adder 28, 29 OR gate 30, 31 AND gate 32, 33 Current source

Claims (8)

[Claims] A fixed frequency divider for dividing an input signal and outputting the divided signal as a reference frequency; a voltage controlled oscillator; and a variable divider for dividing an output of the voltage controlled oscillator by a dividing number provided by a dividing number generating means. A frequency divider, a reference frequency from the fixed frequency divider and an output from the variable frequency divider as inputs, a phase comparator for detecting and outputting a phase difference between these signals, and an output from the phase comparator. A loop filter that smoothes the resulting phase difference signal and outputs the signal as a signal for controlling the voltage controlled oscillator, and a frequency dividing number generating unit that controls the variable frequency divider by giving an integral frequency dividing number, The voltage-controlled oscillator is controlled by the output of the loop filter to form a phase locked loop, and the frequency dividing number generating means includes a plurality of cascade-connected integrators and a differentiator for differentiating a carry-out signal of the integrator. And an adder The output of the differentiator is input to the adder, and the adder takes the sum of the divided number and the integer part and supplies the output of the adder as the divided number of the variable frequency divider. A frequency synthesizer configured to output a phase error compensation value by differentiating the integration result of the eye integrator (n-1) times, wherein the phase error compensation value from the frequency dividing number generating means; A phase error compensator having a time width generated based on an output of the voltage controlled oscillator, generating a signal for compensating for a phase error, and supplying the signal to an input terminal of the loop filter; and an output from the voltage controlled oscillator. And a clock generating means for supplying a clock to the frequency dividing number generating means as an input. 2. The method according to claim 1, wherein said phase error compensating means inputs a maximum value of a counter of said variable frequency divider and a value obtained by multiplying a phase error compensation value from said frequency dividing number generating means by a predetermined value. A third adder; a second adder and a fourth adder each having a load value of the variable frequency divider and a value obtained by multiplying a phase error compensation value from the frequency division number generating means by a predetermined value as inputs. And the contents of the counter of the variable frequency divider,
, The first to fourth comparators for comparing with the output of the adder, the comparison output of the first and second comparators, and the comparison output of the third and fourth comparators, respectively. First and second OR circuits, a first AND circuit that receives an output of the first OR circuit and an inverted value of the most significant bit of the phase error compensation value, A second AND circuit that receives the output of the OR circuit and the most significant bit of the phase error compensation value as inputs, and latches the outputs of the first and second AND circuits with the output of the voltage controlled oscillator First and second latch circuits, a first current source connected between a higher power supply and an output terminal, and controlled to be turned on and off by an output of the first latch circuit; and an output terminal and a lower power supply. And is controlled on / off by an output of the second latch circuit. A second current source, comprising a frequency synthesizer of claim 1, wherein the outputting the output signal of the phase error correction from the end output, and wherein the. 3. A comparator for comparing a value of a counter constituting the variable frequency divider with a predetermined value, wherein the clock generating means outputs an output of the comparator to an output of the voltage controlled oscillator. 2. A frequency synthesizer according to claim 1, further comprising: a latch circuit for latching the signal. 4. A counter which is set to a load value when the variable frequency divider counts up to a maximum value and counts up from the load value, and a ripple carry of the counter is latched by an output of the voltage controlled oscillator. The frequency synthesizer according to claim 1, further comprising: a latch circuit that performs the operation. 5. A crystal oscillator, a fixed frequency divider for dividing an output of the crystal oscillator and outputting the frequency as a reference frequency, a phase comparator for inputting the reference frequency to one input terminal, a loop filter, A charge pump that charges and discharges the loop filter with a current corresponding to a phase difference output from the phase comparator, a voltage-controlled oscillator that inputs an output voltage of the loop filter as a control voltage, and an output of the voltage-controlled oscillator. A variable frequency divider for supplying a variable frequency-divided signal to another input terminal of the phase comparator; an integrator cascaded in a plurality of stages; a differentiator for differentiating a carry-out signal of the integrator; The output of the differentiator is input to the adder, the adder takes the sum with the integer part of the frequency division number, and supplies the output of the adder as the frequency division number of the variable frequency divider. And frequency dividing number generating means for outputting a phase error compensation value by differentiating the integration result of the n-th integrator n-1 times; a phase error compensation value output from the frequency dividing generating means; A phase error compensating means having a time width generated based on an output of the oscillator and generating a current for compensating for a phase error, an output of which is connected to the loop filter; and an output from the voltage controlled oscillator. Clock generating means for receiving a signal and supplying a clock to the frequency dividing number generating means. 6. The variable frequency divider reads a preset load value each time a ripple carry is output, sets the load value as a counter value, starts counting up from the load value, and starts counting up. 6. The frequency synthesizer according to claim 5, further comprising: an n-bit counter that outputs a content and a ripple carry; and a flip-flop that re-timely delays the ripple carry of the counter by one cycle. 7. The phase error compensating means comprises: a maximum value 2 of a count value of the counter of the variable frequency divider.
a first and a third adder which receive ⁿ⁻ 1 and L * Eθ obtained by multiplying the phase error compensation value Eθ from the frequency ^dividing number generating means by a predetermined integer L; and the variable frequency divider. A second and a fourth adder receiving the load value LOAD of the above and L * Eθ obtained by multiplying the phase error compensation value Eθ by the integer L, and the contents of the counter of the variable frequency divider, First to fourth
First to fourth comparators respectively for comparing with the output of the adder, a first OR circuit having inputs of the outputs of the first and second comparators, and outputs of the third and fourth comparators A second OR circuit having the following inputs: an output of the first OR circuit and the phase error compensation value Eθ
And a first AND circuit which receives an inverted value of the most significant bit of the first logical product, and an output of the second OR circuit and the phase error compensation value Eθ
A second AND circuit having the most significant bit of the input as an input, and first and second latch circuits respectively latching the outputs of the first and second AND circuits with the output of the voltage controlled oscillator. A first constant current source connected between a higher power supply and an output terminal and controlled on / off by an output of the first latch circuit; and a second latch connected between the output terminal and the lower power supply 7. The frequency synthesizer according to claim 6, further comprising: a second constant current source that is turned on / off by an output of the circuit. 8. The clock generating means outputs an active signal and outputs a signal in an active state only when a predetermined value is equal to a count value of an up counter included in the variable frequency divider. The frequency synthesizer according to claim 5, further comprising: a flip-flop configured to retime the output of the comparator with the output of the voltage-controlled oscillator and output the same.