JP2001209573A - Memory address converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that a circuit of a conventional memory address converter used for a personal computer or the like is complex for a memory address converter of MPEG2 decoder. SOLUTION: A memory address converter comprises an address counter for indicating a released region in table renewal after releasing the region, an address counter for indicating a secured region just after a region to be released, and a register for indicating a final address of the secured region. Contents of a table can be renewed so that logical blocks continue even after releasing the region by exchanging the contents of the secured region and the region to be released.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory address translator, and more particularly to a memory address translator suitable for an MPEG2 decoder or the like.

[0002]

2. Description of the Related Art A memory address translation device is used to translate a logical address issued by software executed by a central processing unit (hereinafter referred to as a CPU) into a physical address.

[0003] The memory address conversion device is used to facilitate memory management by software, and the memory address conversion speed requires high speed. By using this memory address translator, software and the CPU do not need to spend time translating addresses in the memory.

In recent MPEG video decoders, it is considered that a memory used by the decoder is used by another CPU or the like. In this case, a memory management device is required to effectively use the memory, and a memory address is required. A conversion device is also required. When a memory address translator is used for an MPEG video decoder as described above, there is a problem that a circuit is complicated in a memory address translator generally used in a conventional personal computer or the like.
This is because the personal computer does not know when access to the memory occurs and the interval of occurrence is not guaranteed, so that the memory translation table is updated every time the access to the memory address translator occurs. .

[0005] A memory address translator mounted on an MPEG video decoder is required to be a circuit as simple as possible at the same time as high-speed memory access. The memory address translation device was a complicated circuit.

[0006]

As described above, in the memory address conversion device used in the conventional personal computer and the like, there is a problem that the conversion circuit is complicated to satisfy the performance required in the personal computer and the like. there were.

An object of the present invention is to provide a memory address translator having a circuit configuration as simple as possible and having functions necessary and sufficient for use in an MPEG2 decoder.

[0008]

In order to achieve the above object, a memory address translator according to the present invention comprises:
A memory address translation device for use in an MPEG2 decoding device, having a table for address translation, wherein the address of the table represents an upper address of a logical memory for a CPU, and the contents of the table represent physical addresses corresponding to the logical addresses. In a memory address translator that reserves an area for each application to be used when using a memory and releases the area when it is no longer needed, the area is secured in order from the lowest address in the address conversion table. When a continuous area is secured and a discontinuity occurs in the secured area when the area is released, a continuous area is secured by packing the areas of higher addresses sequentially into the released logical addresses. And

In the above-mentioned memory address translator, an address counter pointing to an open area at the time of updating a table accompanying an area release, an address counter pointing to a reserved area immediately after the area to be released, and pointing to a final address of the reserved area. A register is provided, and by exchanging the contents of the table of the reserved area and the area to be released, the table contents are updated so that the logical blocks continue even after the area is released.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Overall Configuration) First, a memory address translator according to the present invention, including peripheral circuits, will be described in detail with reference to FIGS.

FIG. 1 is a diagram for explaining the configuration of an MPEG decoding device including a memory address conversion device according to the present invention.

In FIG. 1, a decoding core 11, which is a main part for decoding MPEG2 video, outputs a logical address of the memory to a memory address translator 12 when accessing the memory 14 by writing / reading or the like.

When writing data to the memory 14, the decode core 11 outputs a write signal and write data to the memory access unit 13 and writes the same to the memory 14, and conversely, when reading data from the memory 14, it outputs a read signal to the memory access unit 13. 13 to receive read data from the memory 14 via the memory access unit 13.

The decode core 11 outputs a command for controlling the operation mode of the memory address translation device 12 (normal memory address translation mode, memory area reservation, memory area release, etc.) to the memory address translation device 12. . The form of this command is not particularly related to the essence of the present invention, and may be any.

The memory address translator 12 is controlled by a command from the decode core 11, translates a logical address input from the decode core into a physical address,
The converted physical address is stored in the memory access unit 1
Output to 3.

The memory access unit 13 reads data from the memory 14 by designating a physical address input from the memory address translator 12 in accordance with a read / write signal from the decode core 11, or reads data from the memory 14. Write. Further, the memory access unit 13 includes a memory 14 connected to the outside of the decode chip.
Is a circuit for generating signals such as RAS and CAS necessary for the present invention. Since it is not essentially related to the present invention, any circuit may be used.

In the decoding of MPEG2, due to the characteristic that the decoding is performed in units of video display frames, there is a characteristic that a time zone in which memory access is extremely reduced appears periodically. In addition, the memory area is released and secured basically once per frame, and the time period for releasing and securing the memory area is compatible with the time period when access is reduced. Therefore MPEG
In the 2-decoder, the address conversion needs to be performed at a high speed, but the conversion table may be updated by taking a certain period of time in a time period during which the memory access is reduced.

Next, the process of reducing the open area of the memory address translator according to the present invention will be described in detail with reference to FIG.

"Address" shown in FIG. 2 is a physical address of the memory 14 shown in FIG. 1, and "data" is data held in the memory 14 specified by the physical address.

Now, as shown in FIG.
When the memory of the area 72 is released, the data corresponding to the addresses 73 to 76, which are reserved only after the area, are stored in the addresses 3B to 3B as shown in FIG.
The data is moved to the data area corresponding to E. As a result, in the memory 14, as shown in FIG. 2B, it is possible to secure a continuous free area after the address 3F.

In the following, in all the embodiments of the present invention, the processing of FIG. 2 is performed during a time period in which memory access that appears periodically decreases extremely.

(First Embodiment) Next, a first embodiment of the memory address translator according to the present invention will be described in detail with reference to FIGS.

The start data (3B) of the open area is held in the register 31a, and when a memory open command is input from the decode core 11, the start data (3B) of the open area is set in the D counter 35 ( The characters in parentheses indicate the data value of the address of FIG. 2 that is retained).

The head data (73) of the reserved area (the last address of the area to be released + 1) is held in the register 31b, and when a memory release command is input from the decode core 11, the head data of the reserved area is read. (7
3) is set in the S counter 34.

The leading data (77) of the unused area (the last address of the secured area + 1) is set from the register 31c to the E register 32, and the E register 32 sends the held value to the comparison circuit 33. Output.

The D counter 35 outputs the count value to the decoder 36b and the selector 30b.

The selector 30b outputs the value of the D counter 35 to one input terminal of each selector of the selector group 38.

The S counter 34 outputs the count value to the decoder 36a, the comparison circuit 33 and the selector 30c.

The selector 30c outputs the value of the S counter 34 to the other input terminal of each selector of the selector group 38.

The decoder 36a decodes the output of the S counter 34, and outputs a signal which makes only the address corresponding to the value of the S counter 34 "High" (hereinafter referred to as "H").
It outputs to one input terminal of the R circuit 37 and the selector group 38. Thus, in the selector group 38, the S counter 3
Only the address corresponding to the value of 4 selects the output of the selector 30b, and otherwise selects the output of the selector 30c and outputs it to the register group 39.

The decoder 36b decodes the output of the D counter 35, and outputs a signal at which only the address corresponding to the value of the D counter 35 becomes "H" to the other end of the input terminal of the OR circuit 37.

The OR circuit 37 outputs to the register group 39 a signal in which only the addresses corresponding to the output values of the decoders 36a and 37b become "H". This OR circuit 3
By the output of 7, data is written to the corresponding register of the register group 39. At this time, the register of the register group 39 selected by the decoder 36b includes the selector 30c.
Is written, and the output of the selector 30b is written to the register selected by the decoder 36a. That is, the value is exchanged between the register selected by the decoder 36a and the register selected by the decoder 36b.

The comparison circuit 33 performs comparison for ending the data exchange operation. The comparison circuit 33
When a command to release the memory area is input, the value held in the E register is compared with the value of the S counter 34 to determine whether they are equal. If the values are equal, an "H" signal is output to the decoders 36a and 36b. I do. When the signal of "H" is input, the decoder 36a and the decoder 36b output "Low" (hereinafter, referred to as "L"), and the process of filling the memory area ends.

When the process of filling the memory area is completed, the value of the register 31c holding the unused area is updated, and the operation returns to the normal operation to output the physical address corresponding to the input logical address.

Each signal at the time of the refilling operation of the memory address conversion circuit thus configured is as shown in FIG.

FIG. 4A shows a clock pulse, and FIG.
Is a start pulse generated when a command to release the memory area is input, and the refilling operation is started from the fall of the start pulse.

FIG. 4C shows the value of the D count value. FIG.
(D) is the S count value. FIG. 4E shows a signal for writing the S count value. FIG. 4F shows a signal for writing a D count value. FIG. 4G shows a stop signal which becomes “L” at the negative edge in FIG. 4B and becomes “H” by the output of the comparison circuit 33 to stop the refilling operation of the memory area.

As described above, although a certain amount of time is required for the refilling operation of the memory area, the circuit scale can be reduced as compared with a memory address translator generally used in a conventional personal computer or the like.

The refilling of these memory areas is performed during a time period in which the number of periodically appearing memory accesses is extremely reduced, which is convenient for the MPEG2 decoder.

The present invention is not limited to this, and various other circuits can be considered.

In the embodiment shown in FIG. 3, since the conversion table is provided in the form of a register and the output can be read arbitrarily, a simple swap operation is performed.

(Second Embodiment) FIGS. 5 and 6 show a second embodiment of the memory address translator according to the present invention.
This will be described in detail with reference to FIG.

In this embodiment, a part of FIG. 3 described in the first embodiment is modified, and the selector group 38 on the input side is integrated into a selector 54. In addition, as for the circuit scale, the selector group 38 is integrated into one, but the write buffer 53 is increased instead. Further, the decoders 36b and 36a are combined into one to form the decoder 52 and the OR circuit 37 is omitted, but the number of selectors 51 is increased instead.

In FIG. 5, the same components as those in FIG. 3 are denoted by the same reference numerals and description thereof is omitted. FIG. 6 shows the timing. The operation of the circuit will be described based on the timing in FIG.

First, a value is loaded to the D counter and the S counter by a start pulse. The D counter and the S counter count up once every two clocks. The selectors 30 b and 30 c select the output of the register group 39 based on the values of the D counter and the S counter, and output the selected output to the selector 54. At this time, the output of the selector 30c is
Is delayed by one clock. The selector 54 selects an output of the selector 30b and an output of the write buffer 53 by a DS output selection signal (a signal for selecting one of the outputs of the D counter 35 and the S counter 34) generated by a control circuit (not shown). This selected value is shown in FIG.
This is wdata shown in (f).

The comparison circuit 33 compares the comparison result between the value from the E register 32 and the value from the S counter 34 with a selector 51.
Output to The S counter 34 outputs the count value to the selector 51. The D counter 35 outputs the count value to the selector 51. The selector 51 alternately outputs the values of the D counter and the S counter while the stop signal is “L”, and outputs an invalid signal to the decoder 52 when the stop signal becomes “H”.

The write buffer 53 sets the value of waddr to 1
Delay the clock.

The decoder 52 decodes the input value and outputs an "H" signal to the register group 39. In the register group 39, only the register to which the “H” signal is input from the decoder 52 writes data at the next clock.

That is, wdata is written to the register selected by waddr shown in FIG. Therefore,
The value of the register indicated by the S counter and the value of the register indicated by the D counter are exchanged every two clocks.

Although the circuit scale is smaller than that of FIG. 3, the time required for updating is longer.

(Third Embodiment) FIG. 7 shows a third embodiment according to the present invention. In the present embodiment, the conversion table is provided in the form of a memory. Although the memory has two ports, the first embodiment shown in FIGS.
It takes more time compared to the second embodiment.

Reference numeral 71 denotes a two-port memory; 72, an output register; 73, 75, and 76 selectors; 74, a controller; 77, an S counter; 78, a D buffer for delaying the value from the D counter 79 by two clocks; A counter, 81 is an E register, and 80 is a comparison circuit, which is connected as shown in FIG.

The operation will be described below with reference to the timing chart of FIG.

FIG. 8A shows a clock, and FIG.
The initial values are set in the D counter 79 and the S counter 77 by the start pulse shown in (1), and the D counter 79 performs the count-up operation in response to the D count-up signal shown in FIG.
7 performs a count-up operation in response to an S count-up signal shown in FIG.

The values of the D counter 79 and the S counter 77 are selected by a signal from the controller 74 and become the read address of the two-port memory 71 shown in FIG.

The output of the D counter 79 is taken into the D buffer 78 at the same time as counting up, and is selected as the value of the S counter 77 to become the write address of the two-port memory 71. Since the latency at the time of reading of the two-port memory 71 is one clock, the data is extracted from the output register 72 by two clocks with respect to the read address shown in FIG. D counter 79
Is written to the address of the S counter 77, and the data read from the address of the S counter 77 is stored in the address of the D buffer 78 (the corresponding D
(Address of the counter 79).

FIG. 8H shows a D read enable signal for reading a signal from the D counter, and FIG.
An S read enable signal for reading a signal from the counter, each of which means a read address, not an output enable of an output.

FIG. 8 (k) shows an output signal from the memory,
Here, since a general synchronous two-port memory is considered, the output is delayed by one clock with respect to the address and the enable. FIG. 8 (n) shows a write enable signal for the memory. The value of the output register shown in FIG. 8 (l) is written to the write address shown in FIG. 8 (m). The write data is selected by the selector 73 between the output register shown in FIG. 8 (l) and the S count value shown in FIG. 8 (f). This is for initialization, and during normal operation, The output register shown in FIG. 8 (l) is selected.

As described above, although a certain amount of time is required for the refilling operation of the memory area, the circuit scale can be reduced as compared with a memory address translator generally used in a conventional personal computer or the like.

(Fourth Embodiment) The embodiment shown in FIG. 9 is a modification of the conversion table of the embodiment shown in FIG. 7 so as to be constituted by a one-port memory. Since reading and writing of the memory cannot be performed at the same time, updating takes longer time than in the third embodiment.

FIG. 10 shows the timing.

As in the third embodiment, the data at the address indicated by the D counter and the data at the address indicated by the S counter are exchanged. However, since reading and writing cannot be performed simultaneously in the one-port memory, the read data is temporarily stored. The data is stored in the write buffers 1 and 2 and then written.

First, data read from the address indicated by the S counter is stored in the buffer 1, and then data read from the address indicated by the D counter is stored in the buffer 2. Subsequently, the contents of the buffer 1 are stored at the address indicated by the D counter, and the contents of the buffer 2 are stored at the address indicated by the S counter. The D counter and the S counter are incremented, and the above operation is repeated until the value of the S counter becomes equal to the value of the E register.

As described above, although a certain amount of time is required for the refilling operation of the memory area, the circuit scale can be reduced as compared with a memory address translator generally used in a conventional personal computer or the like.

[0065]

As described above, according to the present invention,
The address translation itself requires high speed, as in the MPEG2 decoder, but has the necessary and sufficient functions with a circuit configuration as simple as possible for applications where there is some time margin when updating the table. A circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a memory access configuration diagram when a memory address translator according to the present invention is used.

FIG. 2 is a diagram showing an operation example of a table update according to the present invention.

FIG. 3 is a diagram showing a configuration of a first embodiment of a memory address translator according to the present invention.

FIG. 4 is a view for explaining the operation of FIG. 3;

FIG. 5 is a diagram showing a configuration of a second embodiment of the memory address translation device of the present invention.

FIG. 6 is a view for explaining the operation of FIG. 5;

FIG. 7 is a diagram showing a configuration of a third embodiment of the memory address translation device of the present invention.

FIG. 8 is a diagram for explaining the operation of FIG. 7;

FIG. 9 is a diagram showing a configuration of a fourth embodiment of the memory address translation device of the present invention.

FIG. 10 is a view for explaining the operation of FIG. 9;

[Description of Signs] 11: decode core, 12: memory address translator,
13: memory access unit, 14: memory, 30
a, 30b, 30c ... selectors, 31a, 31b, 31
c: register, 32: E register, 33: comparison circuit, 3
4 ... S counter, 35 ... D counter, 36a, 36b ...
Decoder, 37 ... OR circuit, 38 ... Selector group, 39 ...
Register group.

Claims (2)

[Claims] 1. A memory address translation device used for an MPEG2 decoding device, comprising a table for address translation, wherein an address of the table represents an upper address of a logical memory for a CPU, and a content of the table corresponds to a physical address corresponding to the logical address. It is configured to mean an address,
In a memory address translator that reserves an area for each application that uses the memory and releases the area when it is no longer needed, the area is secured in order from the lowest address in the address translation table. When a discontinuity occurs in the area secured when the area is released, a continuous area is secured by sequentially filling the area of the higher logical address with the released logical address. apparatus. 2. An apparatus according to claim 1, further comprising: an address counter pointing to an open area when the table is updated upon area release, an address counter pointing to a reserved area immediately after the area to be released, and a register pointing to the last address of the reserved area. 2. The contents of a table of an area and an area to be released are exchanged to update the table contents so that logical blocks continue even after the area is released.
3. The memory address translation device according to claim 1.