JP2001204046A - Image coding/decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image coding/decoding device that carries out sampling with a sampling clock recovered with high accuracy on the basis of frequency or phase information sent from a transmitter side. SOLUTION: An image signal for a TV signal that is sampled and coded by an analog/digital converter 1 and a coding circuit 2 is transmitted and a decoding circuit 12 and a digital/analog converter 11 at a receiver recovers the signal. The receiver is provided with a separation circuit 13, a comparison control circuit 14, an averaging circuit 15, a frequency information generating circuit 16, a phase number generating circuit 18, a control circuit 19, a transmission clock recovery circuit 20, a sampling clock recovery circuit 21, a sampling circuit 22 and a 1/M frequency divider counter 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding / decoding apparatus, and more particularly to an image encoding / decoding apparatus which samples a color television signal on a transmitting side, encodes and transmits the signal, and decodes and reproduces a received signal on a receiving side by a reproduction sampling clock. The present invention relates to a decryption device.

[0002]

2. Description of the Related Art In a digital color television (hereinafter, television is abbreviated as TV) system, an analog color TV signal is sampled (sampled or digitized) by a sampling clock on a transmission side and coded and transmitted. On the receiving side, the sampling clock is reproduced, and the digital image signal is D / A (digital-analog) converted by the sampling clock to reproduce an analog TV signal.

As a conventional example (1) of such an apparatus, a method of reproducing a sampling clock on a receiving side is to transmit frequency information so that the number of sampling clocks in a constant cycle is the same for both transmission and reception. For example, there is a method of synchronizing the sampling frequency (see, for example, Japanese Patent Application No. 52-117613).
In this conventional method, the transmitting side samples the count value of the sampling clock at regular intervals and sends it to the receiving side as count information (frequency information) of an integer value, and the receiving side reproduces the sampling clock based on the frequency information. I do. Since the frequency of the reproduction sampling clock is controlled based on the count value of the integer value obtained every fixed period, a stable and higher frequency than the accuracy (integer) of the count value (frequency information) cannot be obtained. In addition, the reproduced sampling clock frequency has a disadvantage that the frequency information fluctuates under the influence of a quantization error in which the frequency information is quantized to an integer, and a color subcarrier (subcarrier, hereinafter abbreviated as SC) of a TV signal to be reproduced. Also, the stability was not high enough.

For example, when sampling is performed at four times the frequency of SC, one clock of the sampling frequency corresponds to １ ／ of the frequency of the color SC. , 90 ° out of phase. Due to the influence of the quantization error, the analog TV signal on the transmitting side and the reproduced TV signal on the receiving side are converted into a vector scope (phase measuring device).
When compared directly above, the relative phase angle of both color bursts fluctuates greatly with the phase shift of the sampling clock (change in relative phase), and the vector on the receiving side rotates and fluctuates with respect to the transmitting side. I do. For this reason, when editing a color TV signal using the decoded signal, a phase synchronization device such as a frame synchronizer is required to synchronize the phase of the color burst at a constant level. Further, since the frequency of the color SC of the TV signal at the broadcasting station is stable, it has been conventionally considered to use this as a reference signal. The Ministry of Posts and Telecommunications has published measurement data of the frequency deviation of SC at each broadcasting station. In this case, the frequency stability is about 10 −11, and high-precision stability is required. In the method of the conventional example (1), no matter how accurate and stable the SC on the transmitting side is, the TV on the receiving side can be controlled with such high frequency accuracy.
It was difficult to reproduce the signal.

On the other hand, in order to obtain high precision, there is also a method of encoding and transmitting an image signal by synchronizing a transmission line clock with a sampling clock. In this case, restrictions such as that the transmission line cannot be put on a standard transmission line network, that the transmission line clock fluctuates depending on the SC of the TV signal, and that the transmission line clock fluctuates due to switching of the TV signal to be transmitted. There is. There was a disadvantage that it could not be used for general purposes. As a method of solving this, instead of sending an integer count value as frequency information, the transmitting side samples and obtains a signal of the phase angle at regular intervals from a phase reference signal synchronized with the sampling clock phase, It is multiplexed with the video signal and transmitted to the receiving side. On the receiving side, there is a method of performing phase synchronization based on the transmitted phase angle signal.

A conventional example (2) is disclosed in
No. 29, “Sampling clock recovery system and device”
There is. From a different point of view, this prior art can be regarded as a method of transmitting count information with a precision below the decimal point. FIGS. 12A and 12B are block diagrams of the transmitting side and the receiving side of the conventional example (2), respectively. FIG.
The detailed configuration of the phase angle generation circuit 206 in FIG.
Shows the configuration of the phase comparison circuit 216 in FIG.
First, in FIG. 12 (A), a TV signal input A
/ D converter 201 and SC generation circuit 203, sampling clock generation circuit 202, encoding circuit 204, multiplexing circuit 20
5. Phase angle generation circuit 206, transmission clock generation circuit 20
7 and a control circuit 208. The SC generation circuit 203 generates an SC signal in synchronization with the color SC of the input TV signal, and supplies the SC signal to the phase angle generation circuit 206 and the sampling clock generation circuit 202. Sampling clock generation circuit 2
02 generates a sampling clock and an A / D converter 201
Supply to The A / D converter 201 samples the TV signal and outputs a digital signal to the encoding circuit 204. The encoding circuit 204 performs data compression encoding on the digital TV signal, and supplies encoded data to the multiplexing circuit 205.

As shown in FIG. 13, the phase angle generation circuit 206 includes an adder 221, a phase angle circuit 222, and a register 22.
3, a sine wave generation circuit 224, a D / A converter 225, and a comparator 226. The adder 221 and the register 2 register the phase angle for each clock generated by the phase angle circuit 222.
Integrator 23 integrates every transmission line clock,
A phase angle for each transfer clock is obtained, and a sine wave generation circuit 224 is obtained.
To the multiplexing circuit 205. Sine wave generation circuit 224
Generates a digital sine wave corresponding to this phase angle,
The D / A converter 225 performs D / A conversion. Then, the comparator 226 compares the phase with the SC signal supplied from the SC generation circuit 203, supplies the error signal to the phase angle circuit 222, corrects the value of the next phase angle, and controls so that the phases match. I do. Assuming that one cycle of the SC (reference signal) is 360 °, the phase angle of the reference signal at each sampling time by the transmission clock is obtained. 360 ° is normalized by an N-bit dynamic range, and the value of the phase angle for each transmission line clock is obtained as an N-bit phase angle signal. And supplies it to the multiplexing circuit 205. The transmission clock generation circuit 207 generates a transmission clock and generates a multiplexing circuit 205 and a control circuit 208.
And to the phase angle generation circuit 206. Control circuit 20
8 generates a frame control signal for composing a frame and a timing control signal for controlling a period for transmitting a phase angle signal, the frame control signal to a multiplexing circuit 205, and the timing control signal to a phase angle generation circuit 206. Supplied. The multiplexing circuit 205 multiplexes the compressed data, the phase angle signal, and other control data necessary for decoding based on the control signal, and outputs a transmission signal.

On the other hand, on the receiving side shown in FIG. 12B, a separating circuit 209 to which a received signal is input, a transmission clock reproducing circuit 210, a control circuit 211, a decoding circuit 212, and a SC
It comprises a reproduction circuit 213, a D / A converter 214, a sampling clock reproduction circuit 215, and a phase comparison circuit 216. Further, as shown in FIG. 14, the phase comparison circuit 216 includes an adder 221, a phase angle circuit 222, and a register 22.
3, a sine wave generating circuit 224, a D / A converter 225, a comparator 226, and a comparing circuit 227. The transmission clock regeneration circuit 210 reproduces the transmission clock, and separates the transmission clock from the separation circuit 209, the control circuit 211, and the phase comparison circuit 216.
Supply to The separation circuit 209 separates compressed data, a phase angle signal, control data necessary for decoding, and the like based on a control signal from the control circuit 211 and supplies the separated data to each unit. The control circuit 211 sends a control signal for detecting a frame from the transmission signal and separating the data multiplexed into the frame to the separation circuit 209, and a timing for obtaining a phase angle signal on the receiving side for each frame period. The control signal is supplied to the phase comparison circuit 216. The decoding circuit 212 decodes the compressed data, reproduces the digital TV signal, and
In step 4, the signal is converted into an analog signal. The sampling clock recovery circuit 215 controls the VCO in accordance with the control signal of the difference signal from the phase comparison circuit 216, and converts the phase angle signal sent from the transmission side and the phase angle signal obtained on the reception side. The oscillation frequency of the reproduced sampling clock is controlled so that the phases coincide with each other so that the phase angles of the transmitted and received SC signals are synchronized. The reproduced sampling clock is supplied to the D / A converter 214. SC
The generation circuit 213 reproduces the continuous sine wave SC in synchronization with the color verse of the reproduced TV signal, and
16.

A phase comparison circuit 216 shown in FIG. 14 obtains a phase angle on the reception side from the reproduced SC and the transmission line clock in the same manner as the phase angle generation circuit 206 on the transmission side. Comparison circuit 2 for each frame period sent
At 27, the transmission and reception phase angle signals are compared and a comparison error signal is output. The error signal is output to the sampling clock recovery circuit 215.
Supplied to The sampling clock recovery circuit 215 controls a VCO (Voltage Controlled Oscillator) based on the phase angle difference signal of the error signal, and controls the recovered sampling clock so that the phase of SC matches. Usually, since the transmission time of the transmission line clock is constant and stable, the phase of the color burst of the reproduced TV signal is changed by synchronizing the transmission and reception SC phases by the above-described configuration. Are synchronized. As a result, the phase of the sampling clock is synchronized with the phase of the sampling clock on the receiving side. That is, this method uses the phase angle generation circuit 206
Then, a phase angle value is generated as a digital value for each transmission line clock, and a sine wave PCM value is read out from the ROM corresponding to the phase angle value and D / A converted to digital processing to generate an analog sine wave local SC signal. . Then, the phase comparison between the local SC signal and the reference SC obtained from the video signal is performed. The comparison error signal is feedback-controlled to the generated value of the phase angle, the phase angle is controlled so that the local SC matches the reference SC, and the phase angle of the reference SC is equivalently obtained as a digital phase angle value. The value of the obtained phase angle is
Transmit to the receiving side.

On the other hand, on the receiving side, the reproduced TV
The reproduction SC is obtained from the signal, and the phase comparison circuit 216 generates a local SC synchronized with the reproduction SC in the same manner as the transmission side, thereby obtaining the phase angle of the reproduction SC. The phase angles of the SCs on the transmitting side and the receiving side are compared. Using the comparison result, the frequency of the reproduced clock reproduced by the sampling clock reproducing circuit 215 is controlled so that the transmission and reception phase angles match. By synchronizing the phases in this way, a sampling clock with high frequency accuracy is reproduced.

[0011]

The prior art described above has several problems. First, a filter including an analog circuit and having good characteristics is required to make the local SC signal highly accurate, and the device becomes large-scale, and practical use is difficult.

Second, in order to simplify the filter and obtain high-precision phase information, the phase angle generation circuit needs to operate at a sufficiently high speed compared to the frequency of the reference SC. In the related art, the operation clock of the digital processing circuit that generates a phase angle with respect to the reference SC frequency (3.5795 MHz) uses a transmission line clock, and the high frequency (DS
In the case of 1, it is necessary to operate with a clock of 44.736 MHz), and the power consumption and the mounting area are increased due to the speeding up of the processing circuit. Also, a comparator for comparing the reference SC with the local SC needs to be able to sufficiently perform comparison at a high frequency.

Third, in order to reduce the size of the device,
It is necessary to reduce the number of parts by implementing an LSI or a processor. If the circuit is a high-speed processing, high-speed LSI development is required to implement LSI. High speed and large power consumption make it difficult to miniaturize and expensive. Furthermore, D
Since an analog processing circuit including an A / A converter is required,
It has been difficult and expensive to implement an analog / digital mixed LSI as compared to an LSI using only digital circuits.

Fourth, in order to apply the method of the conventional example (2) to the device configured in the conventional example (1), there is a difference in whether information to be transmitted is frequency information or phase information. Overall, changes on both the sending and receiving sides were required, and the changes were large-scale.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for reproducing a sampling clock by transmitting frequency information or phase information of an integer count value, which can reproduce a sampling clock with high frequency accuracy with a simple configuration. An object of the present invention is to provide an image encoding / decoding device using a clock recovery circuit.

[0016]

An image encoding / decoding apparatus according to the present invention samples an image signal such as a color TV signal on a transmission side and encodes and transmits the signal. Is a device that reproduces the above-described signal with a sampling clock that is decoded and reproduced. Its features are: an averaging circuit that averages frequency information on the transmission side to obtain high-precision frequency information; a transmission clock regeneration circuit that regenerates a transmission clock from a received signal; and frequency information from the averaging circuit. A comparison control circuit for obtaining a control signal by comparing received frequency information, a sampling clock recovery circuit for recovering a sampling clock based on the control signal, and sampling the sampling clock with a reference clock from the transmission clock recovery circuit A sampling circuit for obtaining a sampled value of the sampled clock, a M dividing counter for dividing the reference clock by a predetermined dividing ratio M,
A phase-shift number generating circuit for generating a phase-shift number from the frequency-divided counter value of the M frequency-divided counter so that phase shifts of one cycle of the sampling clock are arranged in order, and sampling for sampling by the sampling circuit A frequency / phase information generating circuit that obtains frequency information of a clock and inputs the frequency / phase information to a comparison control circuit, and samples a decoded signal with a sampling clock.

According to the embodiment of the present invention, the reference clock is obtained from a frequency dividing circuit for dividing the output from the transmission clock reproducing circuit. Phase information is received instead of frequency information and averaged with high precision to obtain phase information. At the same time, phase information is obtained with high precision from a sampling clock to reproduce a high-frequency precision sampling clock. As a reference clock, a clock obtained by switching a clock having the same frequency and a different phase in a predetermined order at regular intervals is used, and a function substantially similar to the use of a high-frequency reference clock is obtained. Further, a memory circuit is provided for storing a sample value of the sampling clock in a phase number. Four times the SC frequency and a reference clock frequency of 1
The division ratio M of the 9.44 MHz, M division counter is selected to be 167. Also, the sampling clock frequency on the transmitting side is set to 1
3.5 MHz and reference clock frequency 19.44M
Hz, and the dividing ratio M of the M dividing counter is selected to be 36. Further, instead of frequency information, time stamp information is received, frequency information or phase information averaged with high precision is obtained from the time stamp information, and frequency information or phase information is obtained with high precision from the reproduced sampling clock. Then, a sampling clock with high frequency accuracy is reproduced based on this phase information.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction and operation of a preferred embodiment of an image encoding / decoding apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a TV signal is encoded by encoding a signal obtained by sampling a sampling clock four times as large as that of the color SC, and
In a device for transmitting on a 55.52 Mbps transmission line,
The transmitting side transmits the frequency information of the sampling clock to the receiving side. On the receiving side, frequency information on the transmitting side is averaged, frequency information on the reproduced sampling clock is obtained to the decimal place precision, and frequency information on the sampling clock on the transmitting side and the receiving side is compared with high precision after the decimal point. . By controlling the frequency of the reproduced sampling clock so as to eliminate the comparison error, it is possible to reproduce a sampling clock that matches the frequency of the sampling clock on the transmission side with high precision, and the frequency accuracy of the color SC of the reproduced TV signal is improved. An image encoding / decoding apparatus using a sampling clock recovery circuit capable of reproducing a TV signal whose frequency coincides with the transmission side with high precision is obtained.

FIG. 1 is a block diagram showing a preferred embodiment of an image encoding / decoding apparatus according to the present invention.
Is a transmitting side, and (B) is a receiving side. The transmitting side in FIG. 1A includes an A / D converter 1, an encoding circuit 2, a multiplexing circuit 3, a frequency information generating circuit 4, a sampling clock circuit 5, a control circuit 6, a transmission clock circuit 7, and a frequency dividing circuit. 8. The A / D converter 1 samples (digitizes) the TV signal into 10 bits. The encoding circuit 2 encodes the digital signal. The multiplexing circuit 3 multiplexes and transmits the encoded signal, the frequency information signal sampled at regular intervals, and other necessary control signals. The sampling clock circuit 5
Generates a 14.3 MHz sampling clock synchronized with four times the color burst (SC) of the input TV signal. The frequency information generating circuit 4 counts (counts) the number of sampling clocks, and resamples the frequency count value of the sampling clock for each cycle of the signal supplied from the control circuit 6 to obtain frequency information. The transmission clock circuit 7 is 155.52 MHz.
To generate a transmission clock. The frequency dividing circuit 8 divides the transmission clock by 8 to generate a 19.44 MHz frequency-divided transmission clock (reference clock). The control circuit 6 generates a control signal every fixed period (for example, every period obtained by dividing the reference clock by K) in order to send the frequency information to the receiving side.

The receiving side shown in FIG. 1 (B) includes a separating circuit 13 and a transmission clock reproducing circuit 20, a decoding circuit 12, a D / A converter 11, to which a signal received via a transmission line is inputted.
Averaging circuit 15, comparison control circuit 14, frequency phase information generation circuit 16, memory circuit 17, phase number generation circuit 18,
It comprises a control circuit 19, a sampling clock recovery circuit 21, a sampling circuit 22, an M frequency dividing counter 23 and a frequency dividing circuit 24. The transmission clock recovery circuit 20 extracts the clock timing from the above-mentioned received signal to obtain 155.52.
Regenerate the MHz transmission clock. The separation circuit 13 separates a coded signal, frequency information, a control signal, and the like from the received signal. The decoding circuit 12 decodes the encoded signal to reproduce a digital image signal. The D / A converter 11 converts a digital image into an analog image signal. Averaging circuit 15
Obtains averaged transmission-side frequency information from frequency information transmitted from the transmission side. The comparison control circuit 14 compares the reception-side frequency information with the averaged transmission-side frequency information,
A control signal is generated such that the phase information on the receiving side matches the phase information on the transmitting side. The sampling clock regeneration circuit 21 regenerates a sampling clock according to the control signal. The frequency dividing circuit 24 divides the transmission clock by 8 to generate a 19.44 MHz frequency-divided clock (reference clock). The sampling circuit 22 samples the reproduced sampling clock with a 19.44 MHz reference clock and outputs a sampled value of a 1-bit sampling clock. The M frequency dividing counter 23 frequency-divides the 19.44 MHz reference clock by 167. Phase number generation circuit 18
Generates the phase number i such that the phases of one cycle of the sampling clock are arranged in order from the frequency division counter value n. The memory circuit 17 stores the sample value of the sampling clock in the phase number. The frequency / phase information generation circuit 16 calculates the difference between the phase number of the reference phase of the sampling clock obtained from the change point of the sampling value of the sampling clock arranged in the order of the phase number and the phase number corresponding to the M frequency division counter value. The frequency information of the sampling clock at the time of sampling by the sampling circuit 22 is obtained with a precision below the decimal point at regular intervals. The control circuit 19 generates a timing for each fixed period for obtaining frequency information.

FIG. 2 shows a specific configuration example of the frequency / phase information generating circuit 4 on the transmitting side shown in FIG. For example, an 8-bit counter 41 operated by a sampling clock, a register 42 for sampling a counter value by a transmission cycle control signal from the control circuit 6, a register 43 for delaying the output of the register 42 by one control cycle, and both registers It comprises a subtractor 44 for obtaining the frequency counter value of one control cycle with the accuracy of the lower 8 bits from the difference between 42 and 43. Counter 4
1 is a free counter that counts up for each sampling clock, and the counter output is sampled for each transmission cycle. From the output of the subtractor 44, the lower 8-bit value of the counter value for one transmission cycle is output. On the other hand, FIG.
A specific configuration example of the frequency / phase information generation circuit 16 in the receiving side shown in FIG. Shift register 30, determination circuit 3
1, a reference phase numbering device 32, a modulo subtractor 33, a register 34, a comparator 35, a counter 36, a converter 37, a register 38, a register 39, and a subtractor 40. Components 30 to 33 include a normalized phase number generator 3
00.

Next, the operation of the sampling clock recovery circuit shown in FIG. 1 will be described. The control circuit 6 on the transmitting side has a signal of 19.44
MHz divided transmission clock (reference clock) 2430
A transmission cycle timing control signal having a frequency of 62.5 Hz is generated by frequency division of × 8 × 16, and a counter value is sampled every about 16 ms to obtain frequency information. This transmission cycle corresponds to about one field (1/60 second) of the TV signal. The count value of the sampling clock of 14.3 MHz in one cycle is about 0.25 MHz. The width of the value represented by the lower 8 bits of the counter value of one transmission cycle is ± 12.
8, frequency information that can cover a frequency variation of about ± 500 ppm is transmitted. Transmission speed 1
In a 55.52 Mbps SDH signal, 9 rows × 270
Since the frame of the byte of the row is constituted, the frequency information is sampled and transmitted every 128 times of this cycle.

The M-divider counter 23 on the receiving side divides the supplied 19.44 MHz frequency-divided transmission clock (reference clock) by 167, and counts a count n in the range of 0 to 166 to the phase number generator 7. Output to From the relationship between the sampling clock frequency (14.31818 MHz) and the frequency-divided transmission line clock frequency (19.44 MHz), the value of M at which the integral multiple M of the divided transmission clock cycle is substantially equal to the integral multiple of the sampling clock cycle is calculated. Ask. When M = 167, 123.
Since it becomes 0008 times, M is set to 167 in advance.

The phase number generation circuit 18 calculates the following equation between the counter value n and the phase number i: n = MOD (−19 × i, 167) = MOD (148 ×
i, 167), and outputs a phase number i corresponding to the input of the counter value n. n = MOD (−19 ×
i, 167), the following characteristics are obtained. Phase number i = 0, 1, 2, 3, 4,..., 165, 166 Counter value n = 0, 148, 129, 110, 91,..., 38, 19 When these are rearranged in the order of n, i = MOD (123 × n, 167). Counter value n = 0, 1, 2, 3, 4,..., 165, 166 Phase number i = 0, 123, 79, 35, 158,.

The phase number i corresponding to the counter value n is output according to the characteristics of the conversion table. Control circuit 19
Divides a 19.44 MHz frequency-divided transmission clock (reference clock) by a value of 2430 × 8 × 16 to 62.5 Hz
, A timing control signal having a frequency of The frequency / phase information generation circuit 16 uses the phase number from the phase number generation circuit 18, the sampled value of the sampling clock from the memory circuit 17, and the control signal of the transmission cycle from the control circuit 19, and uses 8 bits after the decimal point. And 16-bit count information of the reproduced sampling clock having a total of 16 bits of precision with 8 bits after the decimal point, and output it for each transmission cycle.
The averaging circuit 15 temporarily stores the 8-bit frequency information (integer count information) supplied from the separation circuit 13 for each transmission cycle, and stores it in a long cycle (for example, 128 transmission cycles).
Transmission frequency (approximately 16 ms)
Ask every time. In this case, a count value with an accuracy of 7 bits after the decimal point is obtained, and the obtained transmission side averaged frequency information is
The signal is supplied to the comparison control circuit 14.

Next, the comparison control circuit 14 subtracts the transmission-side averaged frequency information from the reception-side reproduced clock frequency information with 16-bit precision, and obtains a 16-bit (8-bit precision for the decimal point or less) comparison error. Get the signal. When the feedback control is performed from the comparison error signal E, generally, the control amount is dE when the differential signal is dE and the integral signal is ΔE.
The product sum (α · E) of coefficients α, β, and γ of each signal of E, E, and ΣE
+ Β · E + γ · ΔE). The frequency control signal C is supplied to the sampling clock generation circuit 21.
, And controls the VCXO for generating the clock to control the reproduction frequency of the sampling clock, and performs feedback control so that the comparison error becomes zero. The coefficient β determines the time constant until the frequency becomes constant, the coefficient α determines the pull-in acceleration in the frequency change region, and the coefficient γ determines the time constant at which the phase is constant. The control amount is determined in consideration of the voltage response characteristics of the VCXO.

The counter value n generated by the M frequency dividing counter 23 in FIG. 1B is supplied, supplied to the reference phase number 32 and also supplied to the memory circuit 17 as an address. The shift register 30 shown in FIG. 3 reads and holds the sample value of the sampling clock corresponding to the address of the count value from the memory circuit 17. The point in time when the sample value Yn of the sampling clock changes from Yn-1 = "0" to Yn = "1" is determined as the rising point of the sampling clock, and the reference phase number at this time is (n-1). And However, for applications where the sampling clock frequency fluctuates greatly,
There is a possibility that the cycle of the sampling clock fluctuates with time, and the order of the sample points projected on the phase of one cycle and the sample value may be out of order due to the influence of jitter or error. Therefore, three consecutive sample points (n−
2) shows a case in which a change in sample value at (n-1) and n is detected and determined. When the address to the memory circuit 17 is i, the shift register 31 stores three consecutive sample values Y including the sample value Yn read from the memory circuit 17.
n-2, Yn-1, and Yn are supplied to the determination circuit 31.

The determination circuit 31 determines that Yn-2 = “0”, Yn
When -1 = "0" and Yn = "1", it is determined to be the rising point of the sampling clock, and a signal for setting the reference phase number is supplied to the reference phase number unit 32. Reference phase number 3
2 is a value obtained by dividing the input address value n by a divided transmission clock to 1
The clock is delayed and supplied to the reference register as the address value n-1. When a set signal is received from the determination circuit 31, a reference phase number is set. Yn-2 =
When “0”, Yn−1 = “0”, and Yn = “1”, n−
1 is set as the reference phase number in indicating the rising point of the sampling clock. The reference phase number is set approximately once in the frequency division period of 167. The modulo subtractor 33 subtracts the reference phase number in supplied from the reference phase number 32 from the phase number i supplied from the phase number generation circuit 18, and subtracts the result by modulo operation of 167 to obtain the divided transmission clock. , The scaled phase number j = MOD (i
-In, 167).

Next, the signal of the phase number obtained by the normalized phase number generator 300 is compared with the comparison / determination unit 35 and the register 34.
And to the converter 37. The register 34 outputs a signal delayed by the period of the reference clock. The comparison determination circuit 35 compares the current phase number J with the phase number Jn-1 one clock before. If the phase number exceeds 167, it exceeds the rising point of the sampling clock.
Is subtracted to indicate the phase value from 0 again. Therefore, if Jn <Jn-1, it can be determined that the sampling clock has risen during this time, and one clock is supplied to the counter 36. Otherwise, it is determined that there is no rising of the sampling clock, and the counter 3
6 is not supplied with a clock. The counter 36 is an 8-bit counter, counts the number of rising edges of the sampling clock, and supplies an integer frequency count value to the register 38. The converter 37 normalizes the scaled phase number j with a value of 8 bits (256) below the decimal point and outputs the result. The converter 37 outputs 256/167 to the input of the phase number j.
It has a conversion characteristic of converting the value of xj into an integer and outputting the result. The converter 37 can be configured by a multiplier, a ROM, or the like. The phase number value indicating the decimal part, which is standardized to 8 bits, is stored in the register 3
8 is supplied.

Therefore, the register 38 stores 8 decimal places.
It is possible to obtain phase information in which a total of 16 bits of the phase angle value W are 8 bits after the bits and the decimal point. The signal is sampled and output at the timing of the transmission cycle signal from the control circuit 19 and supplied to the register 39 and the subtractor 40. The register 39 operates with the timing clock of the transmission cycle signal, and outputs a signal delayed by one cycle to the subtractor 40. The subtractor 40 subtracts the phase angle signal of the register 39 one cycle before from the phase angle signal of the register 38, and obtains a frequency count value of the frequency information for each transmission cycle with a precision below the decimal point. The frequency phase information generation circuit 16 obtains a total of 16 bits of frequency information in which the integer part is 8 bits and the decimal part is 8 bits.

Next, FIG. 4 shows a specific configuration example of the averaging circuit 15 in FIG. The averaging circuit 15 includes a memory circuit 51, a counting circuit 52, an integrating circuit 53, and a control circuit 54. The memory circuit 51 stores the frequency information for each transmission cycle. The control circuit 54 monitors the fluctuation of the frequency information. When the frequency information is stable, the frequency information up to 128 cycles before is sequentially read out, multiplied by a coefficient of 1/128 by the coefficient circuit 52, and the frequency information of 128 cycles is accumulated by the integration circuit 53. The frequency information averaged over 128 periods is output. On the other hand, when the frequency information fluctuates, the frequency information up to four cycles before is sequentially read out, multiplied by a coefficient of 1/4 by the coefficient circuit 52, and the frequency information of four cycles is accumulated by the integration circuit 53. And outputs frequency information averaged over four periods.

Next, a second embodiment of the sampling clock recovery circuit according to the present invention will be described. In the second embodiment, the count value of the frequency cumulative count from the first transmission cycle to each transmission cycle (in other words, a value indicating the phase) is used as the frequency information. The free counter operated by the sampling clock corresponds to a counter value sampled for each transmission cycle, and this frequency information can be regarded as phase information of an integer part. In the first embodiment described above, since the count value for each transmission cycle is transmitted, if there is a transmission path error, the relative phase information obtained by integrating the frequency information cannot be correctly reproduced on the receiving side, and is reproduced. The phase of the TV signal will be shifted. The frequency information or the phase information is collectively referred to as frequency phase information.

In the second embodiment, even if there is a transmission error, the frequency information indicating the correct phase is transmitted in the transmission cycle in which the frequency information (frequency phase information) indicating the next phase is transmitted. , It is possible to maintain the relative phase with integer period accuracy. The configuration of the second embodiment is the same as that of the first embodiment.
The difference between the frequency information generation circuit 4, the averaging circuit 15, and the frequency phase information generation circuit 16 of FIG. In FIG. 2, the frequency information generating circuit 4 of the second embodiment outputs the sampled cumulative counter value obtained at the output of the register 42 as frequency information indicating the phase, multiplexes the frequency, and transmits the multiplexed value to the receiving side. .

Averaging circuit 15 'in the second embodiment.
FIG. 5 shows a specific example of the configuration. That is, the register 61, the subtractor 62, the average value circuit 63, the adder 64, the subtractor 65,
It comprises a non-linear circuit 66, an adder 67 and a register 68. The phase frequency information is input to the register 61 and the subtracters 62 and 65 of the average value circuit 15 '. A frequency counter value within the time of one transmission cycle is obtained from the output of the subtractor 62. This value is input to the average value circuit 63,
An average value obtained by averaging over a long transmission cycle is output. The averaging circuit 63 has the same function as the averaging circuit 15 of FIG. 1 and has a configuration shown in FIG. The adder 64 is 1
The average value of the transmission cycle and the accumulated count value up to the cycle before output from the register 68 are added to obtain an accumulated counter value up to the current transmission cycle. The subtracter 65 calculates a difference value between the accumulated counter value sent from the transmitting side and the reproduced accumulated counter value, and inputs the difference value to the nonlinear circuit 66. The output of the nonlinear circuit 66 is 0 until the magnitude of the miscalculation is 1. On the other hand, if the value is 1 or more, the output characteristic is such that the slope is initially smaller than 1, for example, 1/4, and is gradually increased, and after crossing the straight line of the slope 1 from the origin, the output characteristic matches the slope. Having. The output value of the non-linear circuit 66 is input to the adder 67 and is added to the reproduction counter value. When the receiving-side cumulative counter value deviates from the transmitting-side cumulative counter value, correction is performed so that the value gradually approaches the transmitting-side cumulative counter value. The corrected counter value becomes an output and is input to the register 68.

Next, the frequency / phase information generating circuit 16 of the second embodiment outputs the accumulated counter value obtained as the output of the register 38 in FIG. The comparison control circuit 14 performs comparison control of the 16-bit signal using the cumulative counter value without using the transmission cycle counter value as the frequency information. Other functional operations are the same as those of the first embodiment.

Next, a description will be given of a third embodiment of the sampling clock recovery circuit according to the present invention. This is the case where the sampling clock is 13.5 MHz, and the configuration diagram is the same as FIG. Sampling clock FS = 13.5 MHz, frequency-divided transmission clock (reference clock) FL1 = 19.44M
In the case of Hz, (13.5 / 19.44) × M becomes close to an integer value when M = 36, and (13.5 / 19.44) × M
/19.44)×36=25. From the relationship between the sampling clock frequency (13.5 MHz) and the frequency-divided transmission line clock frequency (19.44 MHz), the value of M at which the integer multiple M of the divided transmission clock cycle is substantially equal to the integer multiple of the sampling clock cycle is determined. When calculated, 25.0000 when M = 36
Since it becomes 0 times, M = 36 is set.

The M frequency dividing counter 23 receives the input supplied 1
The 9.44 MHz frequency-divided transmission clock is divided by 36 to obtain 0
The count value n in the range of .about.35 is output to the phase number generator 18. By dividing by 36, phase information can be determined with an accuracy of 1/36 of one cycle of the sampling clock. As in the case of the first embodiment, as a result of obtaining the relationship between the counter value (sampling number) n and the phase number i, the phase number generating circuit 7 sets n between the counter value n and the phase number i.
= MOD (13 × i, 36).
The phase number i corresponding to the input of the counter value n is output. The following characteristic is obtained from the characteristic of n = MOD (13 × i, 36). Phase number i = 0, 1, 2, 3, 4, 5,..., 34, 35 Counter value n = 0, 13, 26, 3, 17, 30,. In other words, i = MOD (25 × n, 36). Counter value n = 0, 1, 2, 3, 4,..., 34, 35 Phase number i = 0, 25, 14, 3, 28,. Output the phase number i.

In the block diagram of the first embodiment, M
It is necessary to change the frequency dividing counter 23, the phase number generating circuit 18, the memory circuit 17, and the frequency / phase information generating circuit 16 so as to correspond to the above-described characteristics. The frequencies of the sampling clock circuit 5 and the sampling clock recovery circuit 21 are also changed.
Other configurations are the same as those in the first embodiment.

Next, a description will be given of a fourth embodiment of the sampling clock recovery circuit according to the present invention. The block diagram is the same as that of the third embodiment described above. However, in the third embodiment, the sampling clock is 13.5 MHz and the divided clock (reference clock) FL1 = 19.44 MHz
In the case of (1), the phase identification accuracy of the sampling clock is 1/36 of one cycle (74 ns). This means that the accuracy of quantization of the sampling phase in the time axis direction is equivalent to about 2 ns. In the fourth embodiment, the frequency of the frequency-divided transmission clock is increased, the sampling phase is made highly accurate, and the error is reduced. The frequency of the frequency dividing circuit 24 is changed from the frequency of 8 to the frequency of 2 and the frequency-divided transmission clock (reference clock) is set to FL1 = 7.
7.76 MHz. The value of 13.5 / 77.76 × M, which is an integral multiple of FS / FL1, becomes close to an integer value.
This is the case where M = 144. 13.5 MHz / 77.76
MHz × 144 = 25, which is an integer. M frequency dividing counter 2
3 divides the inputted 77.76 MHz frequency-divided transmission clock by 144 and inputs a count value n in the range of 0 to 143 to the phase number generation circuit 7. The division by 144 means the accuracy of 1/144 period of the sampling clock, and
About O.4 / 144 ns. The phase information can be determined with an accuracy of 5 ns.

The phase number generating circuit 7 has a conversion characteristic of n = MOD (−23 × i, 144) between the counter value n and the phase number i, and corresponds to the input of the counter value n. Output the phase number i. n = MOD (−23 ×
i, 144), the following characteristics are obtained. Phase number i = 0, 1, 2, 3, 4, 5,..., 142, 143 Counter value n = 0, 121, 98, 75, 52, 29,. In other words, i = MOD (25 × n, 144). Counter value n = 0, 1, 2, 3, 4, 5,..., 142, 143 Phase number i = 0, 25, 50, 75, 100, 125,. , And outputs the phase number i corresponding to the counter value n. In the configuration diagram of the third embodiment described above, the frequency dividing circuit 24, the M frequency dividing counter 23,
It is necessary to change the phase number generation circuit 18, the memory circuit 17, and the frequency phase information generation circuit 16 according to the above-mentioned characteristics. The other configuration is the same as that of the third embodiment.

Next, a description will be given of a fifth embodiment of the sampling clock recovery circuit according to the present invention. In the fourth embodiment, the resolution of the phase information can be increased by increasing the reference clock. However, since the circuit for obtaining the phase information requires high-speed processing of 77.76 MHz, a technique for obtaining high accuracy by low-speed processing is used. Show. FIG. 6 is a block diagram on the transmitting side of the fifth embodiment. In this embodiment, the frequency of the frequency-divided transmission clock (reference clock) is 19.44 MHz, and M
Every time sampling is completed at a cycle of = 36, the phase of the frequency-divided transmission clock is shifted at a cycle of 77.76 MHz, and sampling is sequentially performed four times. As a result, the sampling time is four times longer, but the frequency of the reference clock is 19.44 MHz, and the sampling point of the sampling clock can be obtained with the same phase accuracy as the sampling point of 77.76 MHz. it can.

In the circuit shown in FIG. 6, the same reference numerals are used for the components corresponding to FIG. 1B for convenience. The receiving side of the sampling clock recovery circuit of FIG.
Converter 11, decoding circuit 12, separation circuit 13, comparison control circuit 14, averaging circuit 15, memory circuit 17, control circuit 1
9. In addition to the transmission clock recovery circuit 20, the sampling clock recovery circuit 21, and the sampling circuit 22, a frequency / phase information generation circuit 72, a phase number generation circuit 73, an M frequency dividing counter 75, and an adaptive frequency dividing circuit 76 are provided. Adaptive frequency divider 7
6 generates a reference clock of 19.44 MHz. However, a reference clock whose phase is sequentially delayed by a width of a period of 77.76 MHz is generated for each predetermined period T (period of 36 clocks at 19.44 MHz).

Next, FIG. 7 shows a waveform diagram of the clock.
(A), (b), (c) and (d) show a 19.44 MHz clock having four phases that are sequentially shifted in phase. The output clock is a clock obtained by switching these four clocks every period T. (Da), (ab), (b)
Four periods of c) and (cd) form one period. The phase delay is one cycle T1 (1/1 / 77.76 MHz clock).
77.76 MHz) and is sequentially delayed from 0 to 3 times the period (phase (a) to phase (d)).
The rising point of the clock is delayed by a period T1 every time the phase changes. When switching from the phase (d) to the phase (a), the phase is advanced by three times the period T1. Accordingly, the last clock of the phase (d) and the first clock of the phase (a) overlap each other. Therefore, the output of the final clock of the phase (d) is stopped. In the order of (a) to (d) phases, the number of clocks (the number of rising edges) in each T period is 36, 36, respectively.
With 36 and 35, the total is 143. Sampling circuit 22
Performs sampling at the rising edge of this clock.

In the figure of the clock, the numbers in parentheses are the numbers that become the sampling points corresponding to the same phase as the count value (0 to 143) when the period of T is sampled by the 77.76 MHz clock. . One of the 143 sample points will be missing, but one of the missing points will be accurate to 1/72 and the other one will be missing.
Since the phase information can be determined at an accuracy of 1/144 at 42 locations, approximately the same accuracy as sampling at 77.76 MHz can be obtained. The adaptive frequency dividing circuit 76 samples a reference clock composed of a 19.44 MHz clock whose phase changes at regular intervals as shown in FIG.
Output to 5 Further, a 2-bit phase indication signal k (k = 0 to 3) indicating the phase of (a) to (d) delay is output to the M frequency dividing counter 75. The M frequency dividing counter 75 has 19.4
The 4 MHz reference clock is divided by 36 or 35.
When k = 0 to 2, a 36-divided counter is used, and when k = 3, a 35-divided counter is used. Assuming that the counter value is m, a value obtained by adding the phase display signal k to a value obtained by quadrupling the counter value, and 4m + k is a count value n. This is Figure 7
Corresponds to the numbers in parentheses. The M frequency dividing counter 75 converts the obtained count value n (= 4m + k) into the phase number generation circuit 7
3 and output to the frequency phase information generation circuit 72.

The phase number generating circuit 73 has the conversion characteristic of i = MOD (25 × n, 144) shown in the fourth embodiment, and converts the input counter value n to the phase number i according to the conversion characteristic. And output. Frequency phase information generation circuit 7
2 is configured in the same manner as in FIG. 3, and obtains a reference phase number from a change point in sample values of successive phase numbers. Then, a normalized phase number is obtained from the phase number, a normalized counter value W is obtained, and a counter value W sampled for each transmission cycle is obtained and output to the comparison control circuit 14. This gives 1
Even at a low frequency sampling of 9.44 MHz, 77.76 M
It is possible to obtain the same phase pull-in accuracy as that of sampling with a high frequency reference clock of Hz.

Next, a sixth embodiment of the present invention will be described. In the first to fifth embodiments, a divided transmission clock obtained by dividing a transmission clock is used as a reference clock output from the frequency dividing circuit 12. However, it is not always necessary to use a transmission clock generated in the transmitting device as a reference clock for obtaining phase information. If the transmission system is a synchronous network, ATM
Even in a system configuration in which transmission data is packetized and transmitted, etc., if the transmission side device and the reception side device are configured to generate a reference clock for obtaining phase information in synchronization with a network clock, transmission and reception are possible. A synchronized reference clock can be obtained. Then, the phase information of the sampling clock can be obtained with high precision, and the phase of the sampling clock can be synchronized with high accuracy in transmission and reception.

Next, a seventh embodiment of the present invention will be described. In order to obtain a phase number indicating the reference point of the rising edge of the sampling clock, for convenience of explanation, the memory circuit 17 has an address corresponding to M, temporarily stores the sampled values, and then stores the sampled values having successive phase numbers. Is read to find the reference point, but the memory circuit 17 may be omitted. FIG. 8 shows a block diagram on the receiving side in the seventh embodiment. D / A converter 11, decoding circuit 12, separation circuit 13, comparison control circuit 14, averaging circuit 15, phase number generation circuit 18, control circuit 19, transmission clock recovery circuit 20, sampling clock recovery circuit 21, sampling Circuit 22,
It comprises an M frequency dividing counter 23, a frequency dividing circuit 24 and a frequency phase information generating circuit 91. That is, as compared with the block diagram shown in FIG. 1B, the absence of the memory circuit 17 and the configuration of the frequency / phase information generation circuit 91 are partially changed. FIG. 9 shows a detailed configuration of the normalized phase number generator 300 'of the frequency phase information generation circuit 91. It comprises a shift register 30, a reference phase numbering device 32, a subtractor 33, a judgment control circuit 101 and a judgment circuit 102, and the other structures are the same as those in FIG.

In the first embodiment described above, if the phase number of the counter value n is i, n = MOD (−19 × i,
167), and the sample values for every 19 counter values n have adjacent phase numbers. The determination control circuit 101 stores the phase number finally written in the shift register 30 as the final phase number. Next, the phase number generation circuit 18
And the final phase number supplied from
When the phase number matches the adjacent phase number, a control signal for writing the sample value supplied from the sampling circuit 22 to the shift register 30 is issued, and the phase number at that time is set as a new final phase number. The shift register 30 is a 3-bit shift register, and a sample value of the sampling clock is written every time the phase number is decreased by one by a write signal. At the output of the shift register 30, three sample values are sequentially arranged in ascending order of phase number. The determination circuit 102 detects the rising point of the sampling clock from the three consecutive sample values. Upon detection, a detection signal is output to the determination control circuit 101 and the reference phase number 32. Reference phase number 3
In step 2, the phase number corresponding to the detection position supplied from the control circuit 19 is set and output when the detection signal comes.
In the worst case, a period of 19 times is required until the rise is detected. Once the reference phase number is detected, a phase number corresponding to the vicinity of the reference phase number, in this case, a value larger than the reference phase number by 6 is set as the final phase number.
Start detection again. When writing to the shift register is performed 6 to 7 times, the phase number becomes close to the reference phase number, the rise can be detected quickly, and the reference phase number can be repeatedly detected approximately every one cycle.

Next, an eighth embodiment of the present invention will be described. The reference clock (frequency-divided transmission clock FL1) for sampling the sampling clock FS can be similarly realized without any problem even when the reference clock is lower. The color TV signal is transmitted according to ITU-T standard H.264. 261 / H. For example, the present invention is applied to a case where the data is encoded by a method such as H.263 and transmitted at 6.312 Mbps and reproduced on the receiving side, and the sampling clocks on the transmitting side and the receiving side are synchronized. Accordingly, the color burst of the TV signal on the transmitting side and the color burst of the TV signal reproduced on the receiving side can be synchronized.
FIG. 10 shows a block diagram on the receiving side of the eighth embodiment.
D / A converter 11, decoding circuit 12, separation circuit 13, comparison control circuit 14, averaging circuit 15, frequency phase information generation circuit 16, phase number generation circuit 18, control circuit 19, transmission clock reproduction circuit 20, sampling It comprises a clock recovery circuit 21, a sampling circuit 22, and an M frequency dividing counter 23. The separating circuit 13 separates compressed and coded data of a predetermined rate, which has been coded so as to have a data rate allocated to the transmission of the video signal, and outputs it to the decoding circuit 12. The decoding circuit 12 conforms to ITU-T standard H.264. A signal obtained by encoding and compressing a TV signal using the encoding method of H.263 is decoded. The transmission clock recovery circuit 20 generates a 6.312 MHz clock, and outputs a sampling circuit 22, an M frequency dividing counter 2
3 and to the control circuit 19.

H. In the 261 or 263 system, the sampling clock is FS = 13.5 MHz. The transmission path is
At 6.312 MHz, 13.5 MHz / 6. 312 MH
An integer multiple M of z = 2.1387832 is searched for a value of M that approaches an integer value as much as possible. 2.13878 with M = 36
32 × 36 = 76.9962. The error is 0.00
38. Since the precision of 1/36 is 0.027, the magnitude of the error 0.0038 with respect to the resolution precision of 0.027 is about 1/7, which is negligible. The M frequency dividing counter 23 is composed of a 36 frequency dividing counter. The phase number generation circuit 18 has the following conversion characteristics.

In this embodiment, the relationship of n = MOD (−7 × i, 36) holds between the counter value n and the phase number i. From this relationship, the following characteristics are obtained. Phase number i = 0, 1, 2, 3, 4, 5,..., 34, 35 Counter value n = 0, 29, 22, 15, 8, 1, 1,. In other words, i = MOD (5 × n, 3
6). The counter value n = 0, 1, 2, 3, 4, 5,..., 34, 35 The phase number i = 0, 5, 10, 15, 20, 25,. The phase number i corresponding to the counter value n is output according to the characteristics of the conversion table. The frequency / phase information generation circuit 91 obtains frequency / phase information of the counter value W sampled at regular intervals from the sample value and the phase number i.

Next, a ninth embodiment of the present invention will be described. The transmission cycle for transmitting the frequency information is obtained by dividing the frequency of the reference clock, but the transmission cycle may not be an integral multiple of the cycle of the reference clock. Since the reference clock uses a transmission clock, the phase information in the transmission cycle is known if the phase information at the sampling point of the reference clock in the vicinity is known, and the amount of advance of the sampling clock phase for each reference clock,
It is obtained by calculation from the relationship between the reference clock phase and the transmission cycle phase. For example, in the first embodiment, when the reference clock is 19.44 MHz, the phase of the sampling clock that advances by one clock is 0.736532. Therefore, 15
1/8 of the 5.52 MHz transmission line clock cycle
Is 0.0920665, and the phase number at this time corresponds to 15.375. In other words, 155.5
In the clock cycle of 2 MHz, the phase is shifted by 15.375 / 167, so that the correction can be made according to the shift between the reference clock and the sampling phase of the predetermined transmission cycle. For example, the sampling phase of the phase information is
When three clocks are advanced by a clock of 155.52 MHz, 1 is added to the phase number obtained by the phase of the reference clock.
If the value of 5.375 × 3 = approximately 46 is added and corrected, frequency phase information at a phase without sample points can be obtained.

Finally, a tenth embodiment of the present invention will be described. In the MPEG-2 system standardized by the ITU-T, the time stamp system is used to transmit the information of the sampling clock, but this embodiment is an example in the case where the time stamp information is received. . The block diagram of the basic configuration is the same as that of FIG. 1 described above, but the configuration of the averaging circuit 15 is different. The average value circuit 15 of this embodiment calculates a time difference and a frame number difference from the previous time stamp information from the time stamp information and the time. Based on this, frequency information is obtained, and the frequency information is further averaged to obtain averaged frequency information with high precision after the decimal point. By controlling the frequency of the reproduced sampling clock based on this, a sampling clock with a stable frequency can be reproduced.

FIG. 11 is a timing chart showing the relationship between the sampling points of the sampling clock and the reference clock.
(A) shows a sampling clock, (b) shows a corresponding sample number, (c) shows a phase number, (d) shows a reference clock, and (e) shows a count value n.

The configurations and operations of the various embodiments of the image encoding / decoding apparatus according to the present invention have been described above in detail. However, such an embodiment is merely an exemplification of the present invention, and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made without departing from the spirit of the invention.

[0057]

As apparent from the above description, the following remarkable effects can be obtained by the image encoding / decoding apparatus of the present invention. First, the phase of the sampling clock can be detected with high accuracy without using an analog circuit. The reason is that, when the sampling clock is sampled by the reference clock (divided transmission clock), N and M are determined so that the integer multiple M of the reference clock cycle can be substantially equal to the integer multiple N of the sampling clock cycle.
At this time, the sampling clock is sampled by M reference clocks having different phases. Then, by rearranging the sample values of the sampling clock in phase order and detecting the rising edge of the sampling clock, the phase of the sampling clock can be easily detected with a high precision of 1 / M.

Secondly, even when the transmission side receives the integer count information, the reception side outputs the high-precision average count value obtained by averaging the count information and the phase information of the reproduced sampling clock. Since the sampling clock can be generated with high precision by comparing the reproduction count information obtained with high precision and making the comparison error zero, the TV can be generated with high stability and high precision.
The SC of the signal can be reproduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a sampling clock recovery circuit according to the present invention, wherein FIG.
Is the receiving side.

FIG. 2 is a block diagram of a detailed configuration example of a frequency phase information generation circuit shown in FIG.

FIG. 3 is a detailed block diagram of a frequency phase information generation circuit shown in FIG.

FIG. 4 is a block diagram showing a specific configuration example of an averaging circuit shown in FIG.

FIG. 5 is a block diagram of another specific configuration example of the averaging circuit.

FIG. 6 is a block diagram of a receiving side in an image encoding / decoding apparatus according to a third embodiment of the present invention.

FIG. 7 is a timing chart of a reference clock generated by the adaptive frequency divider shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a receiving side in an image encoding / decoding apparatus according to a seventh embodiment of the present invention.

9 is a detailed block diagram of a main part of the frequency / phase information generation circuit shown in FIG.

FIG. 10 is a block diagram showing a configuration on a receiving side in an eighth embodiment of an image encoding recovery clock recovery circuit according to the present invention.

FIG. 11 is a diagram illustrating a relationship between a sampling clock and a reference clock at a head office.

FIG. 12 is a block diagram showing a configuration of a conventional sampling clock recovery circuit, where (A) is a transmitting side and (B) is a receiving side.

FIG. 13 is a detailed block diagram of the phase angle generation circuit of FIG.

FIG. 14 is a detailed block diagram of the phase comparison circuit in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Encoding circuit 3 Multiplexing circuit 4, 16, 91 Frequency information generation circuit 5 Sampling clock circuit 6, 19 Control circuit 7 Transmission clock circuit 8, 24 Divider circuit 11 D / A converter 12 Decoding circuit 13 Separation circuit 14 Comparison control circuit 15, 15 'Averaging circuit 17 Memory circuit 18 Phase number generation circuit 20 Transmission clock recovery circuit 21 Sampling clock recovery circuit 22 Sampling circuit 23 M frequency dividing counter

Continued on the front page F-term (reference) 5C057 AA01 AA06 CC04 EA03 EB12 EJ01 EK01 GB01 GB02 GB04 GB07 GE02 GF01 GF02 GF05 GF07 GG01 GH02 GJ08 GJ09 5C059 KK23 RC03 RC04 RE04 SS02 UA09 UA10 5J0BC BC01 BC01 BC02 BC

Claims (8)

[Claims] An image signal such as a color television signal is sampled on a transmitting side, and a signal to be coded and transmitted is decoded. A receiving side decodes coded data from a received signal and reproduces the signal with a reproduced sampling clock. An averaging circuit for averaging the transmission-side frequency information to obtain high-precision frequency information; a transmission clock regeneration circuit for regenerating a transmission clock from the received signal; and the averaging circuit. A comparison control circuit that obtains a control signal by comparing the frequency information and the reception side frequency information, a sampling clock regeneration circuit that regenerates a sampling clock based on the control signal, and a transmission clock regeneration circuit that regenerates the sampling clock. A sampling circuit for obtaining a sampled value of the sampled clock by sampling the sampled clock with a reference clock from the MPU, and an M dividing counter for dividing the reference clock by a predetermined dividing ratio M A phase number generation circuit for generating a phase number from the frequency division counter value of the M frequency division counter such that the phases of the one cycle of the sampling clock are arranged in order. A frequency phase information generating circuit for obtaining frequency information of a sampling clock and inputting the frequency information to the comparison control circuit, wherein the decoding signal is D / A-converted by the sampling clock. . 2. An image encoding / decoding apparatus according to claim 1, wherein said reference clock is obtained by a frequency dividing circuit for dividing an output from said transmission clock reproducing circuit. 3. High-precision sampling by receiving phase information instead of the frequency information to obtain highly accurate averaged phase information and obtaining high-precision phase information from the reproduced sampling clock. 3. The image encoding / decoding apparatus according to claim 1, wherein the apparatus reproduces a clock. 4. A function substantially the same as that of using a high-frequency reference clock by using a clock obtained by switching clocks having the same frequency and different phases in a predetermined order at regular intervals as said reference clock. 4. The image encoding / decoding apparatus according to claim 1, wherein: 5. A memory circuit according to claim 1, further comprising a memory circuit for storing a sample value of said sampling clock in a phase number.
5. The image encoding / decoding device according to item 1. 6. The transmission side sampling clock is selected to have a frequency four times the subcarrier frequency, the reference clock frequency to be 19.44 MHz, and the frequency division ratio M of the M frequency division counter to be 167. The image encoding / decoding device according to claim 1. 7. The transmission-side sampling clock frequency is set to 1
3.5 MHz and the reference clock frequency is 19.4
2. The image encoding / decoding apparatus according to claim 1, wherein the frequency is 4 MHz, and the frequency division ratio M of the M frequency division counter is 36. 8. Time-stamp information is received in place of said frequency information, frequency information or phase information averaged with high precision is obtained from said time-stamp information, and frequency information or phase information is obtained with high precision from a reproduced sampling clock. 2. The image encoding / decoding apparatus according to claim 1, wherein information is obtained, and a sampling clock with high frequency accuracy is reproduced based on the phase information.