JP2001203329A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a construction of an MIM capacitor which is suitable for a fine wiring process, has small parasitic resistance and parasitic capacitance and has a high capacitance. SOLUTION: This semiconductor device has a 1st electrode 1 which is formed on a semiconductor substrate and has a flat plane shape as a whole, a dialectic layer 2 which is formed on the 1st electrode and has a lat plane shape as a whole, a 2nd electrode 3 which is formed on the dielectric layer 2 and has a flat plane shape as a whole, an interlayer insulating layer 6 which covers the 1st and 2nd electrodes and the dielectric layer as a while and has a plurality of via-holes 4 and 7 bottomed by the surface of the 2nd electrode 3 therein, and conductive layers filling the via-holes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a structure of a capacitor element used in a high-frequency analog integrated circuit.

[0002]

2. Description of the Related Art In recent years, multi-layer wiring technology for semiconductor integrated circuits has not only been reduced in wiring design rules, but also has been steadily miniaturized by introducing metal into via holes and introducing a completely flattening technique for interlayer films. ing.

In general, high-frequency analog integrated circuits used in the field of mobile communications require passive elements such as resistors and capacitors as well as active elements that operate at high speed to handle small signals of high frequency. In such an integrated circuit, it is necessary to reduce the parasitic resistance and the parasitic capacitance in order to improve the operation speed and reduce the power consumption. Among them, in the capacitor element, the MIM having significantly smaller parasitic resistance and parasitic capacitance than the conventional MOS type capacitor is used.
(Metal-Insulator-Metal) type capacitors are being generally used.

FIG. 5 is a sectional view of a conventional MIM type capacitor. A conventional MIM type capacitor is manufactured by the following steps. The interlayer insulating film 16 on the metal silicide layer 11 serving as a lower electrode (first electrode) is patterned by photolithography, and the first opening 14 where a capacitor is formed by reactive ion etching, and the metal silicide layer 11 A second opening 17 in which a lead electrode is formed is formed. After the formation, the dielectric film 12 is
Is deposited on the surface of the interlayer insulating film 16 including the openings.
Then, the dielectric film 12 is patterned so as to leave the dielectric film 12 deposited on the bottom surface of the opening. Then, on the patterned dielectric film 12 and the second opening 1
Aluminum is deposited inside and patterned to form an extraction electrode layer 18 and aluminum 13 to be an upper electrode (second electrode).

[0005]

By the way, the multilayer wiring technology of a semiconductor integrated circuit not only reduces the above-described wiring design rules, but also embeds metal in contact holes and via holes and chemically forms interlayer insulating films. The introduction of a completely flattening technique by a mechanical method is continuing the miniaturization.

However, in the conventional MIM type capacitor structure, it is necessary to increase the electrode area of the capacitor in order to secure the capacitance value. In addition, it is necessary to increase the depth of the first opening 14 in order to reduce the parasitic capacitance between the electrode wiring and the substrate. Therefore, it is necessary to provide a deep step in the interlayer insulating film 2. The metal buried contact formation method, which is a fine wiring technology, deposits a metal film inside an opening by a chemical vapor deposition method and performs reactive ion etching (RI).
E) or 0.8 μm by chemical mechanical polishing (CMP)
This is a technique of embedding metal in a contact hole or a via hole having a size as small as an angle. However, since the first opening 14 has a deep step, it is very difficult to form a metal film uniformly over the entire opening. There is a risk that the film may be reduced at the step portion or the film may peel off.

[0007] Further, as shown in FIG.
It is not desirable to make the surface flat in consideration of securing the capacitance value of the capacitor and simplicity of drawing out the electrode of the capacitor. However, from the viewpoint of fine wiring processing, it is essential to completely flatten the surface of the interlayer insulating film 16.
From the above, it can be said that the above-mentioned structure of the planar type MIM capacitor is inappropriate when compared with the fine wiring technology.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a structure of an MIM capacitor having a small parasitic resistance and a small parasitic capacitance and having a high capacitance value, which is suitable for fine wiring processing.

[0009]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention is formed on a semiconductor substrate.
A first electrode having a whole planar shape,
A dielectric layer formed on the upper surface of the first electrode and having an overall planar shape; a second electrode formed on the upper surface of the dielectric layer and having an overall planar shape; 2
And an interlayer insulating layer that covers the entire dielectric layer and has a plurality of via holes inside the surface of the second electrode, and a conductive layer that fills the via holes. Is a first feature.

A semiconductor device according to the present invention includes a capacitor formed on a semiconductor substrate and having a plate-shaped electrode, and a plurality of via holes that cover the entire capacitor and have the upper electrode surface of the capacitor as a bottom surface. And an electrically conductive layer filling the via hole.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of depositing a first electrode layer, a dielectric layer, and a second electrode layer on a semiconductor substrate in this order; Covering the dielectric layer with an interlayer insulating layer, forming a via hole exposing the surfaces of the first electrode layer and the second electrode layer, and filling the inside of the via hole with a conductive layer. And a step of flattening the surface of the interlayer insulating layer.

According to these features, since the planar capacitor is located at the lowermost portion of the interlayer insulating film, it can occupy a large area on the semiconductor substrate. Therefore, in order to secure the electrode area of the capacitor, it is not necessary to provide a deep step on the semiconductor substrate and deposit an electrode layer on the side and bottom surfaces of the step.

Further, since the via holes are used to draw out the electrodes of the planar capacitor located at the lowermost part of the interlayer insulating film, the surface of the interlayer insulating film can be flattened.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of the MIM type capacitor of the present invention. FIG. 2 is a sectional view taken along the line AA 'of FIG. On the interlayer insulating layer formed on the semiconductor substrate, a first electrode layer 1 having an entire planar shape is formed, and on the upper surface of the first electrode layer 1, the first electrode layer 1 is formed. Similarly, a dielectric layer 2 having the entire surface in a one-plane shape is formed. This dielectric layer 2 needs to be formed smaller than the first electrode layer 1 by the area where the first extraction electrode 8 is formed. In the case of the present embodiment, it is 100 μm.
About 2.

On the upper surface of the dielectric layer 2, there is formed a second electrode layer 3 having a whole planar shape. This second
The area of the electrode layer 3 is substantially equal to that of the dielectric layer 2. These first electrode layer 1, second electrode layer 3, and dielectric layer 2
Is covered with an interlayer insulating layer 6 having a thickness of about 1.5 to 2.0 μm. The interlayer insulating layer 6 has a plurality of via holes 4 and 7 each having a surface of the first electrode 1 and a surface of the second electrode 3 as bottom surfaces. The via holes 4 and 7 are filled with a conductive layer to form a first extraction electrode 5 and a second extraction electrode 8, respectively. Interlayer insulating layer 6
Upper electrode wiring 9 is formed on the surface, and is connected to the first extraction electrode 5 and the second extraction electrode 8.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below. 3 and 4 are views showing the steps of manufacturing the MIM type capacitor of the present invention. In FIG. 3, a first Al layer is formed on a semiconductor substrate. By patterning this Al layer, the MIM
A first electrode layer 1 serving as a lower electrode of the mold capacitor is formed.

After the first electrode layer 1 is formed, a silicon nitride film which will later become the dielectric layer 2 is deposited on the upper surface of the first electrode layer 1 and continuously formed as the upper electrode of the MIM type capacitor. The second electrode layer 3 is formed of a TiN film or a WSi film. Thereafter, in order to secure a connection region between the first electrode layer (second extraction electrode 8) of the first electrode layer to be formed later and the first electrode layer 1, a photolithography step and a reactive ion etching ( RIE: Reactive Ion Etchi
ng), the silicon nitride film, TiN film or WS
The i film is simultaneously patterned to remove the silicon nitride film, the TiN film or the WSi film corresponding to the connection region, and expose the surface of the first electrode layer 1 at that portion. At this point, the silicon nitride film is formed on the dielectric layer 2 by TiN film or WS.
This means that the i film has been processed into the second electrode layer 3.

Next, as shown in FIG. 4, the first electrode layer 1,
BPSG so as to cover the dielectric layer 2 and the second electrode layer 3
(Boron-Phospho Silicate Glass) is formed on the semiconductor substrate by a CVD (Chemical Vapor Deposition) method or the like. And the first electrode layer 1,
Then, via holes 4 and 7 for exposing the surface of the second electrode layer 3 are formed in the interlayer insulating layer 6 by a method such as RIE.

By selectively growing a metal such as tungsten in the via holes 4 and 7, a first extraction electrode 5 and a second extraction electrode which are extraction electrode layers of the first electrode layer 1 and the second electrode layer 3 are formed. An electrode 8 is formed. After forming the first extraction electrode 5 and the second extraction electrode 8, the surface of the interlayer insulating layer 6 is subjected to CMP (Chemical Mechanical Polishing).
And the like, and the planarized interlayer insulating layer 6
An upper electrode wiring 9 is formed of Al or the like on the surface, and is connected to the first extraction electrode 5 and the second extraction electrode 8.

As described above, by using the semiconductor device of the present invention and the method of manufacturing the same, it is possible to maintain the flatness without forming a large-area interlayer film step in the region where the MIM type capacitor is formed. , A low parasitic capacitance, a low parasitic resistance, and a highly reliable MIM-type capacitor element.

As described above, the embodiments of the present invention are not limited to those described above, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

[0023]

According to the present invention, an M transistor having a small parasitic resistance and a small parasitic capacitance and a high capacitance value suitable for fine wiring processing.
It is possible to provide an IM-type capacitor structure.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a view showing a structure of a conventional MIM type capacitor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first electrode layer 2 dielectric layer 3 second electrode layer 6 interlayer insulating layer 4, 7 via hole 5 first extraction electrode 8 second extraction electrode 9 upper layer electrode wiring

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 HH08 JJ19 KK08 KK28 KK33 NN34 PP07 QQ08 QQ09 QQ10 QQ13 QQ37 QQ39 QQ48 RR06 RR15 VV10 XX03 5F038 AC04 AC05 AC15 CA07 CA10 EZ15 EZ20

Claims (11)

[Claims] A first electrode formed on a semiconductor substrate and having an entire planar shape; a dielectric layer formed on an upper surface of the first electrode and having an overall planar shape; A second electrode formed on the upper surface of the dielectric layer, the entirety of the second electrode having a planar shape; and covering the first and second electrodes and the entire dielectric layer. A semiconductor device, comprising: an interlayer insulating layer having a plurality of via holes therein serving as a bottom surface; and a conductive layer filling the via holes. 2. The semiconductor device according to claim 1, wherein said first and second electrodes are formed of aluminum. 3. The semiconductor device according to claim 1, wherein said first and second electrodes are formed of metal silicide. 4. A capacitor formed on a semiconductor substrate, the electrode of which has a plate shape, and an interlayer insulation having a plurality of via holes which cover the entire capacitor and have a top electrode surface of the capacitor as a bottom surface. A semiconductor device comprising: a layer; and a conductive layer filling the via hole. 5. The semiconductor device according to claim 4, wherein said upper electrode is made of aluminum. 6. The semiconductor device according to claim 4, wherein said upper electrode is formed of metal silicide. 7. The semiconductor device according to claim 1, wherein said conductive layer is formed of tungsten. 8. The semiconductor device according to claim 1, wherein an upper surface of said interlayer insulating layer has a planar shape. 9. The semiconductor device according to claim 8, further comprising an upper wiring formed on an upper surface of said interlayer insulating layer. 10. A step of depositing a first electrode layer, a dielectric layer, and a second electrode layer on a semiconductor substrate in this order, and connecting the first, second electrode layer, and dielectric layer to an interlayer insulating layer. Covering the first electrode layer and the second electrode layer; forming a via hole exposing the surface of the first electrode layer and the second electrode layer; filling the inside of the via hole with a conductive layer; Flattening the semiconductor device. 11. The flattening step is performed by a chemical mechanical polishing method.
The method according to claim 10, wherein the method is performed by (Chemical Mechanical Polishing).