JP2001196507A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2001196507A JP2001196507A JP2000005766A JP2000005766A JP2001196507A JP 2001196507 A JP2001196507 A JP 2001196507A JP 2000005766 A JP2000005766 A JP 2000005766A JP 2000005766 A JP2000005766 A JP 2000005766A JP 2001196507 A JP2001196507 A JP 2001196507A
- Authority
- JP
- Japan
- Prior art keywords
- insulating base
- concave portion
- semiconductor element
- sealing resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 151
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229920005989 resin Polymers 0.000 claims abstract description 84
- 239000011347 resin Substances 0.000 claims abstract description 84
- 238000007789 sealing Methods 0.000 claims abstract description 78
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 230000002093 peripheral effect Effects 0.000 claims abstract description 25
- 239000007788 liquid Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 abstract description 27
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 230000035882 stress Effects 0.000 description 13
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000843 powder Substances 0.000 description 5
- 229920001187 thermosetting polymer Polymers 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 239000011800 void material Substances 0.000 description 5
- 238000005219 brazing Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- NEIHULKJZQTQKJ-UHFFFAOYSA-N [Cu].[Ag] Chemical compound [Cu].[Ag] NEIHULKJZQTQKJ-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- OREHYUREDGKKCS-UHFFFAOYSA-N [Pb].[Au].[Ag].[Sn] Chemical compound [Pb].[Au].[Ag].[Sn] OREHYUREDGKKCS-UHFFFAOYSA-N 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- BRPQOXSCLDDYGP-UHFFFAOYSA-N calcium oxide Chemical compound [O-2].[Ca+2] BRPQOXSCLDDYGP-UHFFFAOYSA-N 0.000 description 1
- 239000000292 calcium oxide Substances 0.000 description 1
- ODINCKMPIJJUCX-UHFFFAOYSA-N calcium oxide Inorganic materials [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】 絶縁基体1にクラックが発生したり、封止樹
脂6に剥離や破裂が発生し、内部に封止される半導体素
子3a・3bを長期間にわたり、正常かつ安定に作動さ
せることができない。
【解決手段】 一方の主面に半導体素子3bを収容する
ための凹部1bを有し、凹部1bの内側から主面の外周
部にかけて複数の配線導体4が配設されて成る略四角平
板状の絶縁基体1と、凹部1bの底面に搭載された半導
体素子3bと、一端部が配線導体4の主面の外周部に導
出した部位に接合され、他端部が絶縁基体1の側面から
外側に突出した複数の外部リード端子2と、絶縁基体1
・半導体素子3b・外部リード端子2の一端部を封止す
る封止樹脂6とから成り、凹部1bは、その側面が傾斜
面または階段状面である半導体装置である。傾斜面また
は階段状面となった凹部1b側面で応力が良好に分散緩
和され、絶縁基体1にクラックが発生することを防止で
きる。
PROBLEM TO BE SOLVED: To provide a semiconductor element 3a, 3b, which is internally and normally sealed, for a long period of time due to cracks in an insulating substrate 1, peeling or rupture in a sealing resin 6, and for a long time. Cannot be operated. SOLUTION: A substantially square plate-like shape having a concave portion 1b for accommodating a semiconductor element 3b on one main surface, and a plurality of wiring conductors 4 arranged from the inside of the concave portion 1b to the outer peripheral portion of the main surface. The insulating base 1, the semiconductor element 3 b mounted on the bottom surface of the concave portion 1 b, and one end joined to a portion led out to the outer periphery of the main surface of the wiring conductor 4, and the other end directed outward from the side surface of the insulating base 1 A plurality of projecting external lead terminals 2 and an insulating base 1
The semiconductor device 3b comprises a sealing resin 6 for sealing one end of the external lead terminal 2, and the recess 1b is a semiconductor device whose side surface is an inclined surface or a stepped surface. The stress is satisfactorily dispersed and alleviated on the side surface of the concave portion 1b which is an inclined surface or a step-like surface, so that the occurrence of cracks in the insulating base 1 can be prevented.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、コンピュータ等の
情報処理装置に使用される樹脂封止型の半導体装置に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device used for an information processing device such as a computer.
【0002】[0002]
【従来の技術】従来、コンピュータ等の情報処理装置に
使用される樹脂封止型の半導体装置は、半導体素子と、
半導体素子を搭載するダイパッドと、ダイパッドの周辺
から所定間隔で延出する多数の外部リード端子と、半導
体素子およびダイパッドならびに外部リード端子のダイ
パッド近傍部を封止する封止樹脂とから構成されてい
る。そして、この半導体装置は、ダイパッドと多数の外
部リード端子とが枠状の連結帯を介して一体的に連結形
成されたリードフレームを準備するとともに、このリー
ドフレームのダイパッド上面に半導体素子を搭載固定
し、次に半導体素子の各電極と外部リード端子のダイパ
ッド近傍部とをボンディングワイヤを介して電気的に接
続するとともに半導体素子およびダイパッドならびに外
部リード端子のダイパッド近傍部を封止樹脂により封止
することによって製作されている。2. Description of the Related Art Conventionally, a resin-encapsulated semiconductor device used for an information processing device such as a computer includes a semiconductor element,
The semiconductor device includes a die pad on which a semiconductor element is mounted, a large number of external lead terminals extending at predetermined intervals from the periphery of the die pad, and a sealing resin for sealing the semiconductor element, the die pad, and a portion near the die pad of the external lead terminal. . In this semiconductor device, a lead frame in which a die pad and a large number of external lead terminals are integrally connected via a frame-shaped connecting band is prepared, and a semiconductor element is mounted and fixed on the upper surface of the die pad of the lead frame. Then, each electrode of the semiconductor element is electrically connected to a portion of the external lead terminal near the die pad via a bonding wire, and the semiconductor element, the die pad, and the portion of the external lead terminal near the die pad are sealed with a sealing resin. It is manufactured by.
【0003】なお、リードフレームは、銅や鉄を主成分
とする金属から成り、銅や鉄を主成分とする金属の薄板
に従来周知の打ち抜き加工やエッチング加工等の金属加
工を施すことによって製作される。A lead frame is made of a metal mainly composed of copper or iron, and is manufactured by subjecting a thin plate of a metal mainly composed of copper or iron to metal processing such as punching or etching which is conventionally known. Is done.
【0004】また、かかる従来の半導体装置は、半導体
素子およびダイパッドならびに外部リード端子のダイパ
ッド近傍部を封止樹脂で封止した後、外部リード端子を
枠状の連結帯より切断分離させ、各々の外部リード端子
を電気的に独立させるとともに各外部リード端子の外側
端部を外部電気回路基板の配線導体に半田を介して接続
させることにより内部に収容する半導体素子の各電極が
外部リード端子を介して外部電気回路に接続されること
となる。In such a conventional semiconductor device, a semiconductor element, a die pad, and a portion of an external lead terminal near a die pad are sealed with a sealing resin, and then the external lead terminal is cut and separated from a frame-shaped connecting band. The external lead terminals are electrically independent, and the outer end of each external lead terminal is connected to the wiring conductor of the external electric circuit board via solder, so that each electrode of the semiconductor element housed inside is connected via the external lead terminal. To be connected to an external electric circuit.
【0005】しかしながら、近時、半導体素子は高密度
化・高集積化が急激に進み、その電極数が大幅に増大し
てきており、これに伴って半導体素子の各電極を外部電
気回路に接続する外部リード端子もその線幅が例えば0.
3 mm以下と細く、かつ隣接する外部リード端子の間隔
も0.3 mm以下と極めて狭いものとなってきた。そのた
めこの従来の半導体装置においては、例えば外部リード
端子を外部電気回路に接続する際等に外部リード端子に
外力が印加されるとその外力によって外部リード端子が
容易に変形し、隣接する外部リード端子が接触して短絡
を発生させたり、外部リード端子を所定の外部電気回路
に正確かつ強固に接続することができないという問題点
を有していた。また、ひとつの半導体装置内に複数個の
半導体素子を収容し、それにより半導体素子の外部電気
回路基板に対する実装密度を高いものとするとともに半
導体素子間の信号の授受の高速化を図る要求もあった。In recent years, however, the density and integration of semiconductor elements have been rapidly increasing, and the number of electrodes has been greatly increased. Accordingly, each electrode of the semiconductor element has been connected to an external electric circuit. External lead terminals also have a line width of, for example, 0.
It is as thin as 3 mm or less, and the interval between adjacent external lead terminals is also as extremely small as 0.3 mm or less. Therefore, in this conventional semiconductor device, when an external force is applied to the external lead terminal, for example, when connecting the external lead terminal to an external electric circuit, the external lead terminal is easily deformed by the external force, and the adjacent external lead terminal is deformed. However, there has been a problem in that a short circuit may occur due to contact, and the external lead terminal cannot be accurately and firmly connected to a predetermined external electric circuit. There is also a demand for accommodating a plurality of semiconductor elements in one semiconductor device, thereby increasing the mounting density of the semiconductor elements on an external electric circuit board and increasing the speed of signal transmission and reception between the semiconductor elements. Was.
【0006】そこで、上記問題点を解消するとともに上
記要求を満足させるために、図9に断面図で示すよう
に、酸化アルミニウム質焼結体等の電気絶縁材料から成
り、上面中央部に半導体素子23aが搭載される半導体素
子搭載部21aを、下面中央部に半導体素子23bが収容さ
れる凹部21bを有するとともに、これらの半導体素子搭
載部21a周辺および凹部21b内から上面外周部にかけて
扇状に広がって導出するタングステンやモリブデン等の
金属粉末メタライズから成る複数の配線導体24を有する
略四角平板状の絶縁基体21と、この絶縁基体21の半導体
素子搭載部21aに搭載され、その電極が配線導体24の内
端部にボンディングワイヤ25aを介して電気的に接続さ
れた半導体素子23aと、凹部21b内に収容され、その電
極が配線導体24にボンディングワイヤ25bを介して電気
的に接続された半導体素子23bと、一端部が配線導体24
の絶縁基体21の上面の外周部に導出した部位に接合され
るとともに他端部が絶縁基体21の側面から外側に突出す
る複数個の外部リード端子22と、絶縁基体21および半導
体素子23a・23bならびに外部リード端子22の一端部を
封止するエポキシ樹脂等の熱硬化性樹脂から成る封止樹
脂26とから成る半導体装置が提案されている。かかる半
導体装置によれば、外部リード端子22が扇状に広がった
配線導体24の外端部に取着されていることから、外部リ
ード端子22の線幅および隣接間隔を広いものとして外部
リード端子22の変形を有効に防止しつつ隣接する外部リ
ード端子22間の電気的絶縁を維持することが可能とな
る。また、同一の半導体装置内に2個の半導体素子23a
・23bが近接して収容されていることから、半導体素子
23a・23bの外部電気回路基板に対する実装密度が高い
ものとなるとともに、半導体素子23aと23bとの間の信
号の授受を短い距離で高速に行うことが可能となる。Therefore, in order to solve the above-mentioned problems and to satisfy the above-mentioned requirements, as shown in a sectional view of FIG. 9, an electrically insulating material such as an aluminum oxide sintered body is used. The semiconductor element mounting part 21a on which the semiconductor element 23a is mounted has a concave part 21b in the center of the lower surface in which the semiconductor element 23b is accommodated, and fan-likely spreads from the periphery of the semiconductor element mounting part 21a and the inside of the concave part 21b to the peripheral part of the upper surface. A substantially rectangular plate-shaped insulating base 21 having a plurality of wiring conductors 24 made of metal powder such as tungsten or molybdenum to be derived, and a semiconductor element mounting portion 21a of the insulating base 21, and its electrodes A semiconductor element 23a electrically connected to the inner end via a bonding wire 25a and a semiconductor element 23a housed in the recess 21b, and its electrode is bonded to the wiring conductor 24. A semiconductor element 23b which is electrically connected via the ear 25b, one end wiring conductor 24
A plurality of external lead terminals 22 which are joined to a portion of the upper surface of the insulating base 21 extending to the outer peripheral portion and the other end of which protrudes outward from a side surface of the insulating base 21; the insulating base 21 and the semiconductor elements 23a and 23b. A semiconductor device comprising a sealing resin 26 made of a thermosetting resin such as an epoxy resin for sealing one end of the external lead terminal 22 has been proposed. According to such a semiconductor device, since the external lead terminal 22 is attached to the outer end portion of the fan-shaped spread wiring conductor 24, the external lead terminal 22 has a large line width and a large adjacent space. It is possible to maintain electrical insulation between adjacent external lead terminals 22 while effectively preventing deformation of the external lead terminals 22. Also, two semiconductor elements 23a are provided in the same semiconductor device.
.Since 23b is housed close to the semiconductor element
The packing density of the external electric circuit boards 23a and 23b is increased, and the transmission and reception of signals between the semiconductor elements 23a and 23b can be performed at a high speed over a short distance.
【0007】かかる半導体装置を製造するには、まず絶
縁基体21の下面に形成された凹部21b内に半導体素子23
bを収容するとともに、この半導体素子23bの各電極と
配線導体24とをボンディングワイヤ25bを介して電気的
に接続し、次に絶縁基体21の上面側に形成された半導体
素子搭載部21aに半導体素子23aを搭載するとともに、
この半導体素子23aの各電極と配線導体24とをボンディ
ングワイヤ25aを介して電気的に接続し、しかる後、こ
れを図10に断面図で示すように、下面側に封止樹脂26の
上半分の表面形状に対応した形状のキャビティー51aを
有する上金型51と、上面側に封止樹脂26の下半分の表面
形状に対応した形状のキャビティー52aを有する下金型
52とから成るモールド金型50内に、絶縁基体21および半
導体素子23a・23bならびに外部リード端子22の一端部
がモールド金型50のキャビティー51a・52a内に位置す
るようにして外部リード端子22を上金型51と下金型52と
の間に挟持させることによってセットし、次に図11に断
面図で示すように、このモールド金型50のキャビティー
51a・52a内に封止樹脂26を液状で注入して熱硬化させ
ることによって、絶縁基体21および半導体素子23a・23
bならびに外部リード端子22の一端部を熱硬化した封止
樹脂26により封止する方法が採用されている。To manufacture such a semiconductor device, first, a semiconductor element 23 is placed in a concave portion 21b formed on the lower surface of the insulating base 21.
b, and each electrode of the semiconductor element 23b is electrically connected to the wiring conductor 24 via a bonding wire 25b. Then, the semiconductor element is mounted on the semiconductor element mounting portion 21a formed on the upper surface side of the insulating base 21. With the element 23a mounted,
Each electrode of the semiconductor element 23a is electrically connected to the wiring conductor 24 via a bonding wire 25a. Thereafter, as shown in a sectional view of FIG. An upper mold 51 having a cavity 51a having a shape corresponding to the surface shape of the above, and a lower mold having a cavity 52a having a shape corresponding to the surface shape of the lower half of the sealing resin 26 on the upper surface side.
52, the insulating base 21 and the semiconductor elements 23a and 23b, and one end of the external lead terminal 22 are positioned in the cavities 51a and 52a of the mold 50. Is set by sandwiching it between an upper mold 51 and a lower mold 52, and then, as shown in a sectional view in FIG.
By injecting the sealing resin 26 in a liquid state into the insides 51a and 52a and thermally curing the same, the insulating base 21 and the semiconductor elements 23a and 23
b and one end of the external lead terminal 22 are sealed with a thermosetting sealing resin 26.
【0008】なお、モールド金型50のキャビティー51a
・52a内に封止樹脂26を液状で注入するには、モールド
金型50の上金型51と下金型52との間に、樹脂を注入する
ための樹脂注入路53および空気を排出するための空気排
出路54を設けておき、この樹脂注入路53を介してモール
ド金型50内に液状の封止樹脂26を注入する方法が採用さ
れる。The cavity 51a of the mold 50 is
In order to inject the sealing resin 26 into the liquid 52a in a liquid state, the resin injection path 53 for injecting the resin and the air are discharged between the upper mold 51 and the lower mold 52 of the mold 50. A method of injecting the liquid sealing resin 26 into the mold 50 through the resin injection path 53 is provided.
【0009】また、この半導体装置において、絶縁基体
21の下面側に搭載された半導体素子23bが凹部21b内に
収容されているのは、絶縁基体21上面の半導体素子搭載
部21aに半導体素子23aを搭載する際に、半導体素子23
bおよびボンディングワイヤ25bが外部の部材等に接触
して損傷することを防止するためである。In this semiconductor device, the insulating substrate
The reason why the semiconductor element 23b mounted on the lower surface side of the semiconductor device 21 is accommodated in the recess 21b is that the semiconductor element 23a is mounted on the semiconductor element mounting portion 21a on the upper surface of the insulating base 21.
This is to prevent the b and the bonding wire 25b from being damaged by contacting an external member or the like.
【0010】[0010]
【発明が解決しようとする課題】しかしながら、図9に
示すような従来の半導体装置では、絶縁基体21の下面に
形成された凹部21bの側面が凹部21bの底面に対して略
垂直に切立っており、このため凹部21bの底面と側面と
の間の角部に応力が集中しやすい構造となっている。し
たがって、半導体素子23a・23bが作動時に発生する熱
等が絶縁基体21および封止樹脂26に繰り返し印加される
と、両者の熱膨張係数の相違に起因して発生する応力が
絶縁基体21の凹部21bの側面と底面との間の角部に集中
して作用し、この角部を起点にして絶縁基体21にクラッ
クを発生させてしまい、その結果、絶縁基体21に被着さ
せた配線導体24がクラックの進行に伴って断線して半導
体素子23a・23bを正常に作動させることができなくな
ってしまうという問題点を有していた。However, in the conventional semiconductor device as shown in FIG. 9, the side surface of the concave portion 21b formed on the lower surface of the insulating base 21 rises substantially perpendicularly to the bottom surface of the concave portion 21b. Therefore, the structure is such that stress is easily concentrated on the corner between the bottom surface and the side surface of the concave portion 21b. Therefore, when heat or the like generated during the operation of the semiconductor elements 23a and 23b is repeatedly applied to the insulating base 21 and the sealing resin 26, the stress generated due to the difference in the coefficient of thermal expansion between the insulating base 21 and the sealing resin 26 is reduced. Acting intensively at the corner between the side surface and the bottom surface of 21b, cracks are generated in the insulating base 21 starting from this corner, and as a result, the wiring conductor 24 attached to the insulating base 21 However, there is a problem that the semiconductor elements 23a and 23b cannot be normally operated due to disconnection as the crack progresses.
【0011】また、この半導体装置においては、半導体
装置を製造する際に、半導体素子23a・23bおよび外部
リード端子22が接合された絶縁基体21をモールド金型50
内にセットした後、モールド金型50内に封止樹脂26を液
状で注入すると、凹部21bの側面が絶縁基体21の下面か
ら凹部21b底面まで略垂直に切立っていることから凹部
21bの側面と凹部21bの底面との間の角部に液状の封止
樹脂26が良好に回り込めずに、この部位における封止樹
脂26内に空気が巻き込まれて大きなボイドが形成され、
このようなボイドが発生すると、半導体素子23a・23b
が作動時に発生する熱等により、ボイド内に閉じ込めら
れた空気等が熱膨張して封止樹脂26に剥離や破裂を発生
させてしまい、その結果、封止樹脂26による気密封止が
不完全となって凹部21b内に収容する半導体素子23bを
長期間にわたり正常に作動させることができなくなって
しまうという問題点を有していた。In this semiconductor device, when the semiconductor device is manufactured, the insulating base 21 to which the semiconductor elements 23a and 23b and the external lead terminals 22 are joined is molded with a molding die 50.
When the sealing resin 26 is injected in a liquid state into the mold 50 after being set in the mold 50, the side surface of the concave portion 21b rises substantially vertically from the lower surface of the insulating base 21 to the bottom surface of the concave portion 21b.
The liquid sealing resin 26 does not satisfactorily wrap around the corner between the side surface 21b and the bottom surface of the concave portion 21b, and air is caught in the sealing resin 26 at this portion to form a large void,
When such voids are generated, the semiconductor elements 23a and 23b
The air and the like trapped in the voids thermally expand due to the heat and the like generated during the operation, causing the sealing resin 26 to peel or rupture. As a result, the hermetic sealing by the sealing resin 26 is incomplete. As a result, the semiconductor element 23b housed in the recess 21b cannot be operated normally for a long period of time.
【0012】本発明は、かかる従来の問題点に鑑み案出
されたものであり、その目的は、絶縁基体にクラックが
発生したり、あるいは封止樹脂に剥離や破裂が発生する
ことがなく、それにより内部に封止される半導体素子を
長期間にわたり、正常かつ安定に作動させることが可能
な半導体装置およびその製造方法を提供することにあ
る。The present invention has been devised in view of such conventional problems, and has as its object to prevent the occurrence of cracks in the insulating base or peeling or bursting of the sealing resin. Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which enable a semiconductor element sealed therein to operate normally and stably for a long period of time.
【0013】[0013]
【課題を解決するための手段】本発明の半導体装置は、
一方の主面に半導体素子を収容するための凹部を有する
とともに、凹部の内側から主面の外周部にかけて複数の
配線導体が配設されて成る略四角平板状の絶縁基体と、
凹部の底面に搭載された半導体素子と、一端部が配線導
体の主面の外周部に導出した部位に接合され、他端部が
絶縁基体の側面から外側に突出した複数の外部リード端
子と、絶縁基体および半導体素子ならびに外部リード端
子の一端部を封止する封止樹脂とから成る半導体装置で
あって、凹部は、その側面を傾斜面または階段状面とし
てあることを特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
A substantially square plate-shaped insulating base having a concave portion for accommodating the semiconductor element on one main surface, and a plurality of wiring conductors arranged from the inside of the concave portion to the outer peripheral portion of the main surface;
A semiconductor element mounted on the bottom surface of the concave portion, and a plurality of external lead terminals, one end of which is joined to a portion led out to the outer peripheral portion of the main surface of the wiring conductor, and the other end of which protrudes outward from a side surface of the insulating base; A semiconductor device comprising an insulating base, a semiconductor element, and a sealing resin for sealing one end of an external lead terminal, wherein the recess has a side surface formed as an inclined surface or a stepped surface. .
【0014】また、本発明の半導体装置の製造方法は、
一方の主面に半導体素子を収容するための凹部を有する
とともに、凹部の内側から主面の外周部にかけて複数の
配線導体が配設されて成る略四角平板状の絶縁基体と、
凹部の底面に搭載された半導体素子と、一端部が配線導
体の主面の外周部に導出した部位に接合され、他端部が
絶縁基体の側面から外側に突出した複数の外部リード端
子とを、絶縁基体の両主面側にキャビティーを有するモ
ールド金型内にセットするとともに、モールド金型内に
液状樹脂を注入して硬化させることによって、絶縁基体
および半導体素子ならびに外部リード端子の一端部を封
止樹脂により封止する半導体装置の製造方法であって、
絶縁基体の凹部の側面を傾斜面または階段状面としてお
くことを特徴とするものである。Further, a method of manufacturing a semiconductor device according to the present invention
A substantially square plate-shaped insulating base having a concave portion for accommodating the semiconductor element on one main surface, and a plurality of wiring conductors arranged from the inside of the concave portion to the outer peripheral portion of the main surface;
A semiconductor element mounted on the bottom surface of the concave portion, and a plurality of external lead terminals each having one end joined to a portion led out to the outer peripheral portion of the main surface of the wiring conductor and the other end projecting outward from a side surface of the insulating base. One end of the insulating base, the semiconductor element, and the external lead terminals are set by setting the mold in a mold having cavities on both main surface sides of the insulating base and injecting and curing a liquid resin in the mold. A method for manufacturing a semiconductor device in which is sealed with a sealing resin,
The side surface of the concave portion of the insulating base may be an inclined surface or a stepped surface.
【0015】本発明の半導体装置によれば、凹部の側面
が傾斜面または階段状面であることから、絶縁基体の凹
部側面と底面との間の角部に印加される応力を凹部側面
で良好に分散緩和させることができる。According to the semiconductor device of the present invention, since the side surface of the concave portion is an inclined surface or a stepped surface, the stress applied to the corner between the side surface and the bottom surface of the concave portion of the insulating substrate is favorably applied to the side surface of the concave portion. Can be alleviated.
【0016】また、本発明の半導体装置の製造方法によ
れば、絶縁基体の凹部の側面を傾斜面または階段状面と
しておくことによって、この絶縁基体をモールド金型内
にセットした後、モールド金型内に液状の封止樹脂を注
入すると、液状の封止樹脂が凹部の側面に沿って良好に
流れ、その結果、凹部内が封止樹脂により良好に充填さ
れ、封止樹脂内に大きなボイドが形成されることを有効
に防止することができる。Further, according to the method of manufacturing a semiconductor device of the present invention, by setting the side surface of the concave portion of the insulating substrate to be an inclined surface or a stepped surface, the insulating substrate is set in a mold, and then the mold metal is set. When the liquid sealing resin is injected into the mold, the liquid sealing resin flows well along the side surface of the concave portion. As a result, the inside of the concave portion is well filled with the sealing resin, and a large void is formed in the sealing resin. Can be effectively prevented from being formed.
【0017】[0017]
【発明の実施の形態】次に、本発明を添付の図面を基に
詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings.
【0018】図1は、本発明の半導体装置の実施形態の
一例を示す断面図であり、1は絶縁基体、2は外部リー
ド端子、3a・3bは半導体素子、6は封止樹脂であ
る。また、図2は図1に示す半導体装置の封止樹脂6を
除いた上面図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, wherein 1 is an insulating base, 2 is an external lead terminal, 3a and 3b are semiconductor elements, and 6 is a sealing resin. FIG. 2 is a top view of the semiconductor device shown in FIG. 1 excluding the sealing resin 6.
【0019】絶縁基体1は、酸化アルミニウム質焼結体
・窒化アルミニウム質焼結体・ムライト質焼結体・炭化
珪素質焼結体・窒化珪素質焼結体・ガラスセラミックス
等の電気絶縁材料から成る略四角平板であり、その上面
中央部に半導体素子3aが搭載される半導体素子搭載部
1aを有しており、その下面中央部に半導体素子3bが
収容される凹部1bを有している。そして、半導体素子
搭載部1aには半導体素子3aが、凹部1bの底面には
半導体素子1bが、ろう材・ガラス・樹脂等の接着剤を
介してそれぞれ接着固定されている。The insulating substrate 1 is made of an electrically insulating material such as a sintered body of aluminum oxide, a sintered body of aluminum nitride, a sintered body of mullite, a sintered body of silicon carbide, a sintered body of silicon nitride, and glass ceramic. Having a semiconductor element mounting portion 1a in which the semiconductor element 3a is mounted in the center of the upper surface, and a concave portion 1b in which the semiconductor element 3b is accommodated in the center of the lower surface. The semiconductor element 3a is fixed to the semiconductor element mounting portion 1a, and the semiconductor element 1b is fixed to the bottom surface of the concave portion 1b via an adhesive such as brazing material, glass, resin, or the like.
【0020】また、絶縁基体1は、半導体素子搭載部1
a周辺および凹部1bの内側から外周部にかけて扇状に
広がる多数のタングステン・モリブデン・銅・銀等の金
属粉末メタライズから成る配線導体4が被着形成されて
いる。この配線導体4は、半導体素子3a・3bの各電
極を外部リード端子2に電気的に接続するための導電路
として機能し、その内端部には半導体素子3a・3bの
各電極がボンディングワイヤ5a・5bを介してそれぞ
れ電気的に接続されており、外端部には外部リード端子
2の一端部が接合されている。そして、配線導体4は、
内端部から外端部にかけて扇状に広がっており、外端部
における線幅および隣接間隔が広いものとなっており、
これにより、外端部に接合される外部リード端子2の線
幅および隣接間隔を広いものとすることができる。The insulating substrate 1 is provided with a semiconductor element mounting portion 1.
A large number of wiring conductors 4 made of metal powders of metal such as tungsten, molybdenum, copper, silver, etc., spreading in a fan shape from the periphery of a and the inside of the concave portion 1b to the outer peripheral portion are formed. The wiring conductor 4 functions as a conductive path for electrically connecting the respective electrodes of the semiconductor elements 3a and 3b to the external lead terminals 2, and the inner ends of the respective electrodes of the semiconductor elements 3a and 3b are provided with bonding wires. These are electrically connected via 5a and 5b, respectively, and one end of the external lead terminal 2 is joined to the outer end. And the wiring conductor 4
It spreads like a fan from the inner end to the outer end, and the line width and the adjacent interval at the outer end are wide,
Thereby, the line width and the adjacent distance of the external lead terminal 2 joined to the outer end can be widened.
【0021】配線導体4に接合された外部リード端子2
は、半導体素子3a・3bを外部電気回路に接続するた
めの端子であり、外部リード端子2を外部電気回路基板
の配線導体に接続することによって半導体素子3a・3
bが配線導体4および外部リード端子2を介して外部電
気回路に電気的に接続されることとなる。そして、外部
リード端子2は、その線幅および隣接間隔が例えば0.3
mmを超える広いものとなっており、そのため外部リー
ド端子2に外力が印加されたとしてもこの外部リード端
子2に大きな変形を発生させることはなく、隣接する外
部リード端子2間の電気的絶縁を維持しつつ外部リード
端子2を所定の外部電気回路に正確かつ確実に電気的に
接続することができる。External lead terminal 2 joined to wiring conductor 4
Is a terminal for connecting the semiconductor elements 3a and 3b to an external electric circuit. The semiconductor elements 3a and 3b are connected by connecting the external lead terminals 2 to the wiring conductors of the external electric circuit board.
b is electrically connected to an external electric circuit via the wiring conductor 4 and the external lead terminal 2. The external lead terminal 2 has a line width and an adjacent interval of, for example, 0.3.
mm, so that even if an external force is applied to the external lead terminals 2, the external lead terminals 2 will not be greatly deformed, and the electrical insulation between the adjacent external lead terminals 2 will be reduced. The external lead terminals 2 can be accurately and reliably electrically connected to a predetermined external electric circuit while maintaining them.
【0022】また、絶縁基体1および半導体素子3a・
3bならびに外部リード端子2の配線導体4に接合され
た一端部は、エポキシ樹脂等の封止樹脂6により封止さ
れており、これにより半導体素子3a・3bが気密に封
止され、外部環境から保護されている。そして、この例
においては、絶縁基体1の凹部1bの側面が傾斜面とな
っている。これにより、絶縁基体1と封止樹脂6との熱
膨張係数の相違に起因して発生する熱応力が絶縁基体1
の凹部1bの内面側に繰り返し印加されたとしても、そ
の応力は傾斜面となっている凹部1bの側面で良好に分
散緩和され、その結果、絶縁基体1にクラックが発生す
ることを有効に防止することができ、配線導体4に断線
を来すことなく半導体素子3a・3bを常に正常に作動
させることが可能となる。The insulating base 1 and the semiconductor elements 3a.
3b and one end of the external lead terminal 2 joined to the wiring conductor 4 are sealed with a sealing resin 6 such as an epoxy resin, so that the semiconductor elements 3a and 3b are air-tightly sealed, and from the external environment. Is protected. In this example, the side surface of the concave portion 1b of the insulating base 1 is an inclined surface. As a result, thermal stress generated due to a difference in thermal expansion coefficient between the insulating base 1 and the sealing resin 6 is reduced.
Even if the stress is repeatedly applied to the inner surface side of the concave portion 1b, the stress is satisfactorily dispersed and alleviated on the side surface of the concave portion 1b which is an inclined surface, and as a result, cracks are effectively prevented from being generated in the insulating base 1. It is possible to always operate the semiconductor elements 3a and 3b normally without breaking the wiring conductor 4.
【0023】なお、凹部1bの側面は、その傾斜角Aが
10゜未満であると、凹部1bとして必要な深さを得るた
めに絶縁基体1の大きさを極めて大きなものとする必要
があり、そのため半導体装置の小型化が困難なものとな
り、他方、80゜を超えると、凹部の側面と底面との間の
角部に印加される応力を良好に分散緩和することが困難
となってしまう。したがって、凹部1bの側面の傾斜角
Aは、10〜80゜の範囲が好ましい。The side surface of the concave portion 1b has an inclination angle A.
If it is less than 10 °, it is necessary to make the size of the insulating base 1 extremely large in order to obtain the required depth as the concave portion 1b, which makes it difficult to reduce the size of the semiconductor device. When it exceeds, it becomes difficult to satisfactorily disperse and relax the stress applied to the corner between the side surface and the bottom surface of the concave portion. Therefore, the inclination angle A of the side surface of the recess 1b is preferably in the range of 10 to 80 °.
【0024】さらに、絶縁基体1の外周側面と下面との
間の角部に、例えば幅が0.1mm以上で絶縁基体1の外
周側面に対する角度が10〜80゜の面取り部1cを形成し
ておくと、この角部に接する封止樹脂6に絶縁基体1と
封止樹脂6との熱膨張係数の相違に起因して印加される
応力を良好に分散緩和することができるとともに、この
角部と封止樹脂6の側面との間の厚みを厚いものとし
て、封止樹脂6にクラックが発生するのを有効に防止す
ることができる。したがって、絶縁基体1の外周側面と
下面との間の角部には幅が0.1mm以上で絶縁基体1の
外周側面に対する角度が10〜80゜の面取り部1cを形成
しておくことが好ましい。Further, a chamfered portion 1c having a width of, for example, 0.1 mm or more and an angle of 10 to 80 ° with respect to the outer peripheral side surface of the insulating substrate 1 is formed at a corner between the outer peripheral side surface and the lower surface of the insulating substrate 1. In addition, the stress applied to the sealing resin 6 in contact with the corner due to the difference in thermal expansion coefficient between the insulating base 1 and the sealing resin 6 can be satisfactorily dispersed and relaxed. By making the thickness between the side surfaces of the sealing resin 6 large, cracks in the sealing resin 6 can be effectively prevented. Therefore, it is preferable to form a chamfered portion 1c having a width of 0.1 mm or more and an angle of 10 to 80 ° with respect to the outer peripheral side surface of the insulating substrate 1 at the corner between the outer peripheral side surface and the lower surface of the insulating substrate 1.
【0025】また、図3に本発明の半導体装置の実施形
態の他の例を示す。図3に示す例では、上述の例と同様
に、酸化アルミニウム質焼結体等の電気絶縁材料から成
り、上面中央部に半導体素子13aが搭載される半導体素
子搭載部11aを、下面中央部に半導体素子13bが収容さ
れる凹部11bを有するとともに、これらの半導体素子搭
載部11a周辺および凹部11bの内側から上面の外周部に
かけて扇状に広がって導出するタングステンやモリブデ
ン等の金属粉末メタライズから成る複数の配線導体14を
有する略四角平板状の絶縁基体11と、この絶縁基体11の
半導体素子搭載部11aに搭載され、その電極が配線導体
14の内端部にボンディングワイヤ15aを介して電気的に
接続された半導体素子13aと、凹部11b内に収容され、
その電極が配線導体14にボンディングワイヤ15bを介し
て電気的に接続された半導体素子13bと、一端部が配線
導体14の絶縁基体11の上面外周部に導出した部位に接合
されるとともに他端部が絶縁基体11の側面から外側に突
出する複数個の外部リード端子12と、絶縁基体11および
半導体素子13a・13bならびに外部リード端子12の一端
部を封止するエポキシ樹脂等の熱硬化性樹脂から成る封
止樹脂16とから構成されている。そして、この例におい
ては絶縁基体11の凹部11bの側面が階段状面となってい
る。この例の場合には、凹部11bの側面が階段状面とな
っていることにより、絶縁基体11と封止樹脂16の熱膨張
係数の相違に起因して発生する熱応力が絶縁基体11の凹
部11bの内面側に繰り返し印加されたとしても、その応
力は階段状面となっている凹部11bの側面で良好に分散
緩和され、その結果、絶縁基体11にクラックが発生する
ことを有効に防止することができ、配線導体14に断線を
来すことなく半導体素子13a・13bを常に正常に作動さ
せることが可能となる。FIG. 3 shows another embodiment of the semiconductor device according to the present invention. In the example shown in FIG. 3, similarly to the above-described example, a semiconductor element mounting portion 11a made of an electrically insulating material such as an aluminum oxide sintered body and having a semiconductor element 13a mounted on a central portion of the upper surface and a central portion of the lower surface is formed on the lower surface. A plurality of metal powders, such as tungsten and molybdenum, having a concave portion 11b for accommodating the semiconductor element 13b and extending in a fan shape from the periphery of the semiconductor element mounting portion 11a and from the inside of the concave portion 11b to the outer peripheral portion of the upper surface. A substantially rectangular flat insulating substrate 11 having a wiring conductor 14 and a semiconductor element mounting portion 11a of the insulating substrate 11
A semiconductor element 13a electrically connected to an inner end portion of the 14 through a bonding wire 15a, and a semiconductor element 13a housed in the recess 11b;
A semiconductor element 13b whose electrode is electrically connected to the wiring conductor 14 via a bonding wire 15b, and one end is joined to a portion of the wiring conductor 14 which is led to the outer periphery of the upper surface of the insulating base 11 and the other end is connected. A plurality of external lead terminals 12 projecting outward from the side surfaces of the insulating base 11, and a thermosetting resin such as an epoxy resin sealing one end of the insulating base 11, the semiconductor elements 13a and 13b, and the external lead terminals 12. And a sealing resin 16. In this example, the side surface of the concave portion 11b of the insulating base 11 is a stepped surface. In the case of this example, since the side surface of the concave portion 11b is a stepped surface, the thermal stress generated due to the difference in thermal expansion coefficient between the insulating base 11 and the sealing resin 16 causes the concave portion of the insulating base 11 Even if the stress is repeatedly applied to the inner surface side of 11b, the stress is satisfactorily dispersed and alleviated on the side surface of the concave portion 11b having the stepped surface, and as a result, cracks are effectively prevented from being generated in the insulating base 11. Therefore, the semiconductor elements 13a and 13b can always be normally operated without breaking the wiring conductor 14.
【0026】なお、凹部11bの側面は、各段の高さが0.
5mmを超えると、この側面で応力を良好に分散緩和す
ることが困難となる傾向にある。従って、凹部11bの各
段の高さは、0.5mm以下であるとこが好ましい。ま
た、凹部11bの側面は、その傾斜角Aが10゜未満である
と、凹部11bとして必要な深さを得るために絶縁基体11
の大きさを極めて大きなものとする必要があり、そのた
め半導体装置の小型化が困難なものとなり、他方、80゜
を超えると、凹部の側面と底面との間の角部に印加され
る応力を良好に分散緩和することが困難となってしま
う。したがって、凹部11bの側面の傾斜角Aは、10〜80
゜の範囲が好ましい。The side surface of the recess 11b has a height of each step of 0.
If it exceeds 5 mm, it tends to be difficult to satisfactorily disperse and relax the stress on this side. Therefore, the height of each step of the recess 11b is preferably 0.5 mm or less. When the inclination angle A is less than 10 °, the side surface of the concave portion 11b is formed on the insulating base 11 to obtain a necessary depth as the concave portion 11b.
Needs to be extremely large, which makes it difficult to reduce the size of the semiconductor device. On the other hand, if it exceeds 80 °, the stress applied to the corner between the side surface and the bottom surface of the concave portion is reduced. It becomes difficult to favorably mitigate the dispersion. Therefore, the inclination angle A of the side surface of the concave portion 11b is 10 to 80.
The range of ゜ is preferred.
【0027】さらに、絶縁基体11の外周側面と下面との
間の角部に、例えば幅が0.1mm以上で絶縁基体11の外
周側面に対する角度が10〜80゜の面取り部11cを形成し
ておくと、この角部に接する封止樹脂16に絶縁基体11と
封止樹脂16との熱膨張係数の相違に起因して印加される
応力を良好に分散緩和することができるとともに、この
角部と封止樹脂16の側面との間の厚みを厚いものとし
て、封止樹脂16にクラックが発生するのを有効に防止す
ることができる。したがって、絶縁基体11の外周側面と
下面との間の角部には幅が0.1mm以上で絶縁基体11の
外周側面に対する角度が10〜80゜の面取り部11cを形成
しておくことが好ましい。Further, a chamfered portion 11c having a width of, for example, 0.1 mm or more and an angle of 10 to 80 ° with respect to the outer peripheral side surface of the insulating substrate 11 is formed at a corner between the outer peripheral side surface and the lower surface of the insulating substrate 11. The stress applied to the sealing resin 16 in contact with the corners due to the difference in the thermal expansion coefficient between the insulating base 11 and the sealing resin 16 can be satisfactorily dispersed and relaxed. By making the thickness between the side surfaces of the sealing resin 16 large, cracks in the sealing resin 16 can be effectively prevented. Therefore, it is preferable to form a chamfered portion 11c having a width of 0.1 mm or more and an angle of 10 to 80 ° with respect to the outer peripheral side surface of the insulating substrate 11 at the corner between the outer peripheral side surface and the lower surface of the insulating substrate 11.
【0028】次に、本発明の半導体装置の製造方法を上
述の図1に示す半導体装置を製造する場合を例にとって
説明する。Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to an example of manufacturing the semiconductor device shown in FIG.
【0029】先ず、図4に断面図で示すように、絶縁基
体1と外部リード端子2と半導体素子3a・3bとを準
備する。First, as shown in the sectional view of FIG. 4, an insulating base 1, external lead terminals 2, and semiconductor elements 3a and 3b are prepared.
【0030】絶縁基体1は、例えば酸化アルミニウム質
焼結体から成る場合には、酸化アルミニウム・酸化珪素
・酸化カルシウム・酸化マグネシウム等の原料粉末に適
当なバインダ・溶剤を添加混合して泥漿状となすととも
に、これを従来周知のドクターブレード法やカレンダー
ロール法等のシート成形技術を採用してシート状となす
ことによって絶縁基体1用の複数枚のセラミックグリー
ンシートを得、しかる後、これらのセラミックグリーン
シートに適当な打ち抜き加工を施すとともに、配線導体
4用の金属ペーストを従来周知のスクリーン印刷法等の
厚膜手法を採用して所定のパターンに印刷塗布し、次に
これらのセラミックグリーンシートを上下に積層すると
ともに所定の形状に切断して側面が傾斜面となった凹部
を下面に有する生セラミック成形体を得、最後にこの生
セラミック成形体を還元雰囲気中、約1600℃の温度で焼
成することによって製作される。なお、配線導体4用の
金属ペーストは、例えば配線導体がタングステンメタラ
イズから成る場合であれば、タングステン粉末に適当な
バインダ・溶剤を添加混合してペースト状とすることに
よって得られる。また、通常であれば、配線導体4の露
出表面には、ニッケルや金等の耐蝕性に優れ、かつワイ
ヤーボンディング性やろう材との濡れ性に優れる金属を
電解めっき法や無電解めっき法により1〜20μmの厚み
に鍍着させておく。When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, an appropriate binder and a solvent are added to a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide, and the mixture is mixed to form a slurry. In addition, a plurality of ceramic green sheets for the insulating substrate 1 are obtained by adopting a sheet forming technique such as a doctor blade method or a calender roll method, which is well known in the art, to obtain a plurality of ceramic green sheets. The green sheet is appropriately punched, and a metal paste for the wiring conductor 4 is printed and applied in a predetermined pattern by using a conventionally known thick film technique such as a screen printing method. It has a concave part on the lower surface, which is vertically stacked and cut into a predetermined shape, and the side surface becomes an inclined surface. Give the ceramic molded body, finally in a reducing atmosphere the green ceramic body is fabricated by firing at a temperature of about 1600 ° C.. The metal paste for the wiring conductor 4 can be obtained, for example, when the wiring conductor is made of tungsten metallization, by adding and mixing a suitable binder and solvent to tungsten powder to form a paste. Usually, a metal having excellent corrosion resistance, such as nickel or gold, and having excellent wire bonding properties and wettability with a brazing material is formed on the exposed surface of the wiring conductor 4 by electrolytic plating or electroless plating. It is plated to a thickness of 1 to 20 μm.
【0031】他方、外部リード端子2は銅を主成分とす
る銅系合金や鉄を主成分とする鉄系合金等の金属から成
る薄板に適当な打ち抜き加工やエッチング加工を施すこ
とによって所定の形状に製作される。なお、このような
外部リード端子2は、各外部リード端子2を所定の間隔
で保持するためにその外端部を各リード端子2と一体的
に形成された枠状の連結帯で連結させておくことが好ま
しい。このような連結帯は、外部リード端子2を外部電
気回路基板に接続する前に外部リード端子2から切断除
去すればよい。On the other hand, the external lead terminal 2 is formed into a predetermined shape by subjecting a thin plate made of a metal such as a copper alloy containing copper as a main component or an iron alloy containing iron as a main component to an appropriate punching process or etching process. It is produced in. In order to hold the external lead terminals 2 at a predetermined interval, the external ends of the external lead terminals 2 are connected by a frame-shaped connecting band integrally formed with the respective lead terminals 2. Preferably. Such a connecting band may be cut and removed from the external lead terminal 2 before connecting the external lead terminal 2 to the external electric circuit board.
【0032】また、半導体素子3a・3bは常法によっ
て製作される。The semiconductor elements 3a and 3b are manufactured by a conventional method.
【0033】次に、図5に断面図で示すように、配線導
体4の外端部に外部リード端子2の一端部を銀−銅合金
や金−錫合金・金−ゲルマニウム合金・銀−錫合金・鉛
−錫合金・金−錫−鉛−銀合金・金−錫−鉛−パラジウ
ム合金等のろう材を介して接合するとともに、半導体素
子搭載部1aに半導体素子3aを、凹部1bの底面に半
導体素子3bを、金−シリコン合金等のろう材やエポキ
シ樹脂等の樹脂から成る接着剤を介して接着固定し、こ
の半導体素子3a・3bの各電極をボンディングワイヤ
5a・5bを介して配線導体4に接続する。Next, as shown in the sectional view of FIG. 5, one end of the external lead terminal 2 is connected to the outer end of the wiring conductor 4 by a silver-copper alloy, a gold-tin alloy, a gold-germanium alloy, a silver-tin. The semiconductor element 3a is joined to the semiconductor element mounting portion 1a by the brazing material such as an alloy, lead-tin alloy, gold-tin-lead-silver alloy, gold-tin-lead-palladium alloy, and the bottom surface of the recess 1b. The semiconductor element 3b is bonded and fixed via an adhesive made of a brazing material such as a gold-silicon alloy or a resin such as an epoxy resin, and the respective electrodes of the semiconductor elements 3a and 3b are wired via bonding wires 5a and 5b. Connect to conductor 4.
【0034】そして最後に、図6に断面図で示すよう
に、半導体素子3a・3bおよび外部リード端子2が接
合された絶縁基体1を、下面側に封止樹脂6の上半分の
表面形状に対応した形状のキャビティー31aを有する上
金型31と上面側に封止樹脂6の下半分の表面形状に対応
した形状のキャビティー32aを有する下金型32とから成
るモールド金型30内にセットし、図7に断面図で示すよ
うに、このモールド金型30内にエポキシ樹脂等の封止樹
脂6を樹脂注入路33を介して液状で注入して熱硬化させ
ることによって、図1に示すように、絶縁基体1および
半導体素子3a・3bならびに外部リード端子2の一端
部が封止樹脂6によって封止された半導体装置が完成す
る。そしてこのとき、この例では絶縁基体1の凹部1b
の側面が例えば10゜〜80゜の傾斜面となっていることが
重要である。この例においては、絶縁基体1の凹部1b
の側面が例えば10〜80゜の傾斜面となっていることか
ら、モールド金型30内に絶縁基体1をセットするととも
に液状の封止樹脂6を注入すると、液状の封止樹脂6は
傾斜面となった凹部1bの側面に沿って良好に流れて凹
部1bの内部が封止樹脂6により隙間なく充填され、そ
の結果、封止樹脂6の内部に大きなボイドが形成される
ようなことはない。したがって、この例の製造方法によ
れば、ボイド内に封入された空気等が熱膨張して封止樹
脂6に剥離や破裂が発生することのない気密信頼性に優
れた半導体装置を提供することができる。なお、凹部1
bの側面の傾斜角Aが10゜未満の場合、凹部1bとして
必要な深さを得るために絶縁基体1の大きさを極めて大
きなものとする必要があり、そのため半導体装置の小型
化が困難なものとなり、他方、80゜を超えると、モール
ド金型30内に絶縁基体1をセットするとともに液状の封
止樹脂6を注入した際に、液状の樹脂6が凹部1bの側
面に沿って良好に流れずに凹部1bの内部を封止樹脂6
で隙間なく充填することが困難となる傾向にある。した
がって、凹部1bの側面の傾斜角Aは10〜80゜の範囲が
好ましい。さらに、絶縁基体1の外周側面と下面との間
の角部に、幅が0.1mm以下で、絶縁基体1の外周側面
との角度が10〜80゜の面取り部1cを形成しておくと、
絶縁基体1がセットされたモールド金型30内に液状の封
止樹脂6を注入した際に、絶縁基体1と下金型32のキャ
ビティー32a側面との間隔が広いものとなって絶縁基体
1下面と下金型32との間に液状の封止樹脂6を良好に注
入することができる。したがって、絶縁基体1の外周側
面と下面との間の角部には、幅が0.1mm以下で、絶縁
基体1の外周側面との角度が10〜80゜の面取り部1cを
形成しておくことが好ましい。Finally, as shown in the cross-sectional view of FIG. 6, the insulating substrate 1 to which the semiconductor elements 3a and 3b and the external lead terminals 2 are joined is formed on the lower surface into the surface shape of the upper half of the sealing resin 6. In a mold die 30 comprising an upper die 31 having a cavity 31a of a corresponding shape and a lower die 32 having a cavity 32a of a shape corresponding to the lower half surface shape of the sealing resin 6 on the upper surface side. As shown in a sectional view of FIG. 7, the sealing resin 6 such as an epoxy resin is injected into the molding die 30 in a liquid state through a resin injection path 33 and thermally cured, thereby obtaining As shown, a semiconductor device in which the insulating base 1, the semiconductor elements 3a and 3b, and one end of the external lead terminal 2 are sealed with the sealing resin 6 is completed. At this time, in this example, the concave portion 1b of the insulating base 1 is used.
It is important that the side surface is inclined at, for example, 10 ° to 80 °. In this example, the concave portion 1b of the insulating base 1
Is inclined, for example, at an angle of 10 to 80 °. Therefore, when the insulating base 1 is set in the mold 30 and the liquid sealing resin 6 is injected, the liquid sealing resin 6 is inclined. Flows well along the side surface of the concave portion 1b, and the inside of the concave portion 1b is filled with the sealing resin 6 without any gap. As a result, a large void is not formed inside the sealing resin 6. . Therefore, according to the manufacturing method of this example, it is possible to provide a semiconductor device having excellent hermetic reliability, in which air or the like sealed in the voids does not thermally expand and peeling or rupture occurs in the sealing resin 6. Can be. In addition, the concave portion 1
When the inclination angle A of the side surface of b is less than 10 °, it is necessary to make the size of the insulating substrate 1 extremely large in order to obtain the necessary depth as the concave portion 1b, which makes it difficult to miniaturize the semiconductor device. On the other hand, when the angle exceeds 80 °, when the insulating base 1 is set in the mold 30 and the liquid sealing resin 6 is injected, the liquid resin 6 is satisfactorily formed along the side surface of the concave portion 1b. The inside of the concave portion 1b does not flow and the sealing resin 6
Tend to be difficult to fill without gaps. Therefore, the inclination angle A of the side surface of the concave portion 1b is preferably in the range of 10 to 80 °. Further, if a chamfered portion 1c having a width of 0.1 mm or less and an angle of 10 to 80 ° with the outer peripheral side surface of the insulating substrate 1 is formed at a corner between the outer peripheral side surface and the lower surface of the insulating substrate 1,
When the liquid sealing resin 6 is injected into the molding die 30 on which the insulating base 1 is set, the distance between the insulating base 1 and the side surface of the cavity 32a of the lower die 32 becomes wide, so that the insulating base 1 The liquid sealing resin 6 can be favorably injected between the lower surface and the lower mold 32. Therefore, a chamfered portion 1c having a width of 0.1 mm or less and an angle of 10 to 80 ° with the outer peripheral side surface of the insulating substrate 1 is formed at a corner between the outer peripheral side surface and the lower surface of the insulating substrate 1. Is preferred.
【0035】また、図3に示す実施形態例を製造する場
合には、図8に断面図で示すように、半導体素子13a・
13bおよび外部リード端子12が接合された絶縁基体11
を、下面側に封止樹脂16の上半分の表面形状に対応した
形状のキャビティー41aを有する上金型41と上面側に封
止樹脂16の下半分の表面形状に対応した形状のキャビテ
ィー42aを有する下金型42とから成るモールド金型40内
にセットした後、このモールド金型40内にエポキシ樹脂
等の封止樹脂16を樹脂注入路43を介して液状で注入して
熱硬化させることによって、図3に示すように、絶縁基
体11および半導体素子13a・13bならびに外部リード端
子12の一端部が封止樹脂16によって封止された半導体装
置が完成する。この場合、絶縁基体11の凹部11bの側面
が例えば傾斜角Aが10〜80゜の階段状面となっているこ
とから、モールド金型40内に絶縁基体11をセットすると
ともに液状の封止樹脂16を注入すると、液状の封止樹脂
16は階段状面となった凹部11bの側面に沿って良好に流
れて凹部11b内が封止樹脂16により隙間なく充填され、
その結果、封止樹脂16の内部に大きなボイドが形成され
るようなことはない。なお、凹部11bの側面の傾斜角A
が10゜未満の場合、凹部11bとして必要な深さを得るた
めに絶縁基体11の大きさを極めて大きなものとする必要
があり、そのため半導体装置の小型化が困難なものとな
り、他方、80゜を超えると、モールド金型40内に絶縁基
体11をセットするとともに液状の封止樹脂16を注入した
際に、液状の樹脂16が凹部11bの側面に沿って良好に流
れずに凹部11b内を封止樹脂16で隙間なく充填すること
が困難となる傾向にある。したがって、凹部11bの側面
の傾斜角Aは10〜80゜の範囲が好ましい。When the embodiment shown in FIG. 3 is manufactured, as shown in the sectional view of FIG.
Insulating substrate 11 to which 13b and external lead terminals 12 are bonded
An upper mold 41 having a cavity 41a having a shape corresponding to the upper half surface shape of the sealing resin 16 on the lower surface side, and a cavity having a shape corresponding to the lower half surface shape of the sealing resin 16 on the upper surface side After setting in a mold 40 comprising a lower mold 42 having a 42a, a sealing resin 16 such as an epoxy resin is injected into the mold 40 in a liquid state through a resin injection path 43 and thermoset. By doing so, as shown in FIG. 3, a semiconductor device in which the insulating base 11, the semiconductor elements 13a and 13b, and one end of the external lead terminal 12 are sealed with the sealing resin 16 is completed. In this case, since the side surface of the concave portion 11b of the insulating base 11 is a stepped surface having an inclination angle A of, for example, 10 to 80 °, the insulating base 11 is set in the mold 40 and the liquid sealing resin is set. When 16 is injected, liquid sealing resin
16 flows well along the side surface of the concave portion 11b that has become a stepped surface, and the inside of the concave portion 11b is filled with the sealing resin 16 without gaps,
As a result, a large void is not formed inside the sealing resin 16. The inclination angle A of the side surface of the recess 11b
Is less than 10 °, it is necessary to make the size of the insulating base 11 extremely large in order to obtain a necessary depth for the concave portion 11b, which makes it difficult to reduce the size of the semiconductor device. Is exceeded, when the insulating base 11 is set in the mold 40 and the liquid sealing resin 16 is injected, the liquid resin 16 does not flow well along the side surface of the concave portion 11b and flows through the concave portion 11b. It tends to be difficult to fill the gap with the sealing resin 16 without gaps. Therefore, the inclination angle A of the side surface of the recess 11b is preferably in the range of 10 to 80 °.
【0036】なお、本発明は上述の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲で
あれば種々の変更は可能である。例えば、上述の実施形
態例では絶縁基体1・11は酸化アルミニウム質焼結体等
のセラミックスから形成されていたが、絶縁基体1・11
は、セラミックス以外の材料、例えば熱硬化性ポリイミ
ド樹脂やBTレジン(Bismaleimide Triazine Resi
n)・ガラスエポキシ樹脂基板・ガラス板等から形成さ
れていても良い。また、上述の実施形態例では、配線導
体4・14はタングステンメタライズ等の金属粉末メタラ
イズから形成されていたが、配線導体4・14は、銅やア
ルミニウム・金等の金属薄膜から形成されていてもよ
い。さらに、絶縁基体1・11の上面や内部に配線導体4
・14に接続された容量素子や抵抗素子等を配設してもよ
い。またさらに、上述の実施形態例では半導体素子3a
・3b・13a・13bは各電極がボンディングワイヤ5a
・5b・15a・15bを介して配線導体4・14に接続され
ていたが、半導体素子3a・3b・13a・13bの各電極
はフリップチップ接続により配線導体4・14に接続され
ていてもよい。Note that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the insulating bases 1 and 11 are formed from ceramics such as an aluminum oxide sintered body.
Are materials other than ceramics, such as thermosetting polyimide resin and BT resin (Bismaleimide Triazine Resi
n). It may be formed from a glass epoxy resin substrate, a glass plate, or the like. In the above embodiment, the wiring conductors 4 and 14 are formed from metal powder metallization such as tungsten metallization. However, the wiring conductors 4 and 14 are formed from metal thin films such as copper, aluminum and gold. Is also good. Further, the wiring conductor 4
A capacitance element, a resistance element, or the like connected to 14 may be provided. Furthermore, in the above embodiment, the semiconductor element 3a
・ 3b ・ 13a ・ 13b are bonding wires 5a
Although the electrodes of the semiconductor elements 3a, 3b, 13a, and 13b may be connected to the wiring conductors 4 and 14 by flip-chip connection, the electrodes are connected to the wiring conductors 4 and 14 via 5b, 15a, and 15b. .
【0037】[0037]
【発明の効果】本発明の半導体装置によれば、凹部の側
面が傾斜面または階段状面であることから、絶縁基体の
凹部の側面と底面との間の角部に印加される応力を凹部
の側面で良好に分散緩和させることができ、その結果、
絶縁基体にクラックが発生することがなく、配線導体に
断線を来すことなく半導体素子を常に正常に作動させる
ことが可能な半導体装置を提供することができる。According to the semiconductor device of the present invention, since the side surface of the concave portion is an inclined surface or a stepped surface, the stress applied to the corner between the side surface and the bottom surface of the concave portion of the insulating base is reduced. In the aspect of dispersion can be satisfactorily alleviated, as a result,
It is possible to provide a semiconductor device in which a semiconductor element can always be normally operated without causing cracks in an insulating base and without breaking a wiring conductor.
【0038】また、本発明の半導体装置の製造方法によ
れば、絶縁基体の凹部の側面を傾斜面または階段状面と
しておくことによって、この絶縁基体をモールド金型内
にセットした後、モールド金型内に液状の封止樹脂を注
入すると、液状の封止樹脂が凹部の側面に沿って良好に
流れ、その結果、凹部内が封止樹脂により良好に充填さ
れ、封止樹脂内に大きなボイドが形成されることを有効
に防止することができ、その結果、ボイド内に封入され
た空気等が熱膨張して封止樹脂に剥離や破裂が発生する
ことがなく、内部に収容する半導体素子を長期間にわた
り正常かつ安定に作動させることが可能な気密信頼性に
優れた半導体装置を提供することができる。Further, according to the method of manufacturing a semiconductor device of the present invention, by setting the side surface of the concave portion of the insulating base as an inclined surface or a stepped surface, the insulating base is set in a mold, and then the mold is set. When the liquid sealing resin is injected into the mold, the liquid sealing resin flows well along the side surface of the concave portion. As a result, the inside of the concave portion is well filled with the sealing resin, and a large void is formed in the sealing resin. Can be effectively prevented, and as a result, the air or the like sealed in the voids does not thermally expand and the sealing resin does not peel or burst, and the semiconductor element housed inside , Which can operate normally and stably over a long period of time, and has excellent airtight reliability.
【図1】本発明の半導体装置の実施の形態の一例を示す
断面図である。FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a semiconductor device of the present invention.
【図2】図1に示す半導体装置の封止樹脂6を除いた上
面図である。FIG. 2 is a top view of the semiconductor device shown in FIG. 1 excluding a sealing resin 6;
【図3】本発明の半導体装置の実施の形態の他の例を示
す断面図である。FIG. 3 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention.
【図4】本発明の半導体装置の製造方法を説明するため
の断面図である。FIG. 4 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.
【図5】本発明の半導体装置の製造方法を説明するため
の断面図である。FIG. 5 is a sectional view for illustrating the method for manufacturing a semiconductor device according to the present invention.
【図6】本発明の半導体装置の製造方法を説明するため
の断面図である。FIG. 6 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.
【図7】本発明の半導体装置の製造方法を説明するため
の断面図である。FIG. 7 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention.
【図8】図3に示す半導体装置の製造方法を説明するた
めの断面図である。FIG. 8 is a sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG.
【図9】従来の半導体装置を示す断面図である。FIG. 9 is a cross-sectional view showing a conventional semiconductor device.
【図10】図9に示す半導体装置の製造方法を説明する
ための断面図である。10 is a cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.
【図11】図9に示す半導体装置の製造方法を説明する
ための断面図である。11 is a cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.
1、11・・・・・・・・・・絶縁基体 1a、11a・・・・・・・・半導体素子搭載部 1b、11b・・・・・・・・凹部 2、12・・・・・・・・・・外部リード端子 3a、3b、13a、13b・・半導体素子 4、14・・・・・・・・・・配線導体 6、16・・・・・・・・・・封止樹脂 1, 11 ... Insulating base 1a, 11a .... Semiconductor element mounting part 1b, 11b .... Concave part 2, 12, ... ... External lead terminals 3a, 3b, 13a, 13b semiconductor elements 4, 14,..., Wiring conductors 6, 16,.
Claims (2)
の凹部を有するとともに、該凹部の内側から主面の外周
部にかけて複数の配線導体が配設されて成る略四角平板
状の絶縁基体と、前記凹部の底面に搭載された半導体素
子と、一端部が前記配線導体の前記主面の外周部に導出
した部位に接合され、他端部が前記絶縁基体の側面から
外側に突出した複数の外部リード端子と、前記絶縁基体
および前記半導体素子ならびに前記外部リード端子の前
記一端部を封止する封止樹脂とから成る半導体装置であ
って、前記凹部は、その側面を傾斜面または階段状面と
してあることを特徴とする半導体装置。1. A substantially square plate-shaped insulating base having a concave portion for accommodating a semiconductor element on one main surface, and a plurality of wiring conductors arranged from the inside of the concave portion to the outer peripheral portion of the main surface. And a plurality of semiconductor elements mounted on the bottom surface of the concave portion, one end of which is joined to a portion of the wiring conductor extending to the outer peripheral portion of the main surface, and the other end of which protrudes outward from a side surface of the insulating base. And a sealing resin for sealing the insulating base, the semiconductor element, and the one end of the external lead terminal, wherein the side surface of the concave portion has an inclined surface or a stepped shape. A semiconductor device, which is provided as a surface.
の凹部を有するとともに、該凹部の内側から主面の外周
部にかけて複数の配線導体が配設されて成る略四角平板
状の絶縁基体と、前記凹部の底面に搭載された半導体素
子と、一端部が前記配線導体の前記主面の外周部に導出
した部位に接合され、他端部が前記絶縁基体の側面から
外側に突出した複数の外部リード端子とを、前記絶縁基
体の両主面側にキャビティーを有するモールド金型内に
セットするとともに、該モールド金型内に液状樹脂を注
入して硬化させることによって、前記絶縁基体および前
記半導体素子ならびに前記外部リード端子の一端部を封
止樹脂により封止する半導体装置の製造方法であって、
前記絶縁基体の前記凹部の側面を傾斜面または階段状面
としておくことを特徴とする半導体装置の製造方法。2. A substantially square-plate-shaped insulating base having a concave portion for accommodating a semiconductor element on one main surface and a plurality of wiring conductors arranged from the inside of the concave portion to the outer peripheral portion of the main surface. And a plurality of semiconductor elements mounted on the bottom surface of the concave portion, one end of which is joined to a portion of the wiring conductor extending to the outer peripheral portion of the main surface, and the other end of which protrudes outward from a side surface of the insulating base. The external lead terminals are set in a mold having cavities on both main surfaces of the insulating base, and a liquid resin is injected into the mold to cure the insulating base. A method for manufacturing a semiconductor device for sealing one end of the semiconductor element and the external lead terminal with a sealing resin,
A method of manufacturing a semiconductor device, wherein a side surface of the concave portion of the insulating base is an inclined surface or a stepped surface.
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JP2000005766A JP4369582B2 (en) | 2000-01-06 | 2000-01-06 | Semiconductor device and manufacturing method thereof |
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JP2000005766A JP4369582B2 (en) | 2000-01-06 | 2000-01-06 | Semiconductor device and manufacturing method thereof |
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JP4369582B2 JP4369582B2 (en) | 2009-11-25 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6812556B2 (en) | 2002-04-05 | 2004-11-02 | Oki Electric Industry Co., Ltd. | Multi-chip package semiconductor device having plural level interconnections |
JP2005019815A (en) * | 2003-06-27 | 2005-01-20 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof, circuit board, and electronic equipment |
WO2011040548A1 (en) * | 2009-09-30 | 2011-04-07 | 三洋電機株式会社 | Substrate for mounting element, semiconductor module, optical module and camera module |
CN109473414A (en) * | 2017-09-08 | 2019-03-15 | 万国半导体(开曼)股份有限公司 | Mould intelligent power module and its manufacturing method |
-
2000
- 2000-01-06 JP JP2000005766A patent/JP4369582B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6812556B2 (en) | 2002-04-05 | 2004-11-02 | Oki Electric Industry Co., Ltd. | Multi-chip package semiconductor device having plural level interconnections |
JP2005019815A (en) * | 2003-06-27 | 2005-01-20 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof, circuit board, and electronic equipment |
WO2011040548A1 (en) * | 2009-09-30 | 2011-04-07 | 三洋電機株式会社 | Substrate for mounting element, semiconductor module, optical module and camera module |
CN109473414A (en) * | 2017-09-08 | 2019-03-15 | 万国半导体(开曼)股份有限公司 | Mould intelligent power module and its manufacturing method |
Also Published As
Publication number | Publication date |
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JP4369582B2 (en) | 2009-11-25 |
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