JP2001189729A - Layer three switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce useless data transfer by dividing an interrupt into two according to processing factors and controlling a data transfer size in the case of transferring packet data to a main memory so as to be processed by a CPU. SOLUTION: This switch consists of a PHY 500, a MAC 510, an address solving part 520, a search memory 530, a switch engine 540, a packet memory 550, the CPU 560 and a main memory 570. The part 520 includes a DMA transferring part 524 and a receiving buffer 525 in addition to a packet controlling part 521, an address retrieving part 522 and a CPU interrupting part 523.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a layer 3 switch,
In particular, the present invention relates to improvement of a control method of a layer 3 switch in a network field.

[0002]

2. Description of the Related Art First, an outline of a layer 3 switch will be described. FIG. 3 shows a configuration diagram of a general layer 3 switch. Layer 3 switch means IP (Internet Pr
otocol) and IPX (Internetwork Packet)
Exchange) Layer 3 (network layer) of packets etc.
Is a network relay device that switches a packet having an address (see the packet format in FIG. 4) at a high speed and relays it between subnets (for example, subnet A and subnet B). Before the development of the layer 3 switch, the switching of the layer 3 packet is as follows.
This was done by software processing in the router. On the other hand, the layer 3 switch has a function equivalent to that of a router, and furthermore, realizes a high-speed switching operation by realizing switching processing by hardware using a dedicated ASIC.

FIG. 4 shows the format of a packet. MA
The C (Media Access Control) address is an address of a data link layer in Ethernet. The IP address is a unique address for performing communication using the TCP / IP protocol. ARP
(Address Resolution Protocol) is a protocol for finding a destination MAC address from a destination IP address.

The configuration of the prior art will be described with reference to the block diagram of FIG. This conventional technology uses a PHY (Physical L
ayer Protocol: physical layer protocol) 300, MAC 31
0, address resolution unit 320, search memory 330, switch engine 340, packet memory 350, CPU 36
0 and a main memory 370. here,
The address resolution unit 320 includes a packet control unit 321, an address search unit 322, a CPU interrupt unit 323, and an interrupt factor register 324. Switch engine 340
Includes a switch control unit 341 and a packet memory control unit 342. Further, the CPU 360 includes the processing device 3
61, an interrupt detection unit 362 and a DMA (DirectMemory Acc
ess) The transfer unit 363 is included. Main memory 370
Has a packet storage area 371. Further, the packet controller 321, the packet memory controller 342, the DMA transfer unit 363, the processing device 361, and the packet storage area 371 are interconnected by a CPU interface 380. The CPU interrupt unit 323 and the interrupt detection unit 362 are also interconnected. Also, the packet control unit 321 and the switch control unit 341
90, and performs switching processing of packets sent from the network. Search memory 330
Are connected to the address search unit 322. The packet memory 350 is connected to the packet control unit 342.

[0005] When receiving a packet from the network, the PHY 300 converts the packet from serial data to parallel data. In the case of transmission, the data is converted from parallel data to serial data and transmitted to the network. The MAC 310 performs packet data error checking and the like. In the address resolution unit 320, the packet control unit 321 performs interface control with the MAC 310, switch interface control, an address search instruction, and a CPU interrupt instruction. The address search unit 322 performs an address search of the search memory 330. CPU interrupt unit 3
23 is a CPU detected by the address resolution unit 320
CPU 36 determines the cause of interrupts such as packets addressed to
Send to 0. The interrupt factor register 324 stores an interrupt factor.

[0006] In the switch engine 340, the switch control unit 341 includes a switch interface control and a CPU.
Performs interface control and switch control. The packet control unit 342 controls the packet memory 350. The packet memory 350 stores received packets. In the CPU 360, the processing device 36
1 controls the CPU interface and issues a DMA transfer instruction. The interrupt detection unit 362 detects an interrupt to the CPU 360. The DMA transfer unit 363 performs a DMA transfer between the packet memory 330 and the main memory 370.

The operation of the prior art will be described with reference to the block diagram of FIG. 5 and the flowchart of FIG. Upon receiving a packet from the network (step 400), PH
Address resolution unit 320 from Y 300 via MAC 310
Received by the packet control unit 321 (step 401).
The packet control unit 321 of the address resolution unit 320 is connected to the switch engine 34 via the switch interface 390.
Transfer to 0. The packet sent to the switch engine 340 is sent to the switch control unit 341 and stored in the packet memory 350 by the packet memory control unit 342 (step 402). At the same time, the packet control unit 321 instructs the address search unit 322 to search whether the destination IP address of the received packet is registered in the search memory 330. Therefore, the address search unit 322 searches whether the destination IP address is already registered in the search memory 330 (Step 40).
3).

As a result of the search in search memory 330, destination I
If the P address is detected, it is determined in step 413 whether the packet is a packet addressed to the device (a protocol packet such as RIP or OSPF exchanged between routers) or a “packet addressed to the CPU”.
(Hereinafter, referred to as “packet addressed to CPU”). If the search result is not registered in the search memory 330, the address search unit 322 notifies the packet control unit 321 as "unknown destination packet detection" (hereinafter, "unknown destination packet") (step 404). . The packet control unit 321 requests the CPU interruption unit 323 for a CPU interruption. The CPU interrupt unit 323 causes the CPU 360 to generate an interrupt (Step 405).

When the interrupt detection unit 362 in the CPU 360 recognizes this interrupt, it notifies the processing unit 361. The processing device 361 transfers the packet stored in the packet memory 350 to the DMA transfer unit 363,
0 to be stored in the packet storage area 371 in the
A transfer is activated and executed (step 406). When the DMA transfer is completed, the DMA transfer unit 363 notifies the processing device 361 of the completion. Next, the processing device 361 reads (reads) the interrupt factor register 324 of the address resolution unit 320.
Then, it is determined whether the received packet is a “packet addressed to the CPU” or a “destination unknown packet” (step 407,
408).

When the address resolution unit 320 determines that the packet is an unknown destination packet, the CPU 360 performs ARP processing to obtain a destination MAC address corresponding to the destination IP address (step 409). The destination MAC address and the source MAC address in the packet storage area 371 are rewritten (step 410). After rewriting, the CPU 360
The packet is transferred to and stored in the packet memory 350 (step 411). Then, the packet is output from the packet memory 350 to the corresponding transmission port (step 412).

[0011]

SUMMARY OF THE INVENTION In the prior art,
The interruption to the CPU is performed when the destination IP address is that of the router itself, that is, a packet that requires CPU processing (a packet addressed to the CPU).
An interrupt is performed for requesting an ARP process to the CPU 360 without an address (destination unknown packet). When the received packet is a “packet addressed to the CPU”, all the data of the packet needs to be transferred to the main memory 370. On the other hand, when the received packet is “unknown destination packet”, all the data of the received packet are transferred. There is no need to transfer, and it is enough if there is 64 bytes in the header part. However, in the related art, all the packets are transferred to the main memory 370 regardless of the CPU interrupt factor.

Most packets processed by the CPU interrupt are:
This is "unknown destination packet", which is extremely high compared to the frequency of occurrence of "packet addressed to CPU". Therefore, there is a problem in that the time required to transfer all data of the packet to the main memory 370 is wasted. Also, this is one of the factors that significantly lowers "address learning performance (performance indicating how many new addresses can be learned per second)" which is one of the performance indexes of the layer 3 switch. In addition, unnecessary data transfer to the main memory increases the number of accesses to the packet memory 350, which in turn causes a reduction in layer 3 switching performance.

[0013]

SUMMARY OF THE INVENTION Accordingly, a main object of the present invention is to provide a destination IP address for which a received packet is not registered by an address search.
When a packet, that is, a "destination unknown packet" is received, only a data necessary for address rewriting is transferred to the main memory, thereby reducing unnecessary data transfer and providing a layer 3 switch for improving address learning performance. That is.

[0014]

The present invention comprises a plurality of PHYs,
It is composed of a plurality of MACs, an address resolution unit, a search memory, a switch engine, a packet memory, a main memory and a CPU interconnected with these via a CPU interface.The address resolution unit is connected to a packet control unit and a search memory. A Layer 3 switch including an address search unit and a CPU interrupt unit for interrupting the CPU, wherein the address resolution unit is connected to the packet control unit and stores a header of the received packet; D that is connected between the unit and the CPU interface and that performs DMA transfer of packet data from the receive buffer to main memory
Including MA transfer unit.

According to the preferred embodiment of the present invention, the receiving buffer stores 64 bytes of the header portion of the received packet. The CPU includes a processing unit, an interruption detection unit connected to the CPU interruption unit of the address resolution unit, and an interruption inspection unit for examining an IP address of a packet transferred from the interruption detection unit.
In addition to the packet storage area, the main memory
It has a packet determination area, and indicates whether a packet stored in the packet storage area is a packet addressed to the CPU or a packet whose destination is unknown. Further, the switch engine includes a switch control unit connected to a packet control unit of the address resolution unit via a switch interface, and a packet memory control unit connected to a packet memory.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above and other objects, features and advantages of the present invention, preferred embodiments of a layer 3 switch according to the present invention will be described in detail with reference to the accompanying drawings. explain.

FIG. 1 is a block diagram showing a preferred embodiment of a layer 3 switch according to the present invention. The layer 3 switch includes a PHY 500, a MAC 510, an address resolution unit 52
0, search memory 530, switch engine 540, packet memory 550, CPU 560, and main memory 5
70. The address resolution unit 520
Packet control unit 521, address search unit 522, CPU interrupt unit 523, DMA transfer unit 524, and reception buffer 52
5 is included. The switch engine 540 includes a switch control unit 541 and a packet memory control unit 542. The CPU 560 includes a processing unit 561, an interrupt detection unit 56
2 and an interrupt data inspection unit 563. Also,
The main memory 570 includes a packet storage area 571 and a packet discrimination area 572. Packet control unit 521, DMA transfer unit 524, switch control unit 54
1. The processing unit 561, the interrupt data detection unit 562, and the main memory 570 are interconnected by a CPU interface 580. Further, the packet control unit 521 and the switch control unit 541
Connected to 0. Further, the search memory 530 is connected to the address search unit 522, and the packet memory 550 is connected to the packet memory control unit 542. Also,
The CPU interrupt unit 523 is connected to the interrupt detection unit 562.

The CPU interface 580 includes an address resolution unit 520 and a switch engine 5 connected thereto.
40, CPU 560 and main memory 570
0 is an interface for processing. The switch interface 590 is an interface for performing switching processing of a packet sent from the network by the address resolution unit 520 and the switch engine 540 connected thereto.

Next, the function of each component in FIG. 1 will be described. When receiving a packet from the network, the PHY 500 converts the packet from serial data to parallel data. On the other hand, in the case of transmission, parallel data is converted to serial data and transmitted over a network. The MAC 510 performs an error check and the like of the packet data.

In the address resolution unit 520, the packet control unit 521 controls the interface with the packet from the MAC 510, issues an address search instruction to the address search unit 522, and displays “address unknown” in the address search result from the address search unit 522. A notification is sent to the DMA transfer unit 524 as to whether the packet is an “address” or a “packet addressed to the CPU”. The address search unit 522 controls the search memory 530,
It searches for the destination IP address of the received packet and notifies the packet control unit 521 of the search result. CPU interrupt unit 523
Interrupts the CPU 560. The DMA transfer unit 524 transfers packet data from the packet memory 550 when the received packet is a “packet addressed to the CPU”, and from the reception buffer 525 when the received packet is “unknown destination packet”.
DMA transfer to The reception buffer 525 is a buffer that stores 64 bytes of the header portion of the reception packet.

Next, in the switch engine 540,
The switch control unit 541 includes the switch interface 59
0, packet switching control, and CPU interface 580 control. The packet memory control unit 542 controls the packet memory 550. The packet memory 550 is an area where received packets are temporarily stored.

In the CPU 560, the processing unit 561 includes a CPU
It controls the interface 580, performs ARP processing, and rewrites addresses. The interrupt detection unit 562 detects an interrupt from the address resolution unit 520, and outputs an interrupt data check unit 563.
Instruct the inspection. The interrupt data inspection unit 563 is configured to output the destination IP address of the packet specified and transferred from the interrupt detection unit 562.
It is checked whether the address is not registered in the search memory 530 due to the address resolution or whether the address is a packet of the destination IP address addressed to the CPU 560. In the main memory 570, the packet storage area 571 is
This area stores packets that need to be processed in U560. The packet discrimination area 572 indicates whether the packet stored in the packet storage area 571 is a “packet addressed to CPU” or a “packet with unknown destination”.

Next, the operation of the preferred embodiment of the layer 3 switch shown in FIG. 1 will be described with reference to the flowchart of FIG. When a packet is received from the network (step 600), the packet is transmitted from PHY 500 to MAC5.
The address is sent to the address resolution unit 520 via 10 (step 601). Therefore, the packet control unit 521 stores 64 bytes of the header portion of the packet in the reception buffer 525 (Step 602). Next, the destination IP of the received packet
It instructs the address search unit 522 to search for an address. At the same time, the packet is
0 to the switch control unit 541. The packet passed to the switch control unit 541 is stored in the packet memory 550 by the packet memory control unit 542 (Step 603). The search result of the search memory 530 by the address search unit 522 is notified to the packet control unit 521 (step 604). As a result of this search, destination I
The P address is not registered in the search memory 530,
That is, in the case of "unknown destination packet" (step 605).
First, the packet control unit 521 activates the DMA transfer unit 524. Therefore, the DMA transfer unit 524
5 is transferred to the packet storage area 571 of the main memory 570 (step 606).

Next, in step 605, the address search matches and the destination IP address is addressed to the device (step 61).
In the case of 4), the packet stored in the packet memory 550 is DMA-transferred to the packet storage area 571 in the main memory 570 (step 615). When this transfer ends, the DMA transfer unit 524 sends the packet control unit 5
Then, a completion interrupt is made to 21. The packet control unit 521 stores the interrupt factor in the packet determination area 572 of the main memory 570, and instructs the CPU interrupt unit 523 to interrupt the CPU 560. The CPU interrupt unit 523 is an interrupt detection unit 5 of the CPU 560.
An interrupt is made to 62 (step 607). The interrupt detecting unit 562 that has detected the interrupt instructs the interrupt data checking unit 563 to check whether the data transferred by DMA is a “destination unknown packet” or a “CPU packet” (step 60).
8).

In the case of "unknown destination packet" (step 6)
In step 09), the processing unit 561 of the CPU 560 performs an ARP process (step 610). After this ARP processing, the CPU 560
Destination MAC address and source MAC obtained by ARP
Based on the address, the destination MAC address and the source MAC address in the header portion of the packet storage area 571 are rewritten (step 611). After rewriting, the packet header 64 Byte is overwritten on the packet header 64 Byte stored in the packet memory 550. The switch control unit 541 passes the 64-byte packet to the packet memory control unit 542, and the packet is stored in the packet memory 550 (Step 612). The switch control unit 541 converts the packet stored in the packet memory 550 into the destination IP address.
The address is transmitted to the corresponding port (step 613).

The configuration and operation of the preferred embodiment of the layer 3 switch according to the present invention have been described above in detail. However, it should be noted that such exemplary embodiments are merely examples of the present invention and do not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made without departing from the spirit of the invention.

[0027]

As described above, according to the layer 3 switch of the present invention, the following remarkable practical effects can be obtained. When the destination IP address of the received packet is not registered in the search memory due to the address resolution ("unknown destination packet"), when transferring the packet data to the main memory to rewrite the address for routing processing By using the DMA transfer function of the address resolution unit, it is possible to directly transfer packet data of the number of bytes required for rewriting the MAC address to the main memory without using the CPU in order to perform routing. Therefore, useless data transfer can be eliminated, address learning performance can be improved, and a reduction in switching performance can be prevented by reducing the number of accesses to the packet memory by useless data transfer.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a preferred embodiment of a layer 3 switch according to the present invention.

FIG. 2 is a flowchart illustrating an operation of the layer 3 switch of FIG. 1;

FIG. 3 is a configuration diagram of a general layer 3 switch.

FIG. 4 is a packet format of a layer 3 switch.

FIG. 5 is a configuration diagram of a conventional layer 3 switch.

6 is a flowchart showing an operation of the layer 3 switch of FIG.

[Explanation of symbols]

 500 Physical layer protocol (PHY) 510 Medium access control (MAC) 520 Address resolution unit 521 Packet control unit 522 Address search unit 523 CPU interrupt unit 524 DMA transfer unit 525 Receive buffer 530 Search memory 540 Switch engine 541 Switch control unit 542 packet Memory control unit 550 Packet memory 560 CPU (central processing unit) 561 Processing unit 562 Interrupt detection unit 563 Interrupt data inspection unit 570 Main memory 571 Packet storage area 572 Packet discrimination area 580 CPU interface 590 Switch interface

Claims (5)

[Claims] 1. A plurality of physical layer protocols (PHYs), a plurality of medium access controls (MACs), an address resolution unit connected to the MACs, a search memory connected to the address resolution units,
A switch engine, a packet memory connected to the switch engine, a main memory for storing received packets, and a CPU interconnected via a CPU interface.The address resolution unit is connected to a packet control unit and the search memory. A layer 3 switch including an address search unit and a CPU interrupt unit that interrupts the CPU, wherein the address resolution unit is connected to the packet control unit and stores a header portion of the reception packet; The layer 3 switch, further comprising a DMA transfer unit connected between the packet control unit and the CPU interface and configured to perform a DMA transfer of packet data from the reception buffer to the main memory. 2. The layer 3 switch according to claim 1, wherein said reception buffer stores 64 bytes of a header portion of said reception packet. 3. The CPU includes: a processing unit; an interrupt detection unit connected to the CPU interruption unit of the address resolution unit; and an interrupt for checking an IP address of a packet transferred from the interruption detection unit. The layer 3 switch according to claim 1, further comprising a data inspection unit. 4. The main memory has a packet determination area in addition to a packet storage area, and indicates whether a packet stored in the packet storage area is a packet addressed to a CPU or a packet whose destination is unknown. Terms 1, 2
Or the layer 3 switch according to 3. 5. The switch engine includes a switch controller connected to the packet controller of the address resolution unit via a switch interface, and a packet memory controller connected to the packet memory. The layer 3 switch according to claim 1, wherein