JP2001185038A - Substrate for plasma display - Google Patents

Abstract

(57) [Problem] To eliminate partition wall defects and display defects in a PDP. A top surface of a partition wall has a surface roughness Rmax of 2 μm.
m to 20 μm, and the surface roughness Rma of the dielectric layer 7
x is set to 10 μm or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma address display (PALC), a plasma display (PDP), a field emission device (FED), and the like used for a high-precision, inexpensive, thin, large-screen color display, etc. The present invention relates to a plasma display device substrate (hereinafter, a PDP substrate) to be used.

[0002]

2. Description of the Related Art CRTs, which have been widely used as image display devices, have disadvantages such as large volume and large weight. Due to the recent spread of multimedia, light emitting diodes (LED) and liquid crystal (LC) have been used as information interfaces.
D) or field emission device (FED), plasma display (PDP), plasma address display (P
A flat image display device having features such as high image quality with a large screen such as ALC), light weight, and thinness, and which can be installed anywhere, has been developed, and the range of use thereof has been expanding. As a flat panel image display device that meets such demands, PDPs utilizing plasma emission are attracting attention as light-emitting elements of color image display devices for large screens.

[0003] In these display devices, in order to utilize various discharge phenomena, insulating substrates are arranged opposite to each other at regular intervals to form a discharge space, in which a discharge gas is filled or a high vacuum is maintained. Since a partition structure for partitioning the discharge space is required from the necessity, the partition structure is formed by molding a partition material mainly containing a glass component having a thermal expansion coefficient similar to that of a glass substrate used as an insulating substrate.

A PDP will be described as an example of an image display device having such a structure. As shown in FIG. 4, the PDP is provided with a discharge electrode 3 and a discharge electrode 3 in a space surrounded by partition walls 2 called minute display cells 4 between a pair of flat transparent insulating substrates forming a back plate 1 and a front plate 5. An address electrode 8, a dielectric layer 7 is provided so as to cover the address electrode 8, and a structure in which a dischargeable gas such as a rare gas is filled in the space is formed. Is used to emit light by emitting the phosphor 6 provided on the screen. Therefore, the airtightness and barrier properties of the partition structure are regarded as important so that adjacent display cells 4 do not emit light due to leakage of discharge or the like.

[0005] As a method of manufacturing the partition wall structure, various molding methods such as a screen printing method, a sand blast method, a photosensitive paste method, a press molding method, and a resin embedding method have been proposed.

[0006]

However, according to the prior art, when a partition is formed by, for example, a screen printing method or a sand blast method, there are many irregularities on the top of the partition and there is a problem in the surface roughness. A gap is generated at the joint with the face plate, the function as a partition does not work sufficiently, and the junction with the front plate, the top of the partition is missing at the time of panel sealing,
Leakage of plasma discharge occurs, causing adjacent cells to emit light,
As a result, there is a problem that abnormal lighting occurs. Further, when the partition walls are formed by the same method, the thickness of the dielectric layer tends to vary, so that the plasma discharge becomes unstable, resulting in abnormal lighting.

As a method for solving this problem, Japanese Patent Application Laid-Open
According to JP-A-176267 and JP-A-8-304804, the top of the partition is polished to avoid a plasma leak phenomenon due to a surface roughness problem before and after the top of the partition, and the top of the partition is flattened. , Specifically, R
A method in which max is set to 1 μm or less has been proposed.

However, in addition to the existing manufacturing method, the flattening of the top of the partition wall cannot be performed without a separate processing step such as polishing, and the manufacturing step is complicated by adding a new processing step. And the process yield decreases.

As a method for solving this problem, Japanese Patent Application Laid-Open
According to the description of JP-A-134676, a molding obtained by filling a mixture of a partition material powder and a binder into a mold is joined and integrated with a substrate, thereby flattening the top of the partition and making Rmax 2 μm. It is possible to:

However, in this case, fine partition wall material powder is required, which is very problematic in terms of cost. Also,
Because of the fine partition wall material powder, the cohesiveness is strong, and the uniform kneading with the binder requires a lot of man-hours, and the yield is low. Further, there is a problem that reagglomeration of the partition wall material powders occurs and hinders formation of the partition walls.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and does not cause abnormal lighting due to leakage of plasma discharge at a junction between a partition and a front plate without performing secondary processing. Such, the surface roughness of the top along the partition wall is high precision, is configured with partition walls that are not easily chipped at the time of panel sealing, and the surface roughness of the dielectric layer is high precision, An object of the present invention is to provide a plasma display device substrate having excellent discharge stability with a high yield.

[0012]

Means for Solving the Problems The present inventor has conducted intensive studies and studies in view of the above-mentioned problems, and as a result, without performing secondary processing, the surface roughness of the top along the partition walls has high accuracy,
It has been found that a plasma display device substrate having excellent discharge stability can be manufactured with high yield by being composed of partition walls in which chipping is unlikely to occur at the time of panel sealing, and having a highly accurate surface roughness of the dielectric layer. The present invention has been reached.

That is, in a plasma display device substrate comprising a plurality of address electrodes and a dielectric layer covering the plurality of address electrodes on a back plate, and a plurality of partition walls arranged between the address electrodes, The surface roughness Rmax of the portion is in the range of 2 to 20 μm.

Further, the surface roughness Rmax of the dielectric layer is 10 μm or less.

Further, the top of the partition wall is at least 20 μm.
a flat part having a width of m and an angle of 20 ° provided at both ends of the flat part
Chamfered area of up to 70 ° or radius of curvature of 10 μm or more
It is characterized by comprising a surface portion.

[0016]

According to the plasma display device substrate of the present invention,
Due to the small surface roughness of the top along the partition, the top of the partition is in surface contact at the junction with the front plate, so that abnormal lighting of adjacent cells due to plasma discharge leakage does not occur and display defects occur A rear substrate for a plasma display device that is difficult to perform.

Further, according to the substrate for a plasma display device of the present invention, since the surface roughness of the dielectric layer covering the plurality of address electrodes is small, the thickness variation of the dielectric layer is small, and the plasma discharge stability is excellent. This is a substrate for a plasma display device in which display defects hardly occur.

Furthermore, without introducing a secondary treatment step, the surface roughness of the top and the dielectric layer along the partition can be reduced, and the partition can be provided with a partition shape capable of reducing damage to the partition. Thus, it has become possible to simultaneously improve the quality of products and simplify the manufacturing process.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are schematic sectional views of a substrate for a plasma display device according to the present invention. The back plate 1 is an insulating substrate made of soda lime glass or various ceramics,
A plurality of address electrodes 7 are formed on the back plate 1. The address electrodes 8 are covered with a structure composed of the dielectric layer 7 and the barrier ribs 2, and the display cells 4 are formed by the barrier ribs 2.

Here, in the present invention, a flat portion 12 and a chamfered portion 13 or an R-face portion 14 provided at both ends thereof are provided at the top of the partition 2, and the surface roughness Rm of the top is provided.
ax is set to 2 to 20 μm or less. This is a surface roughness necessary for the partition wall 2 to perform a sufficient function to prevent leakage of plasma discharge, and the surface roughness Rmax is 20%.
If it exceeds μm, a gap is generated at the joint with the front plate 5, the function as the partition wall 2 does not work sufficiently, and a leak of plasma discharge occurs, causing the adjacent cell to emit light, resulting in abnormal lighting. On the other hand, if Rmax is less than 2 μm, it is sufficiently effective to prevent plasma discharge leak. However, the primary powder itself of the partition wall material must be finely divided, and the primary particles are aggregated by the fineness. May occur, which may hinder the formation of the partition walls, which is a problem in terms of cost and productivity.

The flat portion 12 on the top of the partition 2 must have a width W of at least 20 μm. This is a width necessary for the partition walls 2 to perform a sufficient function to prevent plasma discharge leakage and to prevent the partition walls 2 from being damaged at the time of joining with the front plate 5 and sealing the panel.

Further, at both ends of the flat portion 12 of the partition 2, a chamfered portion 13 shown in FIG. 1A or an R surface portion 14 shown in FIG. 1B is provided. This is because if the top end of the partition wall 2 has a steep shape, stress concentration occurs at the top end portion of the partition wall 2 at the time of joining with the front plate 5 and sealing the panel, and damage such as chipping is likely to occur at the base point. It is.

Here, in the case of the chamfered portion 13, the flat portion 12
Is preferably in the range of 20 ° to 70 °. This is an angle of the chamfered shape effective for preventing chipping of the top end of the partition wall. Outside this range, for example, if the angle is less than 20 °, the lower side of the chamfered portion 13 is easily chipped, and if the angle is 70 ° or more, the upper side of the chamfered portion 13 is chipped. It will be easier. Also, the R surface 1
In the case of No. 4, a range where the radius of curvature r of the R surface portion 14 is 10 μm or more is preferable. If the radius r is less than 10 μm, for example, chipping easily occurs at the top end of the partition wall.

The surface roughness Rmax on the dielectric layer 7 shown in FIG. 1 is set to 10 μm or less. This is the value of the surface roughness required to obtain a stable plasma discharge,
If the surface roughness Rmax exceeds 10 μm, the plasma discharge becomes unstable due to a variation in the thickness of the dielectric layer 7 on the address electrode 8, resulting in lighting defects such as lighting delay.

Next, a method of manufacturing a PDP substrate according to the present invention will be described.

FIG. 2 shows a method in which a partition wall forming mold is filled with a partition wall forming composition and then transferred to a back plate.

First, as shown in FIG. 2A, a molding die 9 having a concave portion conforming to the shape of the partition 2 and the dielectric layer 7 is prepared. At this time, the bottom surface of the concave portion of the molding die 9, that is, the partition wall 2
The surface corresponding to the top has a chamfered or rounded surface. Into the concave portion of the molding die 9, a composition 10 for forming a partition wall comprising ceramic or glass powder, a solvent and an organic additive is filled. The ceramic or glass powder used at this time does not need to be particularly subjected to pulverization, and may have a general particle size. Specifically, the average particle size is 2 to 5 μm.
m. These are pressed against the back plate 1 and the composition 10 for forming a partition is cured by a curing method corresponding to the composition 10 for forming a partition.

Next, as shown in FIG. 2B, the mold 9 is released, and the partition wall 2 and the dielectric layer 7 are formed on the back plate 1.
Transcribe The thus-obtained partition wall molded body is heated at a predetermined temperature to remove the binder, and then subjected to a baking step to easily manufacture the plasma display device substrate having the partition wall 2 and the dielectric layer 7 of the present invention. Can be.

FIG. 3 shows that the partition wall forming layer composed of the partition wall forming composition on the back plate is pressed against a mold having a concave portion conforming to the shape of the partition wall and the dielectric layer to plastically deform the partition wall forming layer. And forming a partition and a dielectric layer on the back plate.

First, as shown in FIG. 3A, a partition-forming composition 10 is applied on a portion of the rear plate 1 where the partition 2 and the dielectric layer 7 are to be formed, to form a partition-forming layer 11. At this time, the ceramic or glass powder constituting the partition wall forming composition 10 does not need to be particularly subjected to pulverization treatment, and may have a general particle size. Specifically, those having an average particle size of 2 to 5 μm may be used. Next, as shown in FIG.
And pressurizing with a molding die 9 having a concave portion conforming to the shape of the dielectric layer 7 to plastically deform the partition wall forming layer 11,
The shapes of the partition 2 and the dielectric layer 7 are provided. At this time, the bottom surface of the concave portion of the mold 9, that is, the surface corresponding to the top of the partition 2 has a chamfered or rounded surface.

Thereafter, as shown in FIG. 3C, the mold 9 is released, and the partition walls 2 and the dielectric layer 7 can be formed on the back plate 1. At this time, since the partition wall forming composition 10 uses ceramic or glass powder having a general particle size, the surface roughness of the partition walls 2 is 2 to 20 μm, and the surface roughness of the dielectric layer 7 is 10 μm or less. . The thus-obtained partition wall molded body is heated at a predetermined temperature to remove the binder, and then subjected to a firing step, whereby a substrate for a plasma display device having the partition walls 2 and the dielectric layer 7 of the present invention can be easily manufactured. be able to.

The composition 10 for forming a partition wall usable in the present invention.
Any material may be used as long as it becomes glassy after firing and can maintain airtightness, as long as it is a glass material composed of ceramic or glass powder as a primary material, for example, a mixture of a low melting point glass powder and an oxide ceramic powder as an inorganic component. The mixture of the inorganic component, the solvent, and the organic additive may be appropriately mixed with the partition wall 2 and the dielectric layer 7.
Can be adjusted according to the molding conditions.

As the low melting point glass powder, various glass materials containing a silicate as a main component and one or more of lead, zinc, sulfur, selenium, alum, manganese, alkali salt, bismuth oxide and the like can be used. it can. The average particle size of the ceramic or glass powder is preferably several tens of microns to sub-micron, and is preferably in the range of 2 to 5 microns.

The solvent is not particularly limited as long as it is compatible with the organic additive.

As the organic additive, a thermoplastic resin, an ultraviolet curable resin, a photocurable resin, a thermosetting resin, or the like can be used. Others include dispersants,
Examples include various organic substances such as a release agent, a curing agent, a lubricant, and a plasticizer.

Next, the molding die 9 that can be used in the present invention may be made of any material such as ceramics, metal, resin and rubber.
There is no particular limitation. The shape of the mold 9 is
The shape is not limited to a flat plate, and may be any shape as long as it has a groove having the same shape as the partition 2 or the shape of the dielectric layer 7.

As the substrate used for the back plate 1 of the present invention, a transparent glass substrate such as soda lime glass, low soda glass, lead alkali silicate glass and borosilicate glass can be used. It is desirable that the expansion coefficients are similar.

The address electrodes 8 of the back plate 1 are made of a conductive metal such as Ag, Ni, Al, Pt, Au, Pd, Cu, or an alloy thereof, or a small amount of glass frit on the conductive metal or its alloy. Can be formed by using a conductive paste in which is mixed.

The means for forming the partition wall forming layer 11 composed of the partition wall forming composition 10 on the back plate 1 is not particularly limited. For example, a roll coater, a doctor blade, screen printing, gravure printing, etc. Can be used as long as it can be finally formed with a uniform film thickness.

[0041]

Next, the substrate for a plasma display device of the present invention was evaluated as follows. (Example 1) First, on a back plate 1 made of soda-lime glass having a thickness of 2.8 mm and 42 inches in size, an electrode paste mainly composed of Ag was used to form a width 8 using a thick film printing method.
Address electrodes 8 of 0 μm were formed on the entire surface in a stripe pattern at a pitch of 360 μm and baked to produce back plate 1 with address electrodes 8. On the other hand, the flat part width at the top of the partition wall is 50 μm,
A chamfered shape having an angle of 45 ° with the flat portion on the top of the partition wall, a width of 20 μm, a large number of partition-shaped grooves having a height of 200 μm and a pitch of 360 μm, and the thickness of the dielectric layer 7 of 20 μm were taken into consideration. Mold 9 was prepared. Next, after filling a mold 10 with a partition wall forming composition 10 comprising a low melting glass powder, a reaction curable resin, a solvent, and a dispersant, the back plate 1 with the address electrodes 8 is pressed against the mold 9 to form a partition wall. After the composition 10 was cured by reaction to give the shape of the partition 2 and the dielectric layer 7, the mold 9 was released to form a partition molded body on the back plate 1. Next, after the rear plate 1 on which the partition wall molded body is in close contact is removed at a predetermined temperature to remove the binder, 550 to 550
It was baked at a temperature of 600 ° C. for 10 minutes to produce a PDP substrate for evaluation integrated with the back plate 1.

When the surface roughness of the flat portion on the top of the partition wall was measured at a measurement point at which the obtained substrate was randomly extracted, the surface roughness Rmax was 5.33 μm. When the surface roughness of the dielectric layer 7 was measured, the surface roughness Rmax was 4.52 μm. Scanning electron microscope (SE
When the shape was measured in M), the flat part width at the top of the partition was 4
The chamfer shape was 5 μm, the angle was 45 °, and the width was 18 μm. (Example 2) A back plate 1 with address electrodes 8 was produced in the same manner as in Example 1. On the other hand, the flat portion width at the top of the partition is 50 μm,
A molding die 9 having many partition-shaped grooves corresponding to a partition top end radius of 50 μm, a height of 200 μm, and a pitch of 360 μm and considering the thickness of the dielectric layer 7 of 20 μm was prepared. Next, a partition wall forming composition 10 composed of a low melting glass powder, a binder, a solvent, and a dispersant is uniformly applied on the back plate 1 with the address electrodes 8 using a doctor blade and dried to form a partition wall forming layer 11. did. Thereafter, the mold 9 is press-bonded to the back plate 1 on which the partition wall forming layer 11 is formed, and the partition wall forming layer 11 made of the partition wall forming composition 10 is plastically deformed to give the shape of the partition wall 2 and the dielectric layer 7. After that, the molding die 9 was released to form a partition wall molded body on the back plate 1. Thereafter, the back plate 1 is maintained at a predetermined temperature to remove the binder, and
It was baked at a temperature of 0 to 600 ° C. for 10 minutes to produce a PDP substrate for evaluation integrated with the back plate 1.

When the surface roughness of the flat portion on the top of the partition wall of the obtained substrate was measured, the surface roughness Rmax was 4.92 μm.
The surface roughness Rmax of the dielectric layer 7 is 4.27 μm,
The flat part width at the top of the partition is 45 μm, and the radius at the top end of the partition is 45 μm
m-plane. Example 3 A back plate 1 with address electrodes 8 was produced in the same manner as in Example 1. On the other hand, the partition top flat portion width is 50 μm, the chamfered shape formed by the angle of 10 ° with the partition top flat portion, the width is 20 μm, the height is 200 μm, the pitch is 360 μm, the partition shape has many grooves, and the dielectric is Layer 7 thickness 2
A mold 9 considering 0 μm was prepared. Thereafter, a PDP substrate for evaluation was produced in the same manner as in Example 2.

When the surface roughness of the flat portion on the top of the partition wall of the obtained substrate was measured, the surface roughness Rmax was 4.22 μm,
The surface roughness Rmax of the dielectric layer 7 is 4.77 μm,
The width of the flat portion at the top of the partition wall is 45 μm, and the chamfer shape is at an angle of 10.
° and a width of 18 μm. Example 4 A back plate 1 with address electrodes 8 was produced in the same manner as in Example 1. On the other hand, the flat portion width at the top of the partition is 50 μm,
A molding die 9 having a large number of partition-shaped grooves corresponding to a radius of the partition top end of 10 μm, a height of 200 μm, and a pitch of 360 μm, and considering the thickness of the dielectric layer 7 of 20 μm was prepared. Thereafter, a PDP substrate for evaluation was produced in the same manner as in Example 2. When the surface roughness of the flat part on the top of the partition wall of the obtained substrate was measured, the surface roughness Rmax was 5.12 μm.
m, the surface roughness Rmax of the dielectric layer 7 is 4.97 μm, the flat width at the top of the partition is 45 μm, and the radius at the top end of the partition is 8
It had a μm R-plane. Example 5 A back plate 1 with address electrodes 8 was produced in the same manner as in Example 1. Next, a partition wall forming composition 10 comprising a low melting glass powder, a binder, a solvent, and a dispersant is uniformly applied on a back plate 1 with an address electrode 8 with a doctor blade, and dried to form a 200 μm thick partition wall forming layer. 11 was formed. After that, a photosensitive resin was stuck on the partition wall forming layer 11 and patterning was performed at a line width of 90 μm and a pitch of 360 μm.
A partition wall molded body was formed on the back plate 1. Then, back plate 1
After the binder is removed at a predetermined temperature,
It was baked at a temperature of 00 ° C. for 10 minutes to produce a PDP substrate for evaluation integrated with the back plate 1.

When the surface roughness of the flat portion on the top of the partition wall of the obtained substrate was measured, the surface roughness Rmax was 5.01 μm.
The surface roughness Rmax of the dielectric layer 7 is 12.98 μm, the width of the flat portion at the top of the partition is 83 μm, and the top end of the partition is at an angle of 9 μm.
At 0 °, there was no R-plane. (Example 6) A back plate 1 with address electrodes 8 was produced in the same manner as in Example 1. On the other hand, the flat portion width at the top of the partition wall is 20 μm,
A molding die 9 having many partition-shaped grooves corresponding to a partition top end radius of 50 μm, a height of 200 μm, and a pitch of 360 μm and considering the thickness of the dielectric layer 7 of 20 μm was prepared. Thereafter, a PDP substrate for evaluation was produced in the same manner as in Example 2. When the surface roughness of the flat part on the top of the partition wall of the obtained substrate was measured, the surface roughness Rmax was 4.99 μm.
m, the surface roughness Rmax of the dielectric layer 7 is 4.45 μm, the flat width at the top of the partition is 18 μm, and the radius at the top end of the partition is 4 μm.
It had an R-plane of 5 μm. Comparative Example 1 A back plate 1 with address electrodes 8 was produced in the same manner as in Example 1. Next, the dielectric layer 7 is screen-printed.
Was printed and dried. Then, on a screen having a line pattern with a line width of 70 μm and a pitch of 360 μm,
Thick film lamination printing was repeated 10 times to form a partition wall molded body on the back plate 1. Thereafter, the back plate 1 was held at a predetermined temperature to remove the binder, and then fired at a temperature of 550 to 600 ° C. for 10 minutes to produce a PDP substrate for evaluation integrated with the back plate 1. When the surface roughness of the flat portion on the top of the partition wall of the obtained substrate was measured, the surface roughness Rmax was 21.11 μm.
m, the surface roughness Rmax of the dielectric layer 7 is 4.32 μm, the flat portion width at the top of the partition is 40 μm, and the top end of the partition has a radius of 5 μm.
It had an R plane of 0 μm. Comparative Example 2 A back plate 1 with address electrodes 8 was produced in the same manner as in Example 1. On the other hand, the flat portion at the top of the partition has a chamfered shape with a width of 50 μm, an angle of 45 ° with the flat portion at the top of the partition, a width of 20 μm, a height of 200 μm, and a large number of partition-shaped grooves corresponding to a pitch of 360 μm. Layer 7 thickness 2
A mold 9 considering 0 μm was prepared. Next, on the back plate 1 with the address electrodes 8, a partitioning composition 10 composed of a low-melting glass powder having an average particle diameter of 0.7 μm, a binder, a solvent, and a dispersant was subjected to pulverization by a vibration mill. Uniformly apply and dry with a doctor blade to form partition wall forming layer 11
Was formed. Thereafter, a PDP substrate for evaluation was produced in the same manner as in Example 2.

When the surface roughness of the flat portion on the top of the partition wall of the obtained substrate was measured, the surface roughness Rmax was 1.88 μm.
The surface roughness Rmax of the dielectric layer 7 is 2.05 μm,
The width of the flat part at the top of the partition wall is 45 μm, and the chamfered shape is an angle of 45.
° and a width of 18 μm.

Examples 1 and 2 and Comparative Example 1 thus obtained
Phosphors 6 were formed on PDP substrates for evaluation of Nos. 6 to 6 and joined to the front plate 5 to form a panel. Then, a display defect inspection was performed on the manufactured panel. Thereafter, the substrate for evaluation PDP was taken out of each panel, and the number of defects of the partition walls was measured using an appearance inspection apparatus by image processing.

As is clear from Table 1, in Comparative Example 1, 68 display defects caused by the surface roughness on the top of the partition wall, and in Comparative Example 2, due to the surface roughness and the shape of the partition wall. No display defects occurred, but the fineness of the glass powder to reduce the surface roughness affected the partition wall formability, resulting in 25 display defects, both of which were problems.

On the other hand, in Examples 3 and 4, 5 to 7 display defects caused by the shape of the top end of the partition wall were observed.
In the above, 16 points of display defects caused by the shape of the top end of the partition wall and the surface roughness of the dielectric layer portion occurred, and in Example 6, only 19 points of display defects caused by the width of the top of the partition wall occurred. there were. In Examples 1 and 2, neither a partition wall defect nor a display defect occurred, and the results were optimal. In addition, those having no display defects were evaluated as ○, those having less than 20 points as △, and those with 20 or more points as x.

The present invention is not limited to the above-described embodiment.

[0051]

[Table 1]

[0052]

As described above, according to the plasma display device substrate of the present invention, since the surface roughness of the top along the partition is small, the top of the partition is in contact with the front plate at the joint with the front plate. Because of the contact, abnormal lighting of adjacent cells due to plasma discharge leakage does not occur, and furthermore, variation in the thickness of the dielectric layer is reduced, plasma discharge stability is excellent, and display defects are less likely to occur. At the same time, by providing a partition shape that can reduce partition damage, it is possible to simultaneously improve the quality of products and simplify the manufacturing process.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic cross-sectional views of a substrate for a plasma display device according to the present invention.

FIGS. 2A and 2B are process diagrams showing a transfer molding method for a substrate for a plasma display device of the present invention.

3 (a), 3 (b) and 3 (c) are process diagrams showing a pressure molding method for a plasma display device substrate of the present invention.

FIG. 4 is a cross-sectional view of a general plasma display device substrate.

[Explanation of symbols]

 1: Back plate 2: Partition wall 3: Discharge electrode 4: Display cell 5: Front plate 6: Phosphor 7: Dielectric layer 8: Address electrode 9: Mold 10: Partition forming composition 11: Partition forming layer 12: Flat portion 13: chamfered portion 14: R surface portion W: width of flat portion θ: angle of chamfered portion r: radius of curvature of R surface portion

Claims (4)

[Claims] 1. A plasma display device substrate comprising a plurality of electrodes, a dielectric layer covering the plurality of electrodes, and a plurality of partitions on a main surface of a back plate, wherein the top surface of the partitions has a surface roughness Rmax of 2 to 2. A substrate for a plasma display device having a thickness of 20 μm. 2. The dielectric layer having a surface roughness Rmax of 10 μm.
2. The substrate for a plasma display device according to claim 1, wherein m is equal to or less than m. 3. The method according to claim 1, wherein the top of the partition wall is at least 20 μm.
A flat portion having a width of 20 ° and an angle of 20 ° provided at both ends of the flat portion.
2. The substrate for a plasma display device according to claim 1, wherein the substrate comprises a chamfer of 70 [deg.]. 4. The method according to claim 1, wherein the top of the partition wall is at least 20 μm.
And a radius of curvature 10 provided at both ends of the flat portion.
2. The substrate for a plasma display device according to claim 1, wherein the substrate has an R-plane portion of not less than μm.