JP2001184447A - Information processor, image information professor, and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor which can perform processing in a short time with simple constitution and an image information processor and an information processing method which can not only perform processing in a short time with simple constitution, but also obtain an object image of data in natural form. SOLUTION: Pixel cells PXx,y including photodiodes PD are arrayed in matrix on a semiconductor chip IC, each pixel cell diffuses input image information obtained by the photodiode PD by a resistance network to obtain image information having been diffused at two different time points t2 and t3, and an arithmetic part 18 computes their ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, an image information processing apparatus, and an information processing method for performing analog processing of information such as an image in parallel without calculating digital signals.

[0002]

2. Description of the Related Art Generally, a digital computer is used to process image information. The reason for this is that the use of analog circuits requires adjustment of analog elements to obtain the required accuracy, and is particularly complicated when adjusting spatial gain and removing induction, especially when performing spatial operations in parallel. It is often difficult.

When converting image information from image input means such as a CCD by a digital computer, basically the following processing is performed.

That is, an image of an object is converted by an optical lens into C
An image is formed on a photosensitive surface such as a CD sensor. This allows CC
The D sensor outputs image information as an analog signal.
For example, when an image is captured by a television or a method similar thereto, an electrical signal corresponding to the illuminance of light impinging on each pixel is sequentially and temporally output by raster scanning. This analog signal is shaped by an amplifier. Further, since the reading is performed based on the synchronization pulse, the reading timing of each pixel is determined.

Next, in an analog / digital (A / D) converter, the analog signal is quantized and converted into a digital signal. Thereafter, appropriate processing such as noise removal, distortion correction, filtering, movement / rotation of the image, extraction of lines / contours, etc., combined with these, and improvement of image quality and restoration of the image are performed by image processing techniques. These processes are performed as so-called pre-processes and are also used in pattern recognition.

[0006] This image conversion process is suitable for digital processing that can be made to correspond to the purpose by software, since it is only necessary to mechanically perform an operation suitable for each target image and purpose.

[0007]

However, in the above-mentioned conventional image information processing apparatus, image information by a CCD as an image sensor is converted from an analog signal to a digital signal (A / A / D).
After D-conversion), it is necessary to perform a complicated process on a large amount of data by a computer, so that it takes a long time for the calculation, and as a result, there is a disadvantage that the power consumption increases. That is, in the conventional image information processing apparatus, since processing is performed one point at a time, processing takes a long time for an image having a large number of pixels.

[0008] By the way, in the image conversion processing, it is possible to emphasize a small change which is hard to detect by human eyes, and it is also applied to disease diagnosis and examination. Information requiring advanced human judgment, such as diagnosis, can be given to humans in an emphasized form. In a simple operation of selecting very few bad images from a vast amount of image information including a large number of images of healthy objects such as inspections, it is ideally desirable to be able to perform pattern recognition fully automatically. Further, in order to improve the image quality and effectively check only when the inspector has the above under a favorable environment, it is most desirable to obtain, for example, a complex unevenness or the like quantitatively as a shaded image. At this time, it is desirable that an image with similar shades can be obtained even if the scale is changed.

However, in a conventional image information processing apparatus, there is a limit in quantifying complicated unevenness and the like, and it is difficult at present to see the same depending on the scale.

Therefore, in reality, there is a high demand for realizing an image information processing apparatus that can obtain an image corresponding to the density of an object in a form close to nature with a simple configuration and in a short processing time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an information processing apparatus capable of processing in a short time with a simple configuration, and an information processing apparatus capable of processing in a short time with a simple configuration. In addition, it is an object of the present invention to provide an image information processing apparatus and an information processing method capable of obtaining an object image of data in a form close to nature.

[0012]

To achieve the above object, an information processing apparatus according to the present invention comprises an input node to which information having an arbitrary level is input, and at least one resistor connected to the input node. A first resistor connected to the input node for storing information given as an initial condition to the input node; a second capacitor connected to the input node; and a second capacitor connected to the input node. Means for storing information in which information has been diffused for a predetermined time in the resistance network, in the second capacitive element.

Further, according to the present invention, the information provided as the initial condition stored in the first capacitor and the second
And an arithmetic unit for calculating a ratio with the information after diffusion stored in the capacitive element.

Further, according to the present invention, the analog information given as the initial condition stored in the first capacitive element,
Analog / digital conversion means for converting the analog information after diffusion stored in the second capacitive element into a digital signal, digital information given as initial conditions converted into a digital signal, and digital information after diffusion And an arithmetic unit for calculating the ratio of

Further, an information processing apparatus according to the present invention comprises: an input node to which information having an arbitrary level is input; a resistance network including at least one resistance element connected to the input node; A capacitance element, a second capacitance element, and first means for storing, in the first capacitance element, information in which information supplied to the input node is first-time-spread in the resistance network, and Second means for storing, in the second capacitive element, information in which the information supplied to the input node is spread in the resistor network for a second time different from the first time.

Further, in the present invention, the ratio of the first time-spread information stored in the first capacitor to the second time-spread information stored in the second capacitor is described. And an arithmetic unit for calculating

Further, according to the present invention, the first time-spread information stored in the first capacitor and the second time-spread information stored in the second capacitor are digitally converted. An analog / digital converter for converting the signal into a signal, and a calculation unit for calculating a ratio between the first time-spread digital information converted into a digital signal and the second time-spread digital information.

Further, in the present invention, an input node, an optical sensor unit for receiving light emitted from an object and generating information as an electric signal corresponding to a light receiving level, and an optional level by the optical sensor unit are provided. Input means for inputting information to be input to the input node for a preset storage time, a resistance network including at least one resistance element connected to the input node, and connected to the input node, A first capacitive element, a second capacitive element, a third capacitive element for storing information supplied to the input node and diffused by the resistance network; a first time after the accumulation time has elapsed; First means for storing the diffusion information stored in the first capacitive element in the second capacitive element, and the first means in a second time different from the first time after the accumulation time has elapsed.
And second means for storing the diffusion information stored in the third capacitive element in the third capacitive element.

Further, in the present invention, the ratio of the first-time spread information stored in the second capacitive element to the second-time spread information stored in the third capacitive element is calculated. It has a calculation unit.

Further, in the present invention, the first time diffusion information stored in the second capacitance element and the second time diffusion information stored in the third capacitance element are converted into a digital signal. Analog / digital conversion means for converting, digital spread information of a first time converted into a digital signal,
And a calculation unit for calculating a ratio of the digital spread information to the time of the digital spread information.

According to the image information processing apparatus of the present invention, an input node to which image information having an arbitrary level is input, a resistance network including at least one resistance element connected to the input node, A first capacitive element connected to the input node and storing image information given to the input node as an initial condition; a second capacitive element; and the image information supplied to the input node is connected to the resistor network. Means for storing image information diffused for a predetermined time in the second capacitive element, a pixel cell array in which a plurality of pixel cells are arranged in an array, and a pixel cell array selected from among the plurality of pixel cells. Reading means for reading image information stored in the first capacitive element and the second capacitive element.

Further, according to the present invention, the image information given as the initial condition stored in the first capacitive element of the selected image cell read by the read means and the second capacitive element An arithmetic unit is provided for calculating a ratio with the stored image information after diffusion.

In the present invention, the analog image information given as the initial condition stored in the first capacitance element of the selected image cell read by the reading means and the second capacitance element Analog / digital conversion means for converting the analog image information after diffusion stored in the digital image signal into a digital signal, and the ratio between the digital image information given as the initial condition converted into the digital signal and the digital image information after diffusion. And a calculation unit for calculating

According to the image information processing apparatus of the present invention, there is provided an input node to which image information having an arbitrary level is input, a resistance network including at least one resistance element connected to the input node, and A first capacitive element, a second capacitive element, and a first capacitive element in which image information supplied to the input node is subjected to first time-spreading by the resistance network and stored in the first capacitive element. Means for storing, in the second capacitive element, image information supplied to the input node, the image information being spread by the resistor network for a second time different from the first time. , A pixel cell array in which a plurality of pixel cells including a plurality of pixel cells are arranged in an array, and reading of reading out information stored in a first capacitor element and a second capacitor element of a selected one of the plurality of pixel cells. Having means

Also, in the present invention, the first time-spread image information stored in the first capacitance element of the selected image cell read by the reading means and the second
And an arithmetic unit for calculating a ratio with the second time-spread image information stored in the capacitive element.

Also, in the present invention, the first time-spread image information stored in the first capacitive element of the selected image cell read by the reading means, and the second
Analog / digital conversion means for converting the second time-spread image information stored in the capacitive element into a digital signal, the first time-spread digital image information converted into a digital signal, and the second And a calculation unit for calculating a ratio with the time-spread digital image information.

According to another aspect of the present invention, there is provided an image information processing apparatus comprising: an input node; an optical sensor unit for receiving light emitted from an object to generate image information as an electric signal corresponding to a light receiving level; Input means for inputting image information having an arbitrary level to the input node, a resistance network including at least one resistance element connected to the input node, and the input node connected to the input node. A first capacitor for storing image information given as an initial condition, a second capacitor, and image information obtained by diffusing image information supplied to the input node for a predetermined time in the resistor network. A pixel cell array in which a plurality of pixel cells including means for storing data in a second capacitor element are arranged in an array; and a first capacitor element of a pixel cell selected from among the plurality of pixel cells. And a reading means for reading the image information stored in the second capacitor.

Further, in the present invention, the image information given as the initial condition stored in the first capacitive element of the selected image cell read by the read means and the second capacitive element An arithmetic unit is provided for calculating a ratio with the stored image information after diffusion.

According to the present invention, the analog image information given as the initial condition stored in the first capacitive element of the selected image cell read by the read means and the second capacitive element Analog / digital conversion means for converting the analog image information after diffusion stored in the digital image signal into a digital signal, and the ratio between the digital image information given as the initial condition converted into the digital signal and the digital image information after diffusion. And a calculation unit for calculating

Further, the image information processing apparatus of the present invention comprises: an input node; an optical sensor section for receiving light emitted from an object to generate image information as an electric signal corresponding to a light receiving level; An input unit for inputting image information having an arbitrary level by the unit to the input node; a resistance network including at least one resistance element connected to the input node; a first capacitance element; The capacitive element and the image information supplied to the input node are connected to a first
A first means for storing the time-spread image information in the first capacitive element, and a second means in which the image information supplied to the input node is different from the first time in the resistance network.
And a second means for storing the time-spread image information in the second capacitive element. A pixel cell array in which a plurality of pixel cells are arranged in an array, and a pixel selected from the plurality of pixel cells Reading means for reading image information stored in the first capacitive element and the second capacitive element of the cell.

Also, in the present invention, the first time-spread image information stored in the first capacitance element of the selected image cell read by the reading means and the second time
And an arithmetic unit for calculating a ratio with the second time-spread image information stored in the capacitive element.

Also, in the present invention, the first time-spread image information stored in the first capacitive element of the selected image cell read by the reading means,
Analog / digital conversion means for converting the second time-spread image information stored in the capacitive element into a digital signal, the first time-spread digital image information converted into a digital signal, and the second And a calculation unit for calculating a ratio with the time-spread digital image information.

Further, the image information processing apparatus of the present invention comprises: an input node; an optical sensor unit for receiving light emitted from an object to generate image information as an electric signal corresponding to a light receiving level; An input means for inputting image information having an arbitrary level by the unit to the input node for a preset accumulation time; a resistance network including at least one resistance element connected to the input node; A first capacitive element, a second capacitive element, and a third capacitive element that are connected to each other and store image information supplied to the input node at the accumulation time and diffused by the resistance network; The first means for storing the diffusion information stored in the first capacitive element in the second capacitive element at a first time after the lapse of time is different from the first time after the lapse of the accumulation time. Second time And a second means for storing the diffusion information stored in the first capacitance element in the third capacitance element. A pixel cell array in which a plurality of pixel cells are arranged in an array, Reading means for sequentially reading out image information stored in the second and third capacitors of the selected pixel cell.

Also, in the present invention, the first time diffusion information stored in the second capacitance element of the selected image cell read by the reading means and the third time diffusion information stored in the third capacitance element. And a calculation unit for calculating a ratio to the calculated second time spread information.

According to the present invention, the first time diffusion information stored in the second capacitance element of the selected image cell read by the reading means and the third time diffusion information stored in the third capacitance element are stored. Analog / digital conversion means for converting the converted second time spread information into a digital signal, digital time converted first time digital spread information;
And a calculation unit for calculating a ratio of the digital spread information to the time of the digital spread information.

Further, according to the information processing method of the present invention, information given as an initial condition of information having an arbitrary level is stored, and information obtained by diffusing input information according to a predetermined diffusion equation is obtained. The fractal dimension is obtained by taking the ratio between the information given as the condition and the information after the diffusion.

Further, according to the information processing method of the present invention, the first information at a first time when input information having an arbitrary level is diffused for a predetermined time in accordance with a predetermined diffusion equation, and the input information after the first time, Obtaining second information at a second time when the information is diffused for a predetermined time according to a predetermined diffusion equation;
The fractal dimension is obtained by taking the ratio between the first information and the second information.

In the present invention, the diffusion is performed on a resistance network.

According to the present invention, predetermined information having an arbitrary level, for example, image information is input to the input node. First, information given to the input node as an initial condition is stored in the first capacitive element. Is done. Further, the information supplied to the input node is spread in the resistance network, and the information spread for a predetermined time in the resistance network is stored in the second capacitor. Then, the information given as the initial condition stored in the first capacitive element and the information after diffusion stored in the second capacitive element are converted, for example, from an analog signal to a digital signal, and are sent to the arithmetic unit. Supplied. The arithmetic unit calculates the ratio of the two digital information.

Further, according to the present invention, information having an arbitrary level is given information, for example, image information is inputted to the input node. First, the information supplied to the input node by the first means is converted to a resistance. The first time-spread information in the network is stored in the first capacitive element. Further, the information supplied to the input node by the second means is diffused by the resistor network for a second time different from the first time and stored in the second capacitor. Then, the first time-spread information stored in the first capacitor and the second time-spread information stored in the second capacitor are converted from, for example, an analog signal to a digital signal. Then, it is supplied to the calculation unit. The arithmetic unit calculates the ratio of the two digital information.

Further, according to the present invention, in the optical sensor unit, for example, image information, which is an electric signal corresponding to a light receiving level, is generated by receiving light emitted from the object. The image information generated by the optical sensor unit is supplied to the input node for a storage time set in advance by the input unit.
Then, the image information supplied to the input node during the accumulation time and diffused by the resistance network is stored in the first capacitor.
Next, by the first means, the diffusion information stored in the first capacitive element is stored in the second capacitive element at the first time after the lapse of the accumulation. Further, the diffusion information stored in the first capacitor is stored in the third capacitor at a second time different from the first time after the accumulation time has elapsed. The first time diffusion information stored in the second capacitance element and the second time diffusion information stored in the third capacitance element are:
For example, it is converted from an analog signal to a digital signal,
It is supplied to the calculation unit. The arithmetic unit calculates the ratio of the two digital information.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a system configuration diagram showing a first embodiment of an image information processing apparatus employing an information processing method according to the present invention.

As shown in FIG. 1, the image information processing apparatus 10 includes a pixel cell array 11, a horizontal shift register 12,
Vertical shift register 13, buffers 14, 15, A / D
Converters 16 and 17 and fractal dimension operation unit 18
have.

Among these components, the pixel cell array 11, the horizontal shift register 12, the vertical shift register 13, the buffers 14, 15, and the switch elements SWm, n, SWm + 1, n, SWm + 2, n, And precharge p-channel MOS (PMOS) transistor PT1
1 and PT12 are integrated on the same semiconductor chip IC. The horizontal shift register 12, the vertical shift register 13, the buffers 14, 15, and the switch element SW
Reading means is constituted by m, n, SWm + 1, n, SWm + 2, n and the PMOS transistors PT11, PT12.

The fractal refers to a shape or a phenomenon characterized by a power function.

The pixel cell array 11 includes a plurality of pixel cells PXx, y including a photodiode PD as an optical sensor.
(Where x and y are 1, 2, 3, 4,...), Respectively, are arranged in a matrix. In FIG. 1, for simplification of the drawing, nine pixel cells PXm, n-1, PXm, n, Pm
Xm, n + 1, PXm + 1, n-1, PXm + 1, n, PXm + 1, n + 1,
PXm + 2, n-1, PXm + 2, n, and PXm + 2, n + 1 are shown.

Each pixel cell PXx, y has an input node for an image information signal which is an electric signal connected to a photosensor section PDS including a photodiode PD. Are connected, the image information signal supplied to the input node is diffused by a resistance network, and the image information signals at the input node, which are spread at two different times, are different from each other. And the horizontal shift register 1
2 and outputs the stored image information to the buffers 14 and 15 via the switch elements SWm, n, SWm + 1, n and SWm + 2, n as signals Vout1 and Vout2 based on the control of the vertical shift register 13.

In each pixel cell PXx, y, up to eight resistive elements are connected to the input node, and through the resistive elements,
It is connected to the nearest pixel cells (up to 8 cells). Therefore, in principle, the pixel cell array 11 according to the first embodiment is configured such that the input node NDIN of each pixel cell PXx, y is connected to the nearest pixel cell via the resistance element R as shown in FIG. The input node is connected to the input node NDIN, and each input node is connected to a capacitive element C for storing the input image information signal.

In principle, each pixel cell PXx, y has a first capacitive element C11 and a second capacitive element C12 for storing image information input to the input node NDIN, as shown in FIG. , A third capacitive element C13, a first switch element SW11 as input means for operatively connecting a signal between the photosensor unit PD and the input node ND according to the switching signal sw0, and an input node NDIN and a second capacitance. A second switch element SW12 as first means for operatively connecting the element C12 in response to the switching signal sw1, and operatively connecting the input node NDIN and the third capacitive element C13 in response to the switching signal sw2. It has a third switch element SW13 as a second means as a main component.

Each of the pixel cells PXx, y according to the first embodiment basically has five switching signals sw0, sw1, sw2, sw3, swp, and three bias signals as shown in FIG. The signals pb, rb, b0 are supplied.

Hereinafter, a specific configuration example of the pixel cell PXx, y according to the first embodiment will be described with reference to FIGS. FIG. 5 is a schematic diagram showing a specific configuration example of the pixel cell PXx, y according to the first embodiment, and FIG.
FIG. 3 is a circuit diagram showing a specific configuration example of a pixel cell PXx, y according to the first embodiment using a MOS transistor.

As shown in the figure, this pixel cell PXx, y
Represents an input node NDIN, a photosensor unit PDS, a first source follower circuit SF11, a second source follower circuit SF12, a MOS resistor network RCN, a first capacitance element C11, a second capacitance element C12, and a third Capacitive element C1
3, the first switch element SW11, the second switch element SW12, the third switch element SW13, the fourth switch element SW14, the fifth switch element SW15, the first buffer BF11, the second buffer BF12, and It is composed of output terminals Tout1 and Tout2. The fourth switch element SW14 and the fifth switch element SW1
5, the first buffer BF11, the second buffer BF1
2, and the output terminals Tout1 and Tout2 constitute a part of the reading means.

The photo sensor unit PDS comprises a photodiode PD and an n-channel MOS (NMOS) transistor N
T111. The photodiode PD has an anode grounded, a cathode connected to the drain of the NMOS transistor NT111, and a source connected to the supply line of the power supply voltage V _DD . The switching signal swp is supplied to the gate of the NMOS transistor NT111. The cathode of the photodiode PD and the NMOS transistor NT111
An output node NDPDS of an image information signal EIM, which is an electric signal, is formed by a connection point with the drain of the pixel.

As shown in FIG. 7, the photodiode PD of the photo sensor unit PDS includes a capacitor Cpd and a current source Isrc.
Is replaced by a parallel circuit. Here, the current source Isrc
Is proportional to the light intensity. In the photo sensor unit PDS, the NMOS transistor NT111
Supplies a high-level switching signal swp to the gate of NM.
When the OS transistor NT111 is turned on, the capacitance Cpd
And the output voltage Vout11 is initialized as follows.

[0055]

Vout11 = V _DD −Vth (1)

Note that this initialization is performed during a time T1 after a lapse of a predetermined time from the time T0. Next, the switching signal sw
p is switched to low level, and the NMOS transistor N
When T111 is turned off, electric charge is discharged to the capacitor Cpd. Then, the output voltage after an appropriate time Ta (accumulation time) has elapsed is obtained as an output proportional to the light intensity as follows.

[0057]

Vout11 = V _DD −Vth− (1 / Cpd) × Iphoto × Ta (2)

In the photo sensor unit PDS,
By changing the accumulation time Ta, the output gain can be adjusted. The accumulation time Ta is set for a predetermined time from time T1. Also, an NMOS transistor NT as a switch
By applying a bias voltage to the gate of 111, it is possible to operate also as a logarithmic optical sensor.

Further, as shown in FIG. 8, the photosensor section PDS has a PM transistor instead of an NMOS transistor.
It is also possible to use the OS transistor PT111.
In this case, the output voltage Vout11 = _VDD at the time of initialization, and there is an advantage that the output voltage Vout11 is not affected by the variation in the threshold value of each MOS transistor. However, it cannot operate as a logarithmic optical sensor.

The first source follower circuit SF11 has a function of separating the photosensor unit PDS from the subsequent circuit, receives a predetermined level of the image information signal EIM output from the photosensor unit PDS, and Adjust and output.

This first source follower circuit SF11
The output level is equal to the threshold value Vth of the NMOS transistor NT111 when the photosensor PDS is initialized.
The PMOS transistors PT112 and PT11
3 is used. The drain of the PMOS transistor PT112 is connected to the supply line of the power supply voltage V _DD , the source is connected to the drain of the PMOS transistor PT113,
The source of the PMOS transistor PT113 is grounded. The bias signal pb is supplied to the gate of the PMOS transistor PT112, the gate of the PMOS transistor PT113 is connected to the output node NDPDS of the photosensor unit PDS, and the image information signal EIM, which is an electric signal, is supplied. The connection point between the source of the PMOS transistor PT112 and the drain of the PMOS transistor PT113 is connected to the output node N of the first source follower circuit SF11.
A DSF 11 is configured.

The output voltage Vout12 of the first source follower circuit SF11 has the level of the bias signal pb to the gate of the PMOS transistor PT112 of V (pb), and the photosensor PDS to the gate of the PMOS transistor PT112.
Is given by the following equation, where V (in) is the output level of

[0063]

Vout12 = V (in) + V _DD -V (pb) (3)

As described above, the photo sensor unit PDS is configured as a charge storage type, and the output of the photo sensor unit PDS is added with the source follower circuit, thereby forming an active pixel sensor (APS).

As shown in FIG. 8, when the photosensor section PDSa is formed by using the PMOS transistor PT111, the output rises to the power supply voltage V _DD level. As shown in FIG. 9, a circuit is used in which NMOS transistors NT112 and NT113 are connected in series between the supply line of the power supply voltage V _DD and the ground in place of the PMOS transistor.

In this case, the bias signal pb is supplied to the gate of the NMOS transistor NT113 connected to the ground side, and the NMOS transistor NT113 connected to the supply line side of the power supply voltage _VDD is supplied.
Photosensor PD on the gate of S transistor NT112
The output of S is provided.

The output voltage Vout13 of the source follower circuit is V (pb), the level of the bias signal pb to the gate of the NMOS transistor NT113, and V (pb), the output level of the photosensor unit PDS to the gate of the NMOS transistor NT112. in), it is given by the following equation.

[0068]

Vout13 = V (in) −V (pb) (4)

The first switch element SW11 operatively connects the output node NDSF11 of the first source follower circuit SF11 and the input node NDIN of the pixel cell according to the supply level of the switching signal sw0. First switch element SW
Numeral 11 comprises a PMOS transistor PT114, for example, as shown in FIG. Then, the switching signal sw0 is supplied to the gate of the PMOS transistor PT114. The switching signal sw0 is supplied at a low level until a predetermined time elapses from the input start time T1 of the image information to the input node NDIN, and the image information diffused to the first capacitive element C11 from the time T0 is stored for a predetermined time. It is set to the high level during the time t1 after a predetermined time from the time t0.

The MOS resistor network RCN includes a plurality (6 in the example of FIGS. 5 and 6) of MOS-system resistive elements MR1, MR2, M having one end node commonly connected to the input node NDIN.
R3, MR4, MR5, MR6 and a third source follower circuit SF13. The other end nodes n1, n2, n of the MOS resistance elements MR1 to MR6
3, n4, n5, and n6 are connected to the input nodes of the nearest six pixel cells, respectively. MOS resistance element MR
As shown in FIG. 6, 1 to MR6 are PMOS transistors PT115 and PT116 connected between the input node NDIN and nodes n1, n2, n3, n4, n5 and n6, respectively.
, PT117, PT118, PT119, PT120.

The third source follower circuit SF13 includes N
It is constituted by MOS transistors NT114 and NT115. The drain of the NMOS transistor NT114 is connected to the supply line of the power supply voltage V _DD , and the source is
Transistors PT115, PT116, PT117, PT11
8, PT119 and PT120 are commonly connected. The drain of the NMOS transistor NT115 is connected to the PMOS transistors PT115, PT116, PT117,
The gates of PT118, PT119, PT120 are commonly connected, and the sources are grounded. In this case, the bias signal rb is supplied to the gate of the NMOS transistor NT115 connected to the ground side, and the NMOS transistor NT112 connected to the supply line side of the power supply voltage V _DD connects the input node NDIN to each of the PMOS transistors PT115 to PT120. Connected to a connection point.

Then, the source follower circuit SF14
Output voltage Vout14, that is, the PMOS transistor P
Voltage Vout14 supplied to each gate of T115 to PT120
Sets the level of the bias signal pb to the gate of the NMOS transistor NT115 to V (pb),
The level of the input node NDIN to the gate of T114 is set to V (ND
in), it is given by the following equation.

[0073]

Vout14 = V (NDin) −V (rb) (5)

The PMOS transistors PT115 to PT120
Receives a voltage Vout14 at its gate, functions as a resistance element, and diffuses input image information input to an input node NDIN. This diffusion of the image information is performed by the switch element SW11.
Starts as soon as is turned on.

The first capacitance element C11 has one electrode connected to the input node NDIN, the other electrode grounded, and the switch element SW11 turned on to switch the input node ND.
The image information supplied to IN is stored.

The second source follower circuit SF12 has an M
The voltage value of the capacitor C11 in which the image information after the diffusion has been performed in the OS resistance network RCN is stored. The second source follower circuit SF12 includes NMOS transistors NT116 and NT117. N
The drain of the MOS transistor NT116 is connected to the power supply voltage V _DD
And the source is connected to the drain of the NMOS transistor NT117. And NM
The source of the OS transistor NT117 is grounded.
In this case, the NMOS transistor N connected to the ground side
The bias signal b0 is supplied to the gate of T117, and the NMOS transistor NT116 connected to the supply line side of the power supply voltage _VDD is connected to the input node NDIN and the first capacitor C11.
Is connected to a connection point with one of the electrodes.

Then, the source follower circuit SF12
The output voltage Vout15 of the NMOS transistor NT117
The level of the bias signal b0 to the gate of V (b0), NM
Input node ND to the gate of OS transistor NT114
Assuming that the level of IN, that is, the storage level after diffusion stored in the first capacitive element C11 is V (C11), it is given by the following equation.

[0078]

Vout15 = V (C11) −V (b0) (6)

The second switch element SW12 is connected to the output node NDSF12 of the second source follower circuit SF12 and the second capacitive element C1 according to the supply level of the switching signal sw1.
2. Operately connect to buffer BF11. Second
The switch element SW12 is formed of an NMOS transistor NT118, for example, as shown in FIG.
Then, the switching signal sw1 is supplied to the gate of the NMOS transistor NT118. The switching signal sw1 is at time T0
Is supplied at a low level until time t0 until the image information diffused to the first capacitive element C11 is stored for a predetermined time, and is supplied at a high level only during a time t2 after the time t1 after the time t1 and a predetermined time later. Is set to

The third switch element SW13 is connected to the output node NDSF12 of the third source follower circuit SF12 and the second capacitive element C1 according to the supply level of the switching signal sw2.
3. Operate the connection with the buffer BF12. Third
The switch element SW13 is formed of an NMOS transistor NT119, for example, as shown in FIG.
Then, the switching signal sw2 is supplied to the gate of the NMOS transistor NT119. The switching signal sw2 is at time T0.
From the time t0 until the time t0 until the image information diffused to the first capacitive element C11 is stored for a predetermined time, the time t1 from the time t0, and the time t3 after the time t2 and further after the predetermined time. Is set to high level only during

The second capacitive element C12 has one electrode connected to the output side of the second switch element SW12 and the input of the first buffer BF11, the other electrode grounded, and the first capacitive element C12. The image information stored and diffused in C11 is stored from time t0 to time t2 and output to the first buffer BF11.

The third capacitive element C13 has one electrode connected to the output side of the third switch element SW12 and the input of the first buffer BF12, the other electrode grounded, and the first capacitive element C13. The image information stored and diffused in C11 is stored from time t0 to time t3 and output to the second buffer BF12.

The first buffer BF11 outputs the information stored in the second capacitive element C12 at a predetermined level to the fourth switch element SW14. This first buffer BF11 is
As shown in FIG. 6, it is configured by a PMOS transistor PT121, and has a gate connected to a connection point between the output side of the second switch element SW12 and one electrode of the second capacitor element C12.

The second buffer BF12 outputs the information stored in the third capacitor C13 at a predetermined level to the fifth switch SW15. This second buffer BF12 is
As shown in FIG. 6, it is constituted by a PMOS transistor PT122, and the gate is connected to the connection point between the output side of the third switch element SW13 and one electrode of the third capacitance element C13.

The fourth switch element SW14 operatively connects the output of the first buffer BF11 and the output terminal Tout1 of the pixel cell according to the supply level of the switching signal sw3. The fourth switch element SW14 is composed of, for example, a PMOS transistor PT123 as shown in FIG. The switching signal sw3 is supplied to the gate of the PMOS transistor PT123. The switching signal sw3 is
The signal is supplied at a low level from a time slightly earlier than the time t0 until the next photosensor unit PDS is initialized.

The fifth switch element SW15 operatively connects the output of the second buffer BF12 and the output terminal Tout2 of the pixel cell according to the supply level of the switching signal sw3. The fourth switch element SW15 is composed of, for example, a PMOS transistor PT124 as shown in FIG. The switching signal sw3 is supplied to the gate of the PMOS transistor PT124 in common with the gate of the PMOS transistor PT123.

The PMOS transistor PT121 and the fourth switch element S constituting the first buffer BF11
The PMOS transistor PT123 constituting W14 is connected in series between the ground and the output terminal Tout1, as shown in FIG. Similarly, a PMOS transistor PT122 forming the second buffer BF12 and a PMOS transistor PT125 forming the fifth switch element SW15
Are connected in series between the ground and the output terminal Tout2 as shown in FIG.

The horizontal shift register 12 stores data Hdata including a column address of a pixel cell and a clock signal H.
In response to the clock, the switching signal sw3 is output at an active low level to the pixel cell PXx, y of the addressed column.

The vertical shift register 13 stores data Vdata including a row address of a pixel cell and a clock signal Vcl.
In response to the ock, the switch elements SWm, n, to which the outputs of the addressed row (row) pixel cells PXx, y are connected,
SWm + 1, n and SWm + 2, n are turned on, and the two outputs Vout1 and Vout2 of the selected pixel cell are respectively stored in the buffer 1
4, 15 are input.

The buffer 14 converts the analog output Vout1 of the selected pixel cell into an analog signal out1 of a predetermined level.
To the A / D converter 16. The buffer 15
The analog output Vout2 of the selected pixel cell is output to the A / D converter 17 as an analog signal out2 of a predetermined level.

The A / D converter 16 outputs the analog signal out.
1 is converted to a digital signal D16 and output to the arithmetic unit 18 for the fractal dimension of the digital signal. A / D converter 17
Converts the analog signal out2 into a digital signal D17 and outputs the digital signal D17 to the arithmetic unit 18 for calculating the fractal dimension of the digital signal.

The fractal dimension calculator 18 converts the digital signal D16 (image information after diffusion at time 2) from the A / D converter 16 and the digital signal D17 (image after diffusion at time 3) from the A / D converter 17. ), And obtains a local amount representing the complexity of the target image as shown below and outputs it as a signal S18.

[0093]

D ^* (＾ x) = Vout2 (D17) / Vout1 (D16) = Φ (＾ x, t3) / Φ (＾ x, t2) (7)

Here, ＾ x) is a coordinate, and D is a fractal dimension near the coordinate ＾ x, more precisely, a mass index, and a fractal dimension in which the sum of pixel densities within a radius r is defined by r ^D. Each is represented.

The reason why the fractal dimension due to diffusion can be obtained by simply taking the ratio of the diffused image information at certain two times will be described below.

When the density of pixels on a plane is distributed,
When it is diffused, it changes as follows.

[0097]

Φ (＾ x, t) ∝t ^{(D / 2) -1} (8)

Here, as described above, D is the fractal dimension near the coordinate ＾ x, more precisely, the mass index, and the fractal dimension in which the sum of the pixel densities within the radius r is defined by r ^D , and t is Each represents time.

Therefore, the fractal dimension at the coordinate ＾ x is given by the following equation.

[0100]

D ^* (＾ x) = 2 [｛d log Φ (＾ x, t)｝ / ｛d logt｝ +1] (9)

That is, the faster the way of attenuation when diffused, the lower the dimension, and the slower the way, the higher the dimension. For example, if only one point has a value, it is (1 / t); if there is a linear value, it is (1 / t ^1/2 ); if there is a uniform value over the entire plane, (t ⁰ ; no change) ).

When the fractal dimension itself having such characteristics is to be obtained by an integrated circuit, the following may be performed. That is, the image data {Φ ({x, 1)} given as the initial condition is stored. Next, the image ｛Φ (＾) given as an initial condition according to the diffusion equation
(x, 1)} image data {Φ ({x, t)}
Get. Then, by taking the ratio, the dimension is ideally obtained by the following equation regardless of the diffusion coefficient.

[0103]

D (＾ x) = 2 [log ｛Φ (＾ x, t) / Φ (＾ x, 1)｝ / logt｝ +1] (10)

Here, what is important is that the ratio between the diffused image data and the initial image data is determined. Actually, the fluctuation can be suppressed by inserting two observation times as follows, rather than using the initial data itself.

[0105]

D (＾ x) = 2 [log ｛Φ (＾ x, t3) / Φ (＾ x, t2)｝ / log (t 3 / t2)｝ + 1] (11)

The circuit IC according to the present embodiment is configured such that two observation times are provided based on the equation (11) so that fluctuation can be suppressed.

With the times t2 and t3 fixed, the log
If only emphasis is placed on the fact that is a monotonic function, the following quantities can be considered as local quantities representing complexity.

[0108]

D ^* (＾ x) = Φ (＾ x, t3) / Φ (＾ x, t2) (12)

The equation (12) is similar to the equation (7). Also, in order to reduce spatial fluctuations,
It is desirable to average the obtained values of D ^* . If the dimension value is negative, the value is ignored.

Next, the operation of the above configuration will be described focusing on the operation of one pixel cell PXm, n with reference to the timing chart of FIG.

First, as shown in FIG.
At 0, the switching signal swp is supplied at a high level to the gate of the NMOS transistor NT111 of the photo sensor unit PDS. Thereby, the NMOS transistor NT11
1 is turned on, and the output voltage Vou of the photo sensor PDS is
t11 is initialized to (V _DD -Vth). Next, at time T
The switching signal swp is switched to low to 1. As a result, the NMOS transistor NT111 is turned off, and the electric charge accumulated in the photodiode PD is discharged. As a result, the output voltage Vout11 of the photosensor unit PDS becomes a level proportional to the incident light intensity radiated from the target object, and is output to the first source follower circuit SF11.

In the first source follower circuit SF11,
The photosensor unit PDS is separated from the subsequent circuit, receives the image information signal EIM of a predetermined level output from the photosensor unit PDS, adjusts the level, and outputs the signal to the first switch element SW11.

At this time, PMs constituting the first switch
FIG. 10B shows the gate of the OS transistor PT114.
As shown in the figure, a low-level switching signal sw0 is supplied. Therefore, the PMOS transistor PT114 is on, and the image information of the level according to the light intensity via the first source follower circuit SF11 is input to the input node D.
Propagated to NIN. The charge corresponding to the image information transmitted to the input node NDIN is accumulated (stored) in the first capacitor C11. Then, as shown in FIG. 10C, the switching signal sw0 is switched from the low level to the high level from time t0 to time t1, and the photo sensor unit PD
A supply source of electrical image information composed of S and the first source follower circuit SF11 is electrically separated from the output node NDIN. Thereby, the electric charge accumulated in the first capacitance element C11 is gradually diffused in the MOS resistance network RCN. At this moment, the first capacitive element C11
As shown in (f), the image information output Vps (t1) by the photo sensor unit PDS is stored.

At time t0, the state shown in FIG.
As shown in the figure, the switching signal sw1 is at a high level until the time t2 and the NMO constituting the second switch element SW12 is
It is supplied to the gate of the S transistor NT118. As a result, the NMOS transistor NT118 is turned on until the time t2, and at the time t2, as shown in FIG.
The electric charge corresponding to the potential V11 (t2) = Vo1 between both electrodes of the first capacitor C11 via the second source follower circuit SF12 is accumulated in the second capacitor C12.

Similarly, at time t0, FIG.
As shown in (e), the switching signal sw2 is supplied to the gate of the NMOS transistor NT119 constituting the third switch element SW13 at a high level until time t3.
As a result, the NMOS transistor NT119 is turned on at time t3.
At time t3, as shown in FIG. 10 (f), via the second source follower circuit SF12.
Potential V11 (t3) = V between both electrodes of the capacitive element C11
The charge corresponding to o2 is stored in the third capacitor C13.

Further, based on the data Hdata including the column address of the pixel cell and the clock signal Hclock, the horizontal shift register 12 starts from the time slightly earlier than the time t0 until the next photosensor unit PDS is initialized. During this period, the switching signal sw3 is set to the low level and supplied to the gates of the PMOS transistors PT123 and PT124 constituting the fourth and fifth switch elements SW14 and SW15 of the pixel cell in the same column including the pixel cell PXm, n. Is done. Thus, the diffused image information at time t2 stored in the second capacitor C12 is output as the signal Vout1 through the first buffer BF11 and the fourth switch SW14. Similarly, the diffused image information at time t3 stored in the third capacitive element C13 is transferred to the third buffer BF12 and the fourth switch element S
The signal is output as a signal Vout2 through W15.

Further, in response to the data Vdata including the row address of the pixel cell and the clock signal Vclock, the output of the pixel cell including the addressed row (row) pixel cell PXm, nx is connected by the vertical shift register 13. The turned on switch element SWm, n is turned on. As a result, the two outputs Vout1 and Vout2 of the selected pixel cell are input to the buffers 14 and 15, respectively, and output to the A / D converters 16 and 17 as analog signals out1 and out2, respectively.

In the A / D converter 16, the analog signal ou
t1 is converted into a digital signal D16 and output to the arithmetic unit 18. Similarly, the A / D converter 17 converts the analog signal out2 into a digital signal D17 and
8 is output.

In the fractal dimension calculation unit 18,
Digital signal D16 (image information after diffusion at time 2) by A / D converter 16 and digital signal D17 (image information after diffusion at time 3) by A / D converter 17
Is obtained, a local amount representing the complexity of the target image is obtained, and output as a signal S18. .

The same operation as described above is repeated for each pixel cell.

As described above, according to the present embodiment, the pixel cells PXx, y including the photodiode PD are arranged in a matrix on the semiconductor chip IC, and in each pixel cell, the input image information by the photodiode PD Is diffused by a resistance network to obtain two different times t2 and T2.
Since the image information after the diffusion in step 3 is obtained and these ratios are calculated by the arithmetic unit 18, a numerical value corresponding to the fractal dimension can be easily obtained by the parallel analog processing. In other words, there is an advantage that an image data processing apparatus capable of obtaining a target image of data in a form close to nature can be realized, in addition to being able to perform processing in a short time with a simple configuration.

In this embodiment, the time t2 for storing and determining the image information diffused in the second capacitive element C12 and the time for storing and determining the image information diffused in the third capacitive element C13 Although the description has been given of the case where t3 is a fixed time, these times may be arbitrarily set and changed externally. As a result, a practical device can be realized.

Second Embodiment FIG. 11 is a diagram for explaining a second embodiment of the image information processing apparatus according to the present invention.

The difference between the second embodiment and the first embodiment is that a resistance element R11 is arranged between the input node NDIN and the ground in parallel with the first capacitance element C11. .

The resistance value of the resistance element R11 is set so that the time constant defined by the resistance value thereof and the capacitance value of the first capacitance element C11 is at least longer than the time T1 to the time t3. In this case, the input node NDIN is reset through the resistance element R11 before or during initialization of the photosensor unit PDS.

According to the second embodiment, the first
The same effect as that of the embodiment can be obtained.

The input node N is used as a reset circuit.
It is also possible to arrange a switch element between DIN and ground in parallel with the first capacitive element C11.

[0128]

As described above, according to the present invention,
In addition to being able to process with a simple configuration and in a short time, there is an advantage that an object image can be obtained from data in a form close to nature.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing a first embodiment of an image data processing device according to the present invention.

FIG. 2 is a diagram for explaining a principle configuration of a pixel cell array according to the present invention.

FIG. 3 is a diagram for explaining a principle configuration of a pixel cell according to the present invention.

FIG. 4 is a diagram illustrating an example of input / output signals of a pixel cell according to the first embodiment.

FIG. 5 is a schematic diagram showing a specific configuration example of a pixel cell PXx, y according to the first embodiment.

FIG. 6 shows an example in which the pixel cell PXx, y according to the first embodiment is
FIG. 9 is a circuit diagram illustrating a specific configuration example using an S transistor.

FIG. 7 is a diagram for explaining a function of a photo sensor unit.

FIG. 8 is a circuit diagram showing another example of the configuration of the photosensor unit.

9 is a circuit diagram showing a configuration of a first source follower circuit when the photo sensor unit having the configuration shown in FIG. 8 is used.

FIG. 10 is a timing chart for explaining the operation of the image information processing apparatus according to the first embodiment.

FIG. 11 is a diagram for explaining a second embodiment of the image data processing device according to the present invention.

[Explanation of symbols]

10 image information processing device, 11 pixel cell array, 12
... horizontal shift register, 13 ... vertical shift register, 1
4, 15 ... buffer, 16, 17 ... A / D converter, 18
... Fractal dimension calculator, PXx, y ... Pixel cell, ND
IN: Input node, PDS: Photo sensor unit, SF11 ...
First source follower circuit, SF12 ... second source follower circuit, RCN ... MOS resistor network, C11 ... first
C12, a second capacitance element, C13, a third capacitance element, SW11, a first switch element (input means), SW12, a second switch element (first means),
SW13: third switch element (second means), SW1
4: Fourth switch element, SW15: Fifth switch element, BF11: First buffer, BF12: Second buffer BF, Tout1, Tout2: Output terminals, PT111 to PT
124 ... PMOS transistor, NT111 to NT119 ... N
MOS transistor.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hideki Takayasu 3-14-13 Higashi Gotanda, Shinagawa-ku, Tokyo F-term (reference) in Sony Computer Science Laboratory 5B056 BB01 BB62 HH03

Claims (28)

[Claims] An input node to which information having an arbitrary level is input; a resistance network including at least one resistance element connected to the input node; a resistance network connected to the input node; A first capacitor for storing information given as an initial condition, a second capacitor, and information obtained by diffusing information supplied to the input node for a predetermined time in the resistor network, to the second capacitor. An information processing device having means for storing in an element. 2. An arithmetic unit for calculating a ratio between information given as an initial condition stored in the first capacitive element and information after diffusion stored in the second capacitive element. An information processing apparatus according to claim 1. 3. An analog / digital converter for converting analog information given as an initial condition stored in the first capacitive element and analog information after diffusion stored in the second capacitive element into a digital signal. The information processing apparatus according to claim 1, further comprising: a conversion unit; and an arithmetic unit that calculates a ratio between the digital information converted into a digital signal and provided as initial conditions and the spread digital information. 4. An input node to which information having an arbitrary level is input, a resistor network including at least one resistor connected to the input node, a first capacitor, and a second capacitor. An element, first means for storing, in the first capacitive element, information obtained by first spreading information supplied to the input node by the resistor network, and information supplied to the input node is Second means for storing, in the second capacitive element, information which has been diffused for a second time different from the first time in the resistance network, in the second capacitive element. 5. An arithmetic unit for calculating a ratio between the first time-spread information stored in the first capacitor and the second time-spread information stored in the second capacitor. The information processing apparatus according to claim 4, comprising: 6. Converting the first time-spread information stored in the first capacitor and the second time-spread information stored in the second capacitor into digital signals. 5. The information processing apparatus according to claim 4, further comprising: an analog / digital conversion unit; and an arithmetic unit for calculating a ratio between the first time-spread digital information converted into a digital signal and the second time-spread digital information. apparatus. 7. An input node, an optical sensor unit that receives light emitted from an object and generates information that is an electric signal corresponding to a light receiving level, and outputs information at an arbitrary level by the optical sensor unit. An input means for inputting a predetermined accumulation time to an input node; a resistance network including at least one resistance element connected to the input node; a resistance network connected to the input node; A first capacitive element for storing information supplied and diffused by the resistance network, a second capacitive element, a third capacitive element, and the first capacitive element for a first time after the accumulation time has elapsed. First means for storing the diffusion information stored in the second capacitive element in the second capacitive element; and storing the diffused information in the first capacitive element at a second time different from the first time after the lapse of the accumulation time. Spreading information memorized The third
An image information processing apparatus comprising: a second element for storing data in a capacitive element. 8. An arithmetic unit for calculating a ratio of spread information of the first time stored in the second capacitive element to spread information of the second time stored in the third capacitive element. The information processing device according to claim 7. 9. An analog / digital converter for converting the spread information of the first time stored in the second capacitive element and the spread information of the second time stored in the third capacitive element into a digital signal. The information processing apparatus according to claim 7, further comprising: a digital conversion unit; and a calculation unit that calculates a ratio between the digital spread information of the first time converted into the digital signal and the digital spread information of the second time. 10. An input node to which image information having an arbitrary level is input, a resistance network including at least one resistance element connected to the input node, and the input node connected to the input node. A first capacitor for storing image information given as an initial condition, a second capacitor, and image information obtained by diffusing image information supplied to the input node for a predetermined time in the resistor network. A pixel cell array in which a plurality of pixel cells including means for storing data in a second capacitance element are arranged in an array; a first capacitance element and a second capacitance of a pixel cell selected from the plurality of pixel cells; An image information processing apparatus comprising: a reading unit that reads image information stored in an element. 11. The image information given as an initial condition stored in the first capacitance element of the selected image cell read by the reading means, and the diffusion information stored in the second capacitance element. The image information processing apparatus according to claim 10, further comprising a calculation unit that calculates a ratio with the subsequent image information. 12. An analog image information provided as an initial condition stored in said first capacitor of a selected image cell read by said reading means, and stored in said second capacitor. Analog / digital conversion means for converting the analog image information after diffusion into a digital signal; an arithmetic unit for calculating a ratio between the digital image information given as initial conditions converted into the digital signal and the digital image information after diffusion The image information processing apparatus according to claim 10, comprising: 13. An input node to which image information having an arbitrary level is input, a resistance network including at least one resistance element connected to the input node, a first capacitance element, and a second capacitance element. A capacitor, first means for storing the image information supplied to the input node, the first time-spread image information in the resistor network being stored in the first capacitor, and supplying the image information to the input node. A second means for storing, in the second capacitor, image information obtained by diffusing the image information, which is different from the first time by the second time in the resistance network, in the second capacitor. An image information processing apparatus comprising: a pixel cell array arranged in a plurality of pixel cells; and reading means for reading image information stored in a first capacitance element and a second capacitance element of a pixel cell selected from the plurality of pixel cells. 14. A first image stored in the first capacitive element of a selected image cell read by the reading means.
14. The image information processing apparatus according to claim 13, further comprising an arithmetic unit that calculates a ratio between the time-spread image information and the second time-spread image information stored in the second capacitor. 15. The first image stored in the first capacitive element of the selected image cell read by the reading means.
Analog / digital converting means for converting the time-spread image information into the digital signal and the second time-spread image information stored in the second capacitive element, 14. The image information processing apparatus according to claim 13, further comprising: a calculation unit that calculates a ratio between the time-spread digital image information and the second time-spread digital image information. 16. An input node, an optical sensor unit for receiving light emitted from an object to generate image information as an electric signal according to a light receiving level, and image information for taking an arbitrary level by the optical sensor unit Input means for inputting the data to the input node, a resistance network including at least one resistance element connected to the input node, and image information connected to the input node and given to the input node as an initial condition. Means for storing the image information supplied to the input node and the image information obtained by diffusing the image information supplied to the input node for a predetermined time in the resistance network, in the second capacitance element. A pixel cell array in which a plurality of pixel cells including the following are arranged in an array; and information stored in a first capacitor and a second capacitor of a pixel cell selected from the plurality of pixel cells. Image information processing apparatus having a reading means for reading. 17. The image information given as an initial condition stored in the first capacitance element of the selected image cell read by the reading means, and the diffusion information stored in the second capacitance element. 17. The image information processing apparatus according to claim 16, further comprising a calculation unit that calculates a ratio with respect to subsequent image information. 18. The analog image information provided as an initial condition stored in the first capacitance element of the selected image cell read by the reading means, and stored in the second capacitance element. Analog / digital conversion means for converting the analog image information after diffusion into a digital signal; an arithmetic unit for calculating a ratio between the digital image information given as initial conditions converted into the digital signal and the digital image information after diffusion 17. The image information processing apparatus according to claim 16, comprising: 19. An input node, an optical sensor unit for receiving light emitted from an object to generate image information as an electric signal according to a light receiving level, and image information for taking an arbitrary level by the optical sensor unit Input to the input node, a resistor network including at least one resistor connected to the input node, a first capacitor, and a second capacitor.
And the image information supplied to the input node is first time-spread by the resistor network.
A second means for storing image information supplied to the input node in the resistor network, the image information being diffused for a second time different from the first time by the second means.
A pixel cell array in which a plurality of pixel cells including a second means for storing in the capacitance element are arranged in an array; a first capacitance element and a second capacitance element of a pixel cell selected from the plurality of pixel cells; An image information processing apparatus having reading means for reading information stored in a capacitor. 20. A first image stored in the first capacitor of a selected image cell read by the reading means.
20. The image information processing apparatus according to claim 19, further comprising an arithmetic unit that calculates a ratio between the time-spread image information and the second time-spread image information stored in the second capacitor. 21. A first image stored in the first capacitive element of a selected image cell read by the reading means.
Analog / digital converting means for converting the time-spread image information into the digital signal and the second time-spread image information stored in the second capacitive element, 20. The image information processing apparatus according to claim 19, further comprising: a calculation unit that calculates a ratio between the time-spread digital image information and the second time-spread digital image information. 22. An input node, an optical sensor unit that receives light emitted from an object to generate image information as an electric signal according to a light receiving level, and image information that takes an arbitrary level by the optical sensor unit Input means for inputting a predetermined storage time to the input node, a resistance network including at least one resistance element connected to the input node, and an input means connected to the input node, wherein the input is performed during the storage time. A first capacitive element for storing image information supplied to the node and diffused by the resistance network, a second capacitive element, a third capacitive element, and a first capacitive element for a first time after the accumulation time has elapsed. A first means for storing the diffusion information stored in the first capacitive element in the second capacitive element; and a first means for storing the first information at a second time different from the first time after the lapse of the accumulation time. Stored in the capacitive element A pixel cell array in which a plurality of pixel cells including a second means for storing the diffused information in the third capacitive element are arranged in an array; and a second cell of a selected one of the plurality of pixel cells An image information processing apparatus comprising: a readout unit that reads out information stored in a third capacitive element and a capacitive element. 23. The first image stored in the second capacitor of the selected image cell read by the reading means.
23. The image information processing apparatus according to claim 22, further comprising an arithmetic unit that calculates a ratio between the spread information of the second time and the spread information of the second time stored in the third capacitive element. 24. A first image stored in the second capacitor of a selected image cell read by the reading means.
Analog / digital conversion means for converting the time spread information of the first time and the spread information of the second time stored in the third capacitive element into a digital signal; 23. The image information processing apparatus according to claim 22, further comprising a calculation unit for calculating a ratio between the spread information and the digital spread information for the second time. 25. Information provided as an initial condition of information having an arbitrary level is stored, and information obtained by diffusing input information according to a predetermined diffusion equation is obtained. An information processing method that determines the fractal dimension by taking the ratio with the information after diffusion. 26. The information processing method according to claim 25, wherein the diffusion is performed on a resistance network. 27. First information at a first time at which input information having an arbitrary level is diffused for a predetermined time according to a predetermined diffusion equation, and after the first time, input information is predetermined according to a predetermined diffusion equation. An information processing method of obtaining second information at a second time that has been time-spread, obtaining a fractal dimension by taking a ratio of the first information and the second information. 28. The information processing method according to claim 27, wherein said diffusion is performed on a resistance network.