JP2001177244A - Method of manufacturing multilayered board - Google Patents
Method of manufacturing multilayered boardInfo
- Publication number
- JP2001177244A JP2001177244A JP35831599A JP35831599A JP2001177244A JP 2001177244 A JP2001177244 A JP 2001177244A JP 35831599 A JP35831599 A JP 35831599A JP 35831599 A JP35831599 A JP 35831599A JP 2001177244 A JP2001177244 A JP 2001177244A
- Authority
- JP
- Japan
- Prior art keywords
- thermal expansion
- expansion
- contraction
- manufacturing
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000008602 contraction Effects 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000010030 laminating Methods 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 229920000877 Melamine resin Polymers 0.000 description 1
- 239000004640 Melamine resin Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Landscapes
- Casting Or Compression Moulding Of Plastics Or The Like (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、多層板を製造する
際の多層化積層方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer laminating method for producing a multilayer board.
【0002】[0002]
【従来の技術】近年、プリント配線板の高密度化や高多
層化、薄型軽量化傾向により、ビルドアップ法による製
造や2種類の回路基板を貼り合わせて一体化する貼り合
わせ法による製造が増加してきた。特に貼り合わせ法に
は、内層回路板の上下に介されるプリプレグの厚みや、
性能が異なる配置の非対称構成4層板や3層板を用いる
ことが多い。この内層回路板の上下間に介されるプリプ
レグの厚みや、性能が異なる非対称構成の4層板は、積
層成形時に上下プリプレグ間で伸縮変化量の差を生じる
ため、同じプリプレグを内層回路板の上下に対称に配置
する対称構成の4層板に比べそりが大きく、仕上げ及び
加工する際にそりが問題となる。多層板のそりは、ガイ
ド穴加工する際に寸法の読み取り誤差を拡大させたり、
自動化された切断、端面仕上げライン上でのトラブルの
原因となり、更に自動板厚検査時の誤差要因にもなって
いる。これまで、そりによるトラブル対策としては、ラ
イン投入前の手作業や機械により、多層板を2枚の平行
板に挟んだり、凸型と凹型の間に挟んで加熱したりして
そりを直すことが行われてきた。2. Description of the Related Art In recent years, due to the tendency of printed wiring boards to have higher densities, higher multi-layers, and thinner and lighter weights, production by a build-up method or by a lamination method in which two types of circuit boards are laminated and integrated are increasing. I've been. In particular, in the laminating method, the thickness of the prepreg interposed above and below the inner circuit board,
In many cases, a four-layer plate or a three-layer plate with an asymmetric configuration having different performances are used. The thickness of the prepreg interposed between the upper and lower portions of the inner layer circuit board and the four-layer plate having an asymmetrical configuration having different performances cause a difference in the amount of expansion and contraction between the upper and lower prepregs during lamination molding. The warpage is larger than that of a four-layer plate having a symmetrical configuration arranged symmetrically, and warpage is a problem when finishing and processing. The warpage of the multilayer board can increase the size reading error when machining the guide holes,
This causes troubles on automated cutting and edge finishing lines, and also causes errors in automatic thickness inspection. Until now, as a countermeasure against warping caused by warping, the multilayer board was sandwiched between two parallel plates or heated between the convex and concave molds, and the warpage was corrected by manual work or machine before line introduction. Has been done.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな対応では修正にかける時間や労力が必要となる上、
製品の取り扱いへの注意が必要であり、取り扱い不備に
よるきず不良の発生が懸念される。更に、従来の方法で
修正すると、変形、折れ等を誘発させてしまう。また、
そりの根本対策になっていないという問題があった。非
対称構成多層板のそりは、加熱加圧成形時の内層回路板
の上下に介されるプリプレグの伸縮量に差が出ることが
要因の一つであり、この伸縮量の差を少なくする必要が
ある。本発明は、かかる観点にたってなされたもので、
そりの少ない非対称構成の多層板の製造方法を提供する
ことを目的とする。However, such measures require time and effort for correction, and
It is necessary to pay attention to the handling of the product, and there is a concern that defective defects may occur due to improper handling. Further, modification by a conventional method induces deformation, breakage, and the like. Also,
There was a problem that it was not a fundamental measure for sleds. One of the causes of the warpage of the asymmetrically configured multilayer board is that the difference in the amount of expansion and contraction of the prepreg interposed between the top and bottom of the inner layer circuit board during heating and pressing is one of the factors, and it is necessary to reduce the difference in the amount of expansion and contraction. . The present invention has been made from such a viewpoint,
An object of the present invention is to provide a method of manufacturing a multilayer board having an asymmetric configuration with less warpage.
【0004】[0004]
【課題を解決するための手段】すなわち本発明は、内層
回路板の上下に配するプリプレグの伸縮量に差が生じる
非対称構成の多層板の製造法において、多層化する積層
材料の上下に熱膨張係数が異なる鏡板を配置して積層成
形することを特徴とする多層板の製造方法に関する。That is, the present invention relates to a method of manufacturing a multilayer board having an asymmetrical structure in which the amount of expansion and contraction of a prepreg arranged above and below an inner circuit board is different. The present invention relates to a method for manufacturing a multilayer board, comprising arranging end plates having different coefficients and laminating them.
【0005】[0005]
【発明の実施の形態】本発明に使用する鏡板は、一般的
に市販されている積層板成形用のSUS301やSUS
630等の材質のものでも、使用材料の伸縮量に合わせ
て他の材質のものを使用しても構わない。鏡板の熱膨張
係数差は、SUS301の熱膨張係数10.5〜11.
2×10-6及びSUS630の熱膨張係数14.6〜1
6.8×10-6を考慮して3×10-6以上あることが好
ましいが、使用材料によってはこれ以下でも構わない。
また、プリプレグの伸縮変化量に応じて鏡板の材質を変
更する等の方法で熱膨張係数を調整することが好まし
い。本発明に用いるプリプレグは、従来公知のものが適
宜使用可能であり、具体的には、基材として、ガラス織
布、ガラス不織布等が使用可能であり、前記基材に含浸
させる樹脂としては、エポキシ樹脂系、ポリイミド樹脂
系、トリアジン樹脂系、フェノール樹脂系、不飽和ポリ
エステル樹脂系、メラミン樹脂系およびこれら樹脂の変
性系樹脂を用いることができる。更に、前記樹脂を2種
類以上併用したり、必要に応じて公知の各種硬化剤、硬
化促進剤を併用してもよい。本発明に用いる内層回路板
としては、特に制約はないが、経済性および電気的信頼
性から銅張積層板の銅をエッチングにより、回路加工し
たものを用いることができる。プリプレグは、内層回路
板と外層用金属箔との接着用として、温度150℃〜2
00℃、圧力1〜6MPa程度の範囲で加熱加圧して多
層プリント配線板とされる。使用プリプレグに対する鏡
板の選択は、伸縮変化の大きい側に熱膨張係数の小さい
鏡板、伸縮変化の小さい側に熱膨張係数の大きい鏡板を
基本とする。こうして、鏡板の熱膨張係数の差を利用し
てプリプレグの伸縮変化量を制御することで、そりの少
ない非対称構成多層板を製造することができる。以下、
本発明を実施例を示した図面を参照しながら具体的に説
明するが、本発明はこれに限定されるものではない。BEST MODE FOR CARRYING OUT THE INVENTION A head plate used in the present invention is a commercially available SUS301 or SUS for forming a laminated plate.
A material such as 630 may be made of another material according to the amount of expansion and contraction of the material used. The difference between the thermal expansion coefficients of the head plates is 10.5-11.
Thermal expansion coefficient of 2 × 10- 6 and SUS630 14.6-1
It is preferred that 3 × 10- 6 or more in consideration of 6.8 × 10- 6 but may even lower than this, depending on the material used.
Further, it is preferable to adjust the coefficient of thermal expansion by a method such as changing the material of the head plate according to the amount of change in expansion and contraction of the prepreg. As the prepreg used in the present invention, conventionally known ones can be appropriately used.Specifically, as a substrate, a glass woven fabric, a glass nonwoven fabric, or the like can be used, and as the resin to be impregnated into the substrate, Epoxy resin, polyimide resin, triazine resin, phenol resin, unsaturated polyester resin, melamine resin, and modified resins of these resins can be used. Further, two or more kinds of the above resins may be used in combination, or if necessary, various known curing agents and curing accelerators may be used in combination. The inner layer circuit board used in the present invention is not particularly limited, but may be a circuit board processed by etching copper of a copper-clad laminate from the viewpoint of economy and electrical reliability. The prepreg is used for bonding the inner layer circuit board and the outer layer metal foil at a temperature of 150 ° C to 2 ° C.
The multilayer printed wiring board is formed by heating and pressing at a temperature of 00 ° C. and a pressure of about 1 to 6 MPa. The selection of a head plate for a prepreg to be used is based on a head plate having a small thermal expansion coefficient on the side where the expansion and contraction change is large, and a head plate having a large thermal expansion coefficient on the side where the expansion and contraction change is small. In this way, by controlling the amount of expansion and contraction of the prepreg by utilizing the difference in the coefficient of thermal expansion between the head plates, it is possible to manufacture an asymmetric multilayer board with less warpage. Less than,
The present invention will be specifically described with reference to the drawings showing embodiments, but the present invention is not limited to these.
【0006】[0006]
【実施例】実施例 ガラス布基材エポキシ樹脂銅張積層板(FR−4、0.
14mm、18μm銅箔)にエッチドフォイル法で一般
的に用いる感光性フィルムをラミネートし、回路形成用
のネガフィルムを使用して焼付作業(露光)した後、エ
ッチング処理及び回路表面を酸化処理して内層回路板を
得た。ついで図1に示すように、内層回路板1の上側
(F面)に厚み0.06mmのガラス布−エポキシプリ
プレグ2(日立化成工業(株)製商品名:GE−67
L)、プリプレグ2の上に12μmの銅箔4、その上に
SUS630材質の鏡板6を配置し、内層回路板1の下
側(B面)に厚み0.10mmのガラス布−エポキシプ
リプレグ3(日立化成工業(株)製商品名:GE−67
3NA5L)、プリプレグ3の下に18μm銅箔5、そ
の下にSUS301材質の鏡板7を配置した以外は標準
的な構成とし、減圧雰囲気下、40kg/cm2、17
0℃で90分間加熱加圧した後、30分間冷却して製品
サイズ600×500mmの4層板を得た。EXAMPLE An epoxy resin copper-clad laminate of glass cloth base material (FR-4, 0.
After laminating a photosensitive film generally used by an etched foil method on a 14 mm, 18 μm copper foil) and performing printing (exposure) using a negative film for forming a circuit, etching treatment and oxidation treatment of the circuit surface are performed. To obtain an inner circuit board. Next, as shown in FIG. 1, a 0.06 mm-thick glass cloth-epoxy prepreg 2 (trade name: GE-67, manufactured by Hitachi Chemical Co., Ltd.) is provided on the upper side (F side) of the inner circuit board 1.
L), a 12 μm copper foil 4 on the prepreg 2, a mirror plate 6 made of SUS630 thereon, and a glass cloth-epoxy prepreg 3 (0.10 mm thick) on the lower side (side B) of the inner circuit board 1 ( Product name: GE-67, manufactured by Hitachi Chemical Co., Ltd.
3NA5L), a standard configuration except that an 18 μm copper foil 5 under the prepreg 3 and an end plate 7 made of SUS301 under the copper foil 5, under a reduced pressure atmosphere, 40 kg / cm 2 , 17
After heating and pressing at 0 ° C. for 90 minutes, the mixture was cooled for 30 minutes to obtain a four-layer plate having a product size of 600 × 500 mm.
【0007】比較例1 使用する鏡板の材質を上下ともSUS301としたこと
以外は、全て実施例と同一の方法で4層板を得た。Comparative Example 1 A four-layer plate was obtained in the same manner as in the example except that the upper and lower end plates were made of SUS301.
【0008】比較例2 使用する鏡板の材質を上下ともSUS630としたこと
以外は、全て実施例と同一の方法で4層板を得た。Comparative Example 2 A four-layer plate was obtained in the same manner as in the example except that the upper and lower end plates were made of SUS630.
【0009】実施例及び比較例1、2により製造した4
層板のそり、作業性への影響について評価した。その結
果を表1に示す。表1においてそり量は定盤の上にそり
面を下にして載置し、定盤と製品端部の最大跳上り寸法
をダイヤルゲ−ジで測定した。また、ライン上のトラブ
ルとは製品のそりのために搬送する際に他の設備に接触
してライン停止や製品に傷がつく現象をいう。Examples 4 and 4 prepared according to Comparative Examples 1 and 2
The warpage of the layer plate and the effect on workability were evaluated. Table 1 shows the results. In Table 1, the amount of warpage was set on the surface plate with the sled surface facing down, and the maximum jump size of the surface plate and the end of the product was measured with a dial gauge. In addition, the trouble on the line refers to a phenomenon in which the line stops or the product is damaged due to contact with other equipment when the product is transported for warpage.
【0010】[0010]
【表1】 [Table 1]
【0011】[0011]
【発明の効果】本発明の製造方法によれば、そりの小さ
い非対称構成多層板を得ることができ、そり直し作業を
必要とすることなく、しかも、そりによる仕上げ、加工
ライン上のトラブルを低減することができる。According to the manufacturing method of the present invention, it is possible to obtain a multilayer board having an asymmetric configuration with a small warpage, without the need for a re-warping operation, and to reduce troubles caused by the warping and finishing work. can do.
【図1】 本発明の実施例の多層化積層時の構成を示す
断面図。FIG. 1 is a cross-sectional view showing a configuration of an embodiment of the present invention at the time of multi-layer lamination.
1 内層回路板 2 厚み0.06mmプリプレグ 3 厚み0.10mmプリプレグ 4 厚み12μm銅箔 5 厚み18μm銅箔 6 SUS630鏡板 7 SUS301鏡板 8 クッション材 9 上板 10 送り板 11 熱板 Reference Signs List 1 inner layer circuit board 2 thickness 0.06 mm prepreg 3 thickness 0.10 mm prepreg 4 thickness 12 μm copper foil 5 thickness 18 μm copper foil 6 SUS630 end plate 7 SUS301 end plate 8 cushion material 9 upper plate 10 feed plate 11 hot plate
Claims (3)
縮量に差が生じる非対称構成の多層板の製造法におい
て、多層化する積層材料の上下に熱膨張係数が異なる鏡
板を配置して積層成形することを特徴とする多層板の製
造方法。1. A method for manufacturing a multilayer board having an asymmetric configuration in which a difference in the amount of expansion and contraction of prepregs arranged above and below an inner circuit board is provided, wherein mirror plates having different thermal expansion coefficients are arranged above and below a multilayer material to be multilayered. A method for producing a multilayer board, comprising forming.
×10-6以上あることを特徴とする請求項1記載の多層
板の製造方法。2. The method according to claim 1, wherein the difference between the thermal expansion coefficients of the head plates used up and down is 3
Method for manufacturing a multilayer board according to claim 1, wherein the certain × 10- 6 or more.
の大きい側に熱膨張係数の小さい鏡板を、伸縮変化の小
さい側に熱膨張係数の大きい鏡板を配置することを特徴
とする請求項1又は2記載の多層板の製造方法。3. A head plate having a small thermal expansion coefficient is disposed on a side of the prepreg having a large expansion and contraction change via an inner circuit board, and a head plate having a large thermal expansion coefficient is disposed on a side of a small expansion and contraction change. 3. The method for producing a multilayer board according to 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35831599A JP2001177244A (en) | 1999-12-17 | 1999-12-17 | Method of manufacturing multilayered board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35831599A JP2001177244A (en) | 1999-12-17 | 1999-12-17 | Method of manufacturing multilayered board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001177244A true JP2001177244A (en) | 2001-06-29 |
Family
ID=18458669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP35831599A Pending JP2001177244A (en) | 1999-12-17 | 1999-12-17 | Method of manufacturing multilayered board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001177244A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100755547B1 (en) | 2004-11-22 | 2007-09-06 | 이 아이 듀폰 디 네모아 앤드 캄파니 | Process for the constrained sintering of a pseudo-symmetrically configured low temperature cofired ceramic structure |
JP2013016835A (en) * | 2010-11-18 | 2013-01-24 | Sumitomo Bakelite Co Ltd | Insulating substrate, metal-clad laminate, printed wiring board, and semiconductor device |
KR101376950B1 (en) | 2012-12-28 | 2014-03-20 | 삼성전기주식회사 | Double plate using in substrate pressing and method for pressing substrate |
JP2015145115A (en) * | 2014-02-04 | 2015-08-13 | 日立化成株式会社 | Method for producing metal-clad laminated plate, and metal-clad laminated plate |
CN107734852A (en) * | 2017-09-22 | 2018-02-23 | 郑州云海信息技术有限公司 | A kind of pcb board design method and pcb board for realizing uniformly folded structure machinability |
CN109287080A (en) * | 2018-11-13 | 2019-01-29 | 梅州市志浩电子科技有限公司 | The compression method of asymmetric core plate and asymmetric core plate |
-
1999
- 1999-12-17 JP JP35831599A patent/JP2001177244A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100755547B1 (en) | 2004-11-22 | 2007-09-06 | 이 아이 듀폰 디 네모아 앤드 캄파니 | Process for the constrained sintering of a pseudo-symmetrically configured low temperature cofired ceramic structure |
JP2013016835A (en) * | 2010-11-18 | 2013-01-24 | Sumitomo Bakelite Co Ltd | Insulating substrate, metal-clad laminate, printed wiring board, and semiconductor device |
KR101376950B1 (en) | 2012-12-28 | 2014-03-20 | 삼성전기주식회사 | Double plate using in substrate pressing and method for pressing substrate |
JP2015145115A (en) * | 2014-02-04 | 2015-08-13 | 日立化成株式会社 | Method for producing metal-clad laminated plate, and metal-clad laminated plate |
CN107734852A (en) * | 2017-09-22 | 2018-02-23 | 郑州云海信息技术有限公司 | A kind of pcb board design method and pcb board for realizing uniformly folded structure machinability |
CN109287080A (en) * | 2018-11-13 | 2019-01-29 | 梅州市志浩电子科技有限公司 | The compression method of asymmetric core plate and asymmetric core plate |
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