JP2001168195A - Multilayer wiring semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce crosstalk between different layer wiring and improve wiring efficiency. SOLUTION: First and second layer wiring are formed on orthogonal grids 11, 12. When θ=arctan(na/mb) is established using first and second layer wiring pitches (a, b) and even number n, m exceeding 2, third and fourth layer wiring are formed on inclined grids 13, 14, so that they can incline in the positive and negative θdirection against the first layer wiring, respectively. Third and fourth layer wiring pitches (c, d) are C=d=na×mb/ (na)2+(mb)2}1/2. All the intersections of the third and fourth wiring are located at the position where they overlap with the intersections of the orthogonal grids 11, 12. Fifth and sixth layer wiring are formed on coarse orthogonal grids 15, 16 that form a subset of the orthogonal grids 11, 12. Fifth and sixth layer wiring pitches (e, f) are e=na and f=mb, and all the intersections of the fifth and sixth wiring are located at the position where they overlap with the intersections of the inclined girds 13, 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer wiring structure in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Advances in automatic design technology using a computer and advances in multilayer wiring process technology are factors that have enabled a dramatic increase in the degree of integration of semiconductor integrated circuits. In recent process technology, a low-resistance material such as a copper wiring is used, and the wiring thickness tends to be thin. Therefore, crosstalk caused by capacitance between different-layer wirings has become a problem.

[0003] JP-A-2-262354, JP-A-9-1
Nos. 48444 and 9-162279 disclose a conventional four-layer wiring structure. According to this, the wirings of the first and second layers are formed on an orthogonal grid so as to be orthogonal to each other, and the wiring of the third layer is formed of the first or second wiring.
The wiring of the fourth layer is formed on the inclined grid so as to be inclined at +45 degrees with respect to the wiring of the first layer, and the wiring of the fourth layer is inclined at -45 degrees with respect to the wiring of the first or second layer. In addition, in order to reduce the level difference between the portion where the wiring overlaps and the portion where the wiring does not overlap, the intersection of the third and fourth layers of wiring is shifted from the intersection of the orthogonal grid of the first and second layers of wiring. It was supposed to be.

[0004]

However, in a fine process, a stack via that allows overlapping of through holes (contacts) between different layers can be generally used by a flattening technique (CMP technique). There is no need to take a wiring structure. Further, in the wiring structure as described above, the adjacent holes hinder the use of other holes, and as a result, the wiring efficiency is reduced.

An object of the present invention is to provide a semiconductor integrated circuit having a wiring structure that reduces crosstalk between different-layer wirings due to miniaturization and improves wiring efficiency.

[0006]

In order to achieve the above object, the present invention employs a multi-layer wiring structure in which orthogonal grids and inclined grids are alternately employed, and all the intersections of the upper wiring are formed by the lower wiring grid. It was decided to be in the position which overlaps with the intersection.

More specifically, the invention of claim 1 is:
In a multilayer wiring semiconductor integrated circuit having a wiring structure of at least six layers, the first and second layers of wiring are formed on an orthogonal grid so as to be orthogonal to each other, and the unit wiring pitches of the first and second layers are respectively set to a and b, n and m are each an even number of 2 or more, and arctan (na / mb)
If the angle equal to θ is θ, the wiring of the third layer is inclined in the + θ direction with respect to the wiring of the first or second layer, and
The wiring of the layer is formed on the inclined grid so as to be inclined in the -θ direction with respect to the wiring of the first or second layer, and the unit wiring pitches of the third and fourth layers are set to c and d, respectively. Then, c = d = na × mb / {(na) ² + (mb) ² }
^1/2 , all the intersections of the wirings of the third and fourth layers are located at positions overlapping the intersections of the orthogonal grids of the wirings of the first and second layers, and the wirings of the fifth and sixth layers are Assuming that the unit wiring pitches of the fifth and sixth layers are e and f, they are formed on a coarse orthogonal grid which is a subset of the orthogonal grids of the wirings of the first and second layers. = Mb, and all the intersections of the wirings of the fifth and sixth layers are the third and fourth wirings.
This is at a position overlapping the intersection of the inclined grid of the wiring of the layer.

According to a second aspect of the present invention, there is provided a multilayer wiring semiconductor integrated circuit having a wiring structure of at least four layers.
The wiring of the second layer is formed on an orthogonal grid so as to be orthogonal to each other, unit pitches of the first and second layers are a and b, respectively, and n and m are each an even number (where n , M is an even number of 4 or more) and an angle equal to arctan (na / mb) is θ, the third layer wiring is + θ with respect to the first or second layer wiring. Direction and the fourth layer wiring is the first or second wiring.
It is formed on the inclined grid so as to be inclined in the -θ direction with respect to the wiring of the layer, and when the unit wiring pitches of the third and fourth layers are c and d, c = d = na × mb /
｛(Na) ² + (mb) ² ｝ ^1/2 , and all intersections of the third and fourth layers of wiring overlap the intersections of the orthogonal grids of the first and second layers of wiring It is to be in.

According to a third aspect of the present invention, in a multilayer wiring semiconductor integrated circuit having a wiring structure of at least four layers, the wirings of the first and second layers are orthogonal to each other in any of the first and second regions adjacent to each other. Are formed on a common orthogonal grid, and the unit wiring pitches of the first and second layers are respectively set to a
And b, n and m are each an even number of 2 or more, and an angle equal to arctan (na / mb) is θ, the third-layer wiring in the first region is the first or second-layer wiring. The wiring of the fourth layer is formed on the inclined grid so as to be inclined in the + θ direction with respect to the wiring, and the wiring of the fourth layer is inclined in the −θ direction with respect to the wiring of the first or second layer. When the unit wiring pitches of the third and fourth layers are c and d, c = d = na × mb / ｛(na) ² + (m
b) ² ｝ ^1/2 , and in the second region, the wirings of the third and fourth layers are formed on a coarse orthogonal grid which is a subset of the orthogonal grids of the wirings of the first and second layers, and , All the intersections of the third and fourth layers of wiring in the first and second regions are located at positions overlapping the intersections of the orthogonal grids of the first and second layers of wiring.

According to a fourth aspect of the present invention, in the multilayer wiring semiconductor integrated circuit according to the third aspect of the present invention, the unit wiring pitches of the third and fourth layers in the second region are set to na and mb, respectively.
It is what it was.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1A shows a wiring structure of the first to fourth layers of a six-layer wiring semiconductor integrated circuit according to a first embodiment of the present invention. (B) schematically shows the wiring structure from the third layer to the sixth layer of the same semiconductor integrated circuit. In the figure, reference numeral 10 denotes a layout area, and reference numerals 11 to 16 denote grid lines (priority wiring directions) from the first layer wiring to the sixth layer wiring.

In this embodiment, the first and second layers of wiring are formed on orthogonal grids 11 and 12 so as to be orthogonal to each other, and the unit wiring pitch of the first and second layers is set to a.
And b (where a = b), n and m are each an even number of 2 or more, and an angle equal to arctan (na / mb) is θ, the wiring of the third layer is The third and fourth wirings are formed on the inclined grids 13 and 14 so as to be inclined in the + θ direction with respect to the wiring and the fourth wiring is inclined in the −θ direction with respect to the first wiring. When the unit wiring pitch of the fourth layer is c and d, c = d =
na × mb / ｛(na) ² + (mb) ² ｝ ^1/2 , and all the intersections of the third and fourth wiring layers are orthogonal grids 11 and 12 of the first and second wiring layers. And the wirings of the fifth and sixth layers are formed on coarse orthogonal grids 15 and 16 which form a subset of the orthogonal grids 11 and 12 of the wirings of the first and second layers. Assuming that the unit wiring pitches of the fifth and sixth layers are e and f, respectively, e = na and f = mb, and all the intersections of the wirings of the fifth and sixth layers are the third and the fourth. Inclined grids 13 and 1 for fourth layer wiring
4 is located at a position overlapping the intersection. In the illustrated example, since a = b and n = m = 2, θ is 45 degrees, c = d = 2 ^1/2 × a = 1.41 × a, and e = f = 2a.
It is.

According to this embodiment, since there is no long-distance wiring running in parallel between adjacent wiring layers, crosstalk between different-layer wirings due to miniaturization can be reduced. Further, by using the stack via at the intersection of each wiring, through holes in different layers can be formed without waste, and wiring efficiency is improved. Also,
The higher wiring layer has a wider pitch and the lower wiring layer has a narrower pitch, which not only conforms to the conditions of the manufacturing process, but is also advantageous in reducing crosstalk between wiring in the same layer in the upper wiring layer. It is. Furthermore, since the grid lines 13 of the third layer wiring and the grid lines 14 of the fourth layer wiring are orthogonal to each other, not only the first and second layers and the fifth to sixth layers, but also the third to fourth layers. Even in the layer, automatic routing can be performed by a route search method on a “grid” based on the conventional maze routing method. Adopting the oblique wiring in the third and fourth layers also has the effect of reducing the wiring length.

In this embodiment, grid lines 15 and 16 of the fifth and sixth layer wirings are regarded as grid lines of the first and second layer wirings, respectively, and upper wiring layers having the same relation as described above are further stacked. This makes it possible to realize an arbitrary number of multi-layer wirings at small wiring pitches such as ^21/2 times, 2 times, 2 × 2 ^1/2 times, and 4 times the first layer unit wiring pitch a.

(Second Embodiment) FIG. 2A shows the wiring structure of the first to fourth layers of a six-layer wiring semiconductor integrated circuit according to a second embodiment of the present invention. (B) schematically shows the wiring structure from the third layer to the sixth layer of the same semiconductor integrated circuit. In the figure, reference numeral 10 denotes a layout area, and reference numerals 11 to 16 denote grid lines (priority wiring directions) from the first layer wiring to the sixth layer wiring.

In this embodiment, the first and second layers of wiring are formed on orthogonal grids 11 and 12 so as to be orthogonal to each other, and the unit wiring pitch of the first and second layers is a
And b (where a <b), n and m are each an even number of 2 or more, and an angle equal to arctan (na / mb) is θ, the wiring of the third layer is the wiring of the first layer The third and fourth wirings are formed on the inclined grids 13 and 14 so as to be inclined in the + θ direction with respect to the wiring and the fourth wiring is inclined in the −θ direction with respect to the first wiring. When the unit wiring pitch of the fourth layer is c and d, c = d =
na × mb / ｛(na) ² + (mb) ² ｝ ^1/2 , and all the intersections of the third and fourth wiring layers are orthogonal grids 11 and 12 of the first and second wiring layers. And the wirings of the fifth and sixth layers are formed on coarse orthogonal grids 15 and 16 which form a subset of the orthogonal grids 11 and 12 of the wirings of the first and second layers. Assuming that the unit wiring pitches of the fifth and sixth layers are e and f, respectively, e = na and f = mb, and all the intersections of the wirings of the fifth and sixth layers are the third and the fourth. Inclined grid 13, 1 for fourth layer wiring
4 is located at a position overlapping the intersection. In the illustrated example, since a <b and n = m = 2, θ is a positive angle smaller than 45 degrees, and e = 2a and f = 2b.

According to the present embodiment, since there is no long-distance wiring running in parallel between adjacent wiring layers, crosstalk between different-layer wirings due to miniaturization can be reduced. Further, by using the stack via at the intersection of each wiring, through holes in different layers can be formed without waste, and wiring efficiency is improved. Also,
The higher wiring layer has a wider pitch and the lower wiring layer has a narrower pitch, which not only conforms to the conditions of the manufacturing process, but is also advantageous in reducing crosstalk between wiring in the same layer in the upper wiring layer. It is.

The grid lines 15 and 16 of the fifth and sixth layer wirings in the present embodiment are regarded as grid lines of the first and second layer wirings, respectively, and upper wiring layers having the same relationship as described above are further stacked. Thus, an arbitrary number of multilayer wirings can be realized.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
4 schematically shows a wiring structure of a four-layer wiring semiconductor integrated circuit according to the embodiment. In the figure, reference numeral 10 denotes a layout area, and reference numerals 11 to 14 denote grid lines (priority wiring directions) from the first layer wiring to the fourth layer wiring.

In this embodiment, the first and second layers of wiring are formed on orthogonal grids 11 and 12 so as to be orthogonal to each other, and the unit wiring pitch of the first and second layers is set to a.
And b, and n and m are each an even number of 2 or more (however,
one of n and m is an even number of 4 or more) and ar
When an angle equal to ctan (na / mb) is θ,
The wiring of the third layer is inclined in the + θ direction with respect to the wiring of the first layer, and the wiring of the fourth layer is-with respect to the wiring of the first layer.
When formed on the inclined grids 13 and 14 so as to be inclined in the θ direction and the unit wiring pitches of the third and fourth layers are c and d, c = d = na × mb / ｛(na)
² + (mb) ² ｝ ^1/2 , and all the intersections of the wirings of the third and fourth layers are located at positions overlapping the intersections of the orthogonal grids 11 and 12 of the wirings of the first and second layers. I decided to be. In the specific example shown, a = b, n = 2 and m = 4,
θ is a positive angle smaller than 45 degrees, and c = d = 4 × 5
Is ^{1/2 × a = 1.78 ×} a.

According to this embodiment, since there is no long-distance wiring running in parallel between adjacent wiring layers, crosstalk between different-layer wirings due to miniaturization can be reduced. Further, by using the stack via at the intersection of each wiring, through holes in different layers can be formed without waste, and wiring efficiency is improved.

Under the condition of a = b, for example, n = 2
If m = 2 (see FIG. 1A), c = d = 2 ^1/2 ×
If a = 1.41 × a and n = 2 and m = 4 (see FIG. 3), then c = d = 4 × 5 ^1/2 × a = 1.78 × a, n = 2 and m If = 6, c = d = 6 × 10 ^1/2 × a
= 1.89 × a. That is, the unit wiring pitches c and d of the third and fourth layers are set to 1.41 of the unit wiring pitch a of the first layer.
It can be set in small increments from double to double. Therefore, the crosstalk between the wirings in the same layer can also be controlled and suppressed in small increments.

(Fourth Embodiment) FIG. 4A is a block diagram showing the overall configuration of a four-layer wiring semiconductor integrated circuit according to a fourth embodiment of the present invention, and FIG. FIG. 2 is an enlarged schematic diagram illustrating a part of a wiring structure in the integrated circuit. In the figure, reference numeral 20 denotes the four-layer wiring semiconductor integrated circuit;
Represents a functional block (first area) composed of basic logic cells,
Reference numeral 22 denotes a hard block such as a ROM / RAM, 23 denotes an IO cell, and 24 denotes a wiring area between blocks (second area).
Numeral 10 denotes a layout area extending over the first and second areas 21 and 24 adjacent to each other, and 11 to 14 denote grid lines (priority wiring directions) from the first layer wiring to the fourth layer wiring.

In this embodiment, the first and second regions 21 and 21 are used.
In any of 4, the first and second layer wirings are formed on the common orthogonal grids 11 and 12 so as to be orthogonal to each other. The third and fourth layer wirings of the present embodiment in the first region 21 are formed on the inclined grids 13 and 14, similarly to the third and fourth layer wirings shown in FIG. Is done.
On the other hand, the wirings of the third and fourth layers of the present embodiment in the second region 24 are the same as those of the fifth and sixth layers shown in FIG. Formed on top.

According to the present embodiment, a multilayer wiring structure suitable for the function and characteristics of each region can be realized by selectively adopting the inclined grid.

[0027]

As described above, according to the present invention, a multilayer wiring structure in which orthogonal grids and inclined grids are alternately employed is adopted, and all the intersections of the upper wiring overlap the intersections of the lower wiring grid. Since it is located at the position, not only crosstalk between different-layer wirings due to miniaturization can be reduced, but also wiring efficiency can be improved by using stacked vias.

[Brief description of the drawings]

FIG. 1A is a diagram illustrating a wiring structure from a first layer to a fourth layer of a six-layer wiring semiconductor integrated circuit according to a first embodiment of the present invention, and FIG. It is a schematic diagram which respectively shows the wiring structure of the 3rd layer-the 6th layer.

FIG. 2A is a diagram illustrating a wiring structure from a first layer to a fourth layer of a six-layer wiring semiconductor integrated circuit according to a second embodiment of the present invention, and FIG. It is a schematic diagram which respectively shows the wiring structure of the 3rd layer-the 6th layer.

FIG. 3 is a schematic diagram showing a wiring structure of a four-layer wiring semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4A is a block diagram showing an overall configuration of a four-layer wiring semiconductor integrated circuit according to a fourth embodiment of the present invention;
FIG. 2B is a schematic diagram showing an enlarged part of a wiring structure in the semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Layout area 11 Grid line of 1st layer wiring 12 Grid line of 2nd layer wiring 13 Grid line of 3rd layer wiring 14 Grid line of 4th layer wiring 15 Grid line of 5th layer wiring 16 Grid of 6th layer wiring Line 20 Semiconductor integrated circuit 21 Function block (first area) 22 Hard block 23 IO cell 24 Wiring area (second area) a Unit wiring pitch of first layer b Unit wiring pitch of second layer c Third layer D Unit wiring pitch of the fourth layer e Unit wiring pitch of the fifth layer f Unit wiring pitch of the sixth layer

Claims (4)

[Claims] 1. A multilayer wiring semiconductor integrated circuit having a wiring structure of at least six layers, wherein first and second wiring layers are formed on an orthogonal grid so as to be orthogonal to each other. The unit wiring pitch of the second layer is a and b respectively, n and m are each an even number of 2 or more, and ar
When an angle equal to ctan (na / mb) is θ,
The third layer wiring is inclined in the + θ direction with respect to the first or second layer wiring, and the fourth layer wiring is in the −θ direction with respect to the first or second layer wiring. When the unit wiring pitches of the third and fourth layers are c and d, respectively, c = d = na × mb / ｛(na) ² +
(Mb) ² ｝ ^1/2 , and all the intersections of the wirings of the third and fourth layers are located at positions overlapping with the intersections of the orthogonal grids of the wirings of the first and second layers. , The wiring of the sixth layer is formed on a coarse orthogonal grid that is a subset of the orthogonal grid of the wiring of the first and second layers, and the unit wiring pitch of the fifth and sixth layers is e, respectively. And f, e = na and f = mb, and all the intersections of the fifth and sixth layers of wiring are the intersections of the inclined grids of the third and fourth layers of wiring. A multilayer wiring semiconductor integrated circuit, which is located at an overlapping position. 2. A multilayer wiring semiconductor integrated circuit having a wiring structure of at least four layers, wherein first and second wiring layers are formed on an orthogonal grid so as to be orthogonal to each other. The unit wiring pitch of the second layer is a and b, respectively, and n and m are each an even number (n,
m is at least 4 or an even number) and arct
When an angle equal to an (na / mb) is θ, the third
The wiring of the layer is + θ with respect to the wiring of the first or second layer.
Direction, and the fourth layer wiring is the first or second wiring.
When the unit wiring pitch of the third and fourth layers is c and d, respectively, c = d = na × mb. / ｛(Na) ² +
(Mb) ² ｝ ^1/2 , and all intersections of the third and fourth layers of wiring are located at positions overlapping with intersections of orthogonal grids of the first and second layers of wiring. A multilayer wiring semiconductor integrated circuit characterized by the above-mentioned. 3. A multilayer wiring semiconductor integrated circuit having a wiring structure of at least four layers, wherein the wirings of the first and second layers are orthogonal to each other in any of the first and second regions adjacent to each other. , The unit wiring pitches of the first and second layers are a and b, n and m are each an even number of 2 or more, and ar
When an angle equal to ctan (na / mb) is θ,
In the first region, the third-layer wiring is the first or second wiring.
The wiring of the fourth layer is formed on the inclined grid so as to be inclined in the + θ direction with respect to the wiring of the layer, and the wiring of the fourth layer is inclined in the −θ direction with respect to the wiring of the first or second layer. Assuming that the unit wiring pitches of the third and fourth layers in the first region are c and d, c = d = na × m
b / ｛(na) ² + (mb) ² ｝ ^{1/2 In} the second region, the third and fourth layers of wiring are orthogonal grids of the first and second layers of wiring. All intersections of the third and fourth layers of wiring in the first and second regions are formed on a coarse orthogonal grid that forms a subset, and are orthogonal to the first and second layers of wiring. A multilayer wiring semiconductor integrated circuit, which is located at a position overlapping an intersection of a grid. 4. The multilayer wiring semiconductor integrated circuit according to claim 3, wherein unit pitches of the third and fourth layers in the second region are na and mb, respectively. circuit.